JP2591849B2 - Test circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit suitable for testing the operation speed of a high-speed digital circuit or the like.

[Prior Art] Conventionally, a test of an operation speed of a semiconductor integrated circuit is generally performed using a general-purpose tester.

FIG. 5 is a block diagram for explaining a conventional method for testing a semiconductor integrated circuit.

That is, when testing a logic circuit 71 built in a semiconductor integrated circuit 70, which is a test sample, conventionally, a test data and a clock from a pattern generator of a general-purpose tester are applied to a data input terminal 72 and a clock input terminal 73, respectively. CK
Supplying the door, and the output data D ₀ output from the data output terminal 74 is supplied to the pattern analyzer universal tester. Then, by comparing the output data D _0, which is actually obtained with the expected value pattern provided in the pattern analyzer, so that to determine the acceptability of the test sample.

[Problems to be Solved by the Invention] By the way, general-purpose testers are generally
Since a common test board is used and an auxiliary circuit or the like for switching a plurality of measurement systems is included, the load impedance parasitic on its terminal becomes extremely heavy as compared with a normal use condition of a test sample.

For this reason, in particular, when a high-speed clock signal CK is input to the clock input terminal 73, the pattern waveform of the general-purpose tester itself has a sufficient driving capability, so that the data input terminal 72 and the clock input terminal 73 have correct waveforms. The waveform output from the output terminal 74 is input but the logic circuit 71 does not have sufficient ability to drive the load 75 parasitic on the output terminal 74, and as shown in FIG. The result is a dull waveform.

Therefore, the conventional method using a pattern analyzer of a general-purpose tester has a problem that a correct determination result cannot be obtained. In addition, when the operation speed of the logic circuit 71 is tested, there is a problem in that the influence of the load 75 is too large to obtain a correct test result.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a test circuit that can correctly test the operation speed of a semiconductor integrated circuit even when a general-purpose tester is used.

[Means for Solving the Problems] A test circuit according to the present invention is a test circuit provided together with a logic circuit to be tested inside a semiconductor integrated circuit,
Frequency dividing means for dividing a clock signal, a delay circuit for delaying an output of the frequency dividing means by a delay time corresponding to the number of gate stages of the logic circuit to be tested, and an output of the delay circuit and the frequency dividing means And a flip-flop for latching the output of the gate circuit in synchronization with the clock signal.

[Operation] According to the present invention, by supplying the clock signal to the frequency dividing means, a frequency-divided output which is inverted at the rising timing of the clock signal is obtained from the frequency dividing means. This divided output is delayed by a delay circuit having a delay characteristic corresponding to the number of gate stages of the logic circuit to be tested. And
Since the exclusive logic of the delay output and the divided output is obtained by the gate circuit, a signal having a pulse width corresponding to the delay time can be obtained from the gate circuit.
By latching this signal at the falling timing of the clock signal, for example, it is possible to obtain a logical value that is fixedly determined depending on whether the delay time is longer or shorter than 1/2 of the clock cycle.

According to the present invention, the delay amount to be tested can be determined based on a fixed logic level, so that a correct determination result can be obtained without being affected by the load impedance parasitic on the output terminal.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a configuration of a test circuit according to an embodiment of the present invention.

As shown in FIG. 3, the test circuit 1 is provided in a semiconductor integrated circuit 10 together with a logic circuit 11 to be tested, and has the following configuration.

That is, a clock signal CK from a pattern generator of a general-purpose tester (not shown) is input from the input terminal 2, and the clock signal CK is input to the T-type flip-flop 3. The T-type flip-flop 3 constitutes frequency dividing means, and inverts its output level in synchronization with the rise of the clock signal CK. The output signal A of the T-type flip-flop 3 is delayed by the delay circuit 4 for a predetermined time. Then, the output signal B from the delay circuit 4 and the output signal A are input to an exclusive OR (hereinafter, referred to as EX-OR) gate 5, and the exclusive OR of both is obtained. I have. The output signal C from the EX-OR gate 5 is input to the data terminal of the D-type flip-flop 6. The clock signal input from the input terminal 2 is supplied to the clock input terminal of the D-type flip-flop 6. D-type flip-flop 6
The output signal C is latched at the timing of the falling edge of the clock signal CK, the output as a test output signal O _T, and outputs from an output terminal 7.

Next, the operation of the test circuit 1 according to the present embodiment configured as described above will be described.

FIG. 2 is a timing chart showing the operation of the test circuit 1.

When the clock signal CK is input to the input terminal 2, the T-type flip-flop 3 divides the frequency of the clock signal CK by 1/2 and outputs an output signal A. Since the output signal A is delayed by the delay circuit 4 for a predetermined time, the delay circuit 4 outputs an output signal B obtained by delaying the output signal A as illustrated. When these output signals A and B are supplied to the EX-OR gate 5, E
The X-OR gate 4 outputs an output signal C which becomes high only during a period when the levels of both signals are different. This output signal C is latched by the D-type flip-flop 6 at the falling timing of the clock signal CK.

Here, the delay time from the rise of the clock signal CK to the fall of the delay output signal C is T _d ,
Assuming that the cycle of CK is T and the duty ratio is 50%, under the condition of T _d <T / 2, as shown in FIG. 2A, the EX-OR gate 5 before the clock signal CK falls. , The D-type flip-flop 6 always latches the low level period of the output signal C. Thus, the test output signal O _T will be fixed to a low level.

On the other hand, as shown in FIG. 2 (d), under the condition of T _d ≧ T / 2, the output signal C of the EX-OR gate 5 has not yet fallen at the time when the clock signal CK falls. The type flip-flop 6 always latches the high level period of the output signal C. Thus, the test output signal O _T will be fixed to a high level.

By the way, the delay time _Td by the T-type flip-flop 3 and the delay circuit 4 is fixed depending on the test sample. Therefore, by performing the test while keeping the clock cycle T constant, the first state ( _Td < _{Td) can be obtained.} / 2) or the second state (T _d ≧ T / 2) can be determined based on the level of the output terminal 7.

FIG. 3 is a block diagram showing an example in which the above-described test circuit 1 is built in an actual semiconductor integrated circuit 10. Test data is input from a data input terminal 12 to a logic circuit 11 to be tested inside the semiconductor integrated circuit 10. Output data output from the logic circuit 11 is output to the outside via the data output terminal 14. On the other hand, the clock signal CK input from the outside via the clock input terminal 13 is input to the clock input terminal of the logic circuit 11 and is also input to the test circuit 1. Test output signal O _T output from the test circuit 1 has a what is output to the outside via the test output terminal 15.

When performing a general-purpose test of the semiconductor integrated circuit 10 configured as described above, the duty ratio is input to the clock input terminal 13.
A clock signal CK having a period T of 50% is supplied. Then, the level of the test output terminal 15 is determined. If the level is low, the first state can be determined, and if the level is high, the second state can be determined.

At this time, high impedance loads 16 and 17 by the general-purpose tester are parasitic on the output terminals 14 and 15, respectively.However, the output of the test output terminal 15 itself is fixed at a low level or a high level, and is affected by this. The determination can be made without any need.

Next, a specific configuration example of the delay circuit 4 will be described with reference to FIG.

FIG. 4A is a block diagram showing a critical path included in the logic circuit 11 of FIG. That is, the logic circuit 21 configured between the D-type flip-flops 20 and 22
Is composed of active elements 31, 34, 37, 40 and a number of passive elements 32, 33, 35, 36, 38, 39 parasitic thereon. And
It is assumed that a critical path is formed from the flip-flop 20 to the flip-flop 22 via the logic circuit 21, and the operation speed of the entire logic circuit 11 is determined by this.

When the critical path of the logic circuit 11 has the above configuration, the delay circuit 4 includes the active elements 51 and 54 equivalent to the active elements forming the logic circuit 21 and the passive elements parasitic thereto.
57, 60 and similar passive elements 52, 53, 55, 5
6,58,59. Then, the other inputs of the active element 54 and the active elements 57 and 60 are fixed to a low level and a high level, respectively, so that the critical path formed by these elements is opened.

As a result, the delay time of the delay circuit 4 is
Is substantially equal to the delay time of the critical path. Further, the delay time from the clock input of the D-type flip-flop 20 is substantially equal to the delay time from the clock input of the T-type flip-flop 3 in the test circuit 1 of the present invention. Is substantially equal to the above-described time _Td .

[Effects of the Invention] As described above, according to the present invention, the relationship between the delay time and the clock cycle in a delay circuit having delay characteristics corresponding to the number of gate stages of a logic circuit to be tested is fixed. Thus, the operating speed of the semiconductor integrated circuit can be accurately determined without being affected by the output load impedance.

According to the present invention, the function test of the logic circuit built in the semiconductor integrated circuit may be performed with a low-frequency signal pattern. Even when a general-purpose tester is used, the function test is performed together with the above-described operation speed test. This has the effect that the quality of the semiconductor integrated circuit can be determined with high accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram of a test circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the test circuit,
FIG. 3 is a block diagram showing a semiconductor integrated circuit incorporating the test circuit, FIG. 4 is a block diagram showing a specific example of the semiconductor integrated circuit, FIG. 5 is a block diagram of a conventional semiconductor integrated circuit, and FIG. Is a waveform diagram at the time of testing the circuit. 1; test circuit, 2; input terminal, 3; T-type flip-flop,
4; delay circuit, 5; EX-OR gate, 6, 20, 22; D-type flip-flop, 7; output terminal, 10, 70; semiconductor integrated circuit, 11, 21, 7
1; logic circuit, 12; data input terminal, 13; clock input terminal, 14; data output terminal, 15; test output terminal, 16, 17, 7
5; load,

Claims (1)

(57) [Claims] 1. A test circuit provided in a semiconductor integrated circuit together with a logic circuit to be tested, wherein the frequency divider divides a clock signal, and an output of the frequency divider is a logic circuit to be tested. A delay circuit for delaying by a delay time corresponding to the number of gate stages, etc., a gate circuit for outputting an exclusive logic of the output of the delay circuit and the output of the frequency dividing means, and an output of the gate circuit as the clock signal. A test circuit comprising: a flip-flop that latches in synchronization.