JP2947178B2 - Clock skew judgment circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock skew determination circuit, and more particularly to a clock skew determination circuit for determining a clock skew failure of a microprocessor.

[0002]

2. Description of the Related Art In recent years, the number of microprocessors operating in synchronization with a plurality of clocks has been increasing. A clock skew occurs between a plurality of clocks used in the microprocessor due to a delay in a circuit in the microprocessor or a difference in clock drive capability, but when the clock skew becomes a design value or more, the signal becomes skewed. In the cylinder, which is a factor that hinders the normal operation of the microprocessor.

Conventionally, this type of clock skew determination is performed by directly outputting an internal clock to an external terminal and observing the output at the corresponding terminal using an oscilloscope to measure the internal clock or directly compare the internal clocks. The output signal is output to an external terminal, and the internal clock is measured by observing the output at the corresponding terminal using an oscilloscope. This has been done by directly measuring the internal clock using an oscilloscope.

FIG. 5 is a circuit block diagram showing a configuration example of a conventional clock skew determination circuit.

In this conventional example, as shown in FIG. 5, frequency dividers 500 and 501 for dividing an input clock signal, a clock signal divided by the frequency divider 500 and a frequency divider 50 are used.
It comprises an XOR gate 503 which takes an exclusive OR with the clock signal divided in 1 and an output terminal 502 which outputs the exclusive OR obtained by the XOR gate 503.

Hereinafter, the operation of the clock skew determination circuit configured as described above will be described.

First, the frequency divider 500 receives the first clock signal CLK1 and the frequency divider 501 receives the second clock signal CLK1.
2 are input, the frequency divider 500 outputs the clock signal C1 having the same phase as the clock signal CLK1 and the duty 50%, and the frequency divider 501 has the duty 50% and the same phase as the clock signal CLK2.
Is output.

Next, the clock signal C1 output from the frequency divider 500 and the clock signal C2 output from the frequency divider 501 are input to the XOR gate 503, where the clock signal C1 and the clock signal C2 are output.
Of the output terminal 50
2, a high-level pulse having the width of the clock skew generated between the clock signal CLK1 and the clock signal CLK2 is output.

Then, by observing the high level time of the pulse output to the output terminal 502,
The clock skew generated between the clock signal CLK1 and the clock signal CLK2 is determined.

[0010]

However, in the conventional clock skew determination circuit as described above,
There are problems as described below.

(1) A clock skew determination circuit for measuring an internal clock by directly outputting an internal clock to an external terminal and observing the output at the corresponding terminal using an oscilloscope and directly measuring a plurality of clocks externally. Although the clock skew is determined, since the clock is measured directly, it is affected by various external noises, which makes accurate measurement difficult.

(2) A signal obtained by directly comparing the internal clocks with each other is output to an external terminal, and the output at the corresponding terminal is observed using an oscilloscope. In order to determine whether or not the internal clock is within the designed skew, high measurement accuracy is required when measuring an output signal using an oscilloscope or the like.

(3) A plurality of clocks are directly measured externally by a clock skew determination circuit which performs a needle setting on a clock line on a chip and directly measures an internal clock using an oscilloscope in a portion where the needle setting is performed. The clock skew is determined according to the following formula, but since the clock is measured directly, it is affected by various external noises, which makes accurate measurement difficult.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and provides a clock skew determination circuit capable of accurately and easily determining a clock skew inside a microprocessor. The purpose is to do.

[0015]

Means for Solving the Problems In order to achieve the above object, the present invention provides a first clock signal and a second clock signal.
Clock to determine the clock skew that occurs between
A skew determination circuit that latches an input signal with a first clock signal and outputs a different signal level before and after the latch; and a signal output from the first latch circuit in advance. A delay circuit that delays and outputs the signal by a predetermined time, a second latch circuit that latches and outputs a signal output from the delay circuit with a second clock signal, and a signal that is output from the first latch circuit Inputting the signal and the signal output from the second latch circuit
A logic gate that takes a logic, and a skew generated between the first clock signal and the second clock signal exceeds a clock skew design time based on a pulse width output from the logic gate. Or not.

Further, the first clock signal and the second clock signal
Clock skew between the clock signal
In the lock skew determination circuit, the input signal is latched by the first clock signal , and different signal levels are obtained before and after the latch.
A first latch circuit that outputs a bell, a plurality of delay circuits that delay the signal output from the first latch circuit by a predetermined time respectively set, and output the delayed signal, and a plurality of delay circuits that output the signal output from the plurality of delay circuits. A selection circuit for selecting and outputting one signal from the selected signals, a second latch circuit for latching and outputting a signal output from the selection circuit by a second clock signal, Inputting the output signal and the signal output from the second latch circuit ,
A logic gate that takes logic, and a skew generated between the first clock signal and the second clock signal is selected by the selection circuit based on a pulse width output from the logic gate. The skew amount generated between the first clock signal and the second clock signal is measured by determining whether or not the delay time in the delay circuit has been exceeded.

Further, the microprocessor is built in the microprocessor.

(Operation) In the present invention configured as described above, the test signal for determining the clock skew is latched and output at the rising edge of the first clock signal in the first latch circuit, and the first latch circuit outputs the test signal. A signal latched and output by the circuit is output after being delayed by a predetermined time in a delay circuit, and the signal delayed in the delay circuit is latched and output by a second latch circuit at a rising edge of a second clock signal, and the first latch is output. The signal output from the circuit and the signal output from the second latch circuit are input to a logic gate, and the logic gate outputs the signal output from the first latch circuit and the signal output from the second latch circuit. AND operation is performed, and based on the result, a skew defect occurring between the first clock signal and the second clock signal. Constant is performed.

As described above, the problem determination of the clock skew generated between the first clock signal and the second clock signal due to the pulse width of the output signal using the first clock signal and the second clock signal. Is performed, the clock skew inside the microprocessor can be accurately and easily determined without being affected by various external noises.

A plurality of delay circuits having different delay times are provided, and a second one of the signals output from the plurality of delay circuits is provided.
When a selection circuit for selecting a signal input to the latch circuit is provided, the selection circuit selects a signal input to the second latch circuit from signals output from the plurality of delay circuits, and The amount of clock skew between the first clock signal and the second clock signal is measured by referring to the clock skew determination result at that time.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit block diagram showing a first embodiment of a clock skew determining circuit according to the present invention.

In this embodiment, as shown in FIG. 1, a clock skew test signal S for determining clock skew is used.
The first and first clock signals CLK1 are input, a first latch circuit 100 that latches and outputs the clock cue test signal S1 as a signal S2 when the clock signal CLK1 rises, and a signal S2 output from the latch circuit 100 is predetermined. A delay circuit 102 that outputs the signal S3 with a delay by a time, and a second latch circuit 101 that receives the signal S3 and the second clock signal CLK2 and latches and outputs the signal S3 as a signal S4 when the clock signal CLK2 rises. And an AND gate 104 to which the signal S4 output from the latch circuit 101 and the signal S2 output from the latch circuit 100 are input, AND the signal S2 and the signal S4, and output as a signal S5;
And an output terminal 103 for outputting the signal S5 output from the AND gate 104 to the outside.

Hereinafter, the operation of the clock skew determining circuit configured as described above will be described.

First, when the clock skew test signal S1 and the clock signal CLK1 are input to the latch circuit 100, the clock signal CLK
1 at the rise of the clock cue test signal S
1 is latched and output as a signal S2.

Next, the signal S2 output from the latch circuit 100 is input to the delay circuit 102, where the signal S2 is delayed by a predetermined time and output as a signal S3.

Next, the signal S3 and the clock signal CLK2 output from the delay circuit 102 are input to the latch circuit 101, and the latch circuit 101 outputs the clock signal CLK.
The signal S3 is latched and output as the signal S4 at the rise of the signal S2.

Next, the signal S4 output from the latch circuit 101 is input to the AND gate 104. Where A
The signal S2 output from the latch circuit 100 is also input to the ND gate 104. The AND gate 104 obtains the logical product of the signal S2 and the signal S4, and
5 is output.

Then, by measuring the high level time of the pulse output to the output terminal 103,
The clock skew generated between the clock signal CLK1 and the clock signal CLK2 is determined.

Hereinafter, the operation of the above-described clock skew determination circuit will be described in detail with reference to the drawings.

FIG. 2 is a timing chart in the case where the clock skew is within the range of the design value in the clock skew determination circuit shown in FIG.

The test signal S1 is latched and output as a signal S2 at the rising edge of the clock signal CLK1 in the latch circuit 100 (point 200).

The signal S2 latched by the clock signal CLK1 is delayed by a predetermined time in the delay circuit 102 and output as a signal S3 (point 201).

Signal S3 output from delay circuit 102
Is latched as a signal S4 at the rising edge of the clock signal CLK2 in the latch circuit 101 (point 20).
2). At this time, since the clock skew between the clock signals CLK1 and CLK2 is within the range of the design value, the state before the signal S3 changes is latched and output.

The value after the change of the signal S3 is the clock signal C
At the next rising of LK2, it is latched and output (point 203).

The logical product S5 of the signal S2 and the signal S4 has a small pulse waveform within the range of the design value of the clock skew (point 204).

FIG. 3 is a timing chart in the case where the clock skew exceeds the design value range in the clock skew determination circuit shown in FIG.

The test signal S1 is latched and output as a signal S2 at the rising edge of the clock signal CLK1 in the latch circuit 100 (point 300).

The signal S2 latched by the clock signal CLK1 is delayed by a predetermined time in the delay circuit 102 and output as a signal S3 (point 301).

Signal S3 output from delay circuit 102
Is latched as a signal S4 at the rising edge of the clock signal CLK2 in the latch circuit 101 (point 30).
2). At this time, since the clock skew between the clock signal CLK1 and the clock signal CLK2 exceeds the range of the design value, the state after the signal S3 has changed is latched and output.

The logical product S5 of the signal S2 and the signal S4 has a large pulse waveform which is larger than the width of the clock signal (point 303).

As described above, the clock skew can be determined only by checking whether the output signal has a pulse larger than the internal clock without using an oscilloscope or the like.

(Second Embodiment) FIG. 4 is a circuit block diagram showing a clock skew determination circuit according to a second embodiment of the present invention, in which the amount of clock skew can be measured. .

In this embodiment, as shown in FIG. 4, a clock skew test signal S for determining clock skew is used.
The first and second clock signals CLK1 are input, the first latch circuit 400 latches and outputs the clock cue test signal S1 as the signal S2 when the clock signal CLK1 rises, and the signal S2 output from the latch circuit 400, respectively. And a plurality of delay circuits 402-1 to 402-n which respectively output signals X1 to Xn after being delayed by a predetermined time set in
A selection circuit 405 that selects one signal from the signals X1 to Xn output from 02-n and outputs it as a signal S3
And the signal S3 and the second clock signal CLK2 output from the selection circuit 405 are input, and the clock signal CLK
A second latch circuit 401 that latches and outputs the signal S3 as the signal S4 at the rise of the second latch circuit 4;
01 and the signal S2 output from the latch circuit 100 are input, and the signal S2 and the signal S4
AND gate 404 which takes the logical product of the AND and outputs the signal S5 and the signal S output from the AND gate 404
5 to the outside.

Hereinafter, the operation of the clock skew determining circuit configured as described above will be described.

First, when the clock skew test signal S1 and the clock signal CLK1 are input to the latch circuit 400, the clock signal CLK
1 at the rise of the clock cue test signal S
1 is latched and output as a signal S2.

Next, the signal S2 output from the latch circuit 400 is input to the delay circuits 402-1 to 402-n.
In the delay circuits 402-1 to 402-n, the signal S2
Are output as signals X1 to Xn after being delayed by a predetermined time set for each. The delay circuit 40
In 2-1 to 402-n, different delay times are set.

Next, the signals X1 to Xn output from the delay circuits 402-1 to 402-n are input to the selection circuit 405, where the delay amount selection signals Y1 to Yn are output.
One of the signals X1 to Xn is selected by n, and is output as a signal S3.

Next, the signal S3 and the clock signal CLK2 output from the selection circuit 405 are input to the latch circuit 401.
The signal S3 is latched and output as the signal S4 at the rise of the signal S2.

Next, the signal S 4 output from the latch circuit 401 is input to the AND gate 404. Where A
The signal S2 output from the latch circuit 400 is also input to the ND gate 404. The AND gate 404 calculates the logical product of the signal S2 and the signal S4, and outputs the signal S2.
5 is output.

Thereafter, by measuring the high level time of the pulse output to the output terminal 403,
The clock skew generated between the clock signal CLK1 and the clock signal CLK2 is determined.

Here, in the present embodiment, the selection circuit 40
5, the signal S3 input to the latch circuit 401 is the signal X output from the delay circuits 402-1 to 402-n.
Since it is selected from 1 to Xn, it is possible to measure the amount of clock skew between the clock signal CLK1 and the clock signal CLK2.

For example, if the delay amount of the delay circuit 402-1 is 1
0 ns, the delay amount of the delay circuit 402-2 is 11 ns, and the determination result of the clock skew when the signal X1 output from the delay circuit 402-1 is selected by the selection circuit 405 exceeds the design value. When the selection result of the clock skew when the signal X2 output from the delay circuit 402-1 is selected by the selection circuit 405 is within the design value, the clock signal CLK1 and the clock signal CLK2 are obtained. It can be seen that the clock skew is 10 ns or more and less than 11 ns.

[0054]

Since the present invention is constructed as described above, it has the following effects.

According to the first aspect of the present invention, a pulse generated between the first clock signal and the second clock signal by a pulse width of an output signal using the first clock signal and the second clock signal. In this configuration, the clock skew defect determination is performed, so that the clock skew inside the microprocessor can be accurately and easily determined without being affected by various external noises.

According to the second aspect of the present invention, a plurality of delay circuits having different delay times are provided, and a selection circuit selects a signal input to the second latch circuit from signals output from the plurality of delay circuits. Since the circuit is provided, the selection circuit selects the signal input to the second latch circuit from the signals output from the plurality of delay circuits, and refers to the determination result of the clock skew at that time, thereby obtaining The amount of clock skew between the first clock signal and the second clock signal can be measured.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of a clock skew determination circuit according to the present invention.

FIG. 2 is a timing chart in the case where the clock skew is within a design value range in the clock skew determination circuit shown in FIG.

FIG. 3 is a timing chart in a case where a clock skew exceeds a design value range in the clock skew determination circuit shown in FIG. 1;

FIG. 4 is a circuit block diagram illustrating a clock skew determination circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit block diagram illustrating a configuration example of a conventional clock skew determination circuit.

[Explanation of symbols]

 100, 101, 400, 401 Latch circuit 102, 402-1 to 402-n Delay circuit 103, 403 Output terminal 104, 404 AND gate 200 to 204, 300 to 303 Observation point 405 Selection circuit

Claims (3)

(57) [Claims] 1. A first clock signal and a second clock signal.
Clock to determine the clock skew that occurs between
A skew determination circuit that latches an input signal with a first clock signal and outputs a different signal level before and after the latch; and a signal output from the first latch circuit in advance. A delay circuit that delays and outputs the signal by a predetermined time, a second latch circuit that latches and outputs a signal output from the delay circuit with a second clock signal, and a signal that is output from the first latch circuit Inputting the signal and the signal output from the second latch circuit
A logic gate that takes a logic, and a skew generated between the first clock signal and the second clock signal exceeds a clock skew design time based on a pulse width output from the logic gate. A clock skew determination circuit for determining whether the clock skew has occurred. 2. A first clock signal and a second clock signal.
Clock skew generated between
In the skew determination circuit, the input signal is latched by the first clock signal , and different signal levels are obtained before and after the latch.
, A plurality of delay circuits for delaying a signal output from the first latch circuit by a predetermined time respectively set and outputting the same, and a plurality of delay circuits output from the plurality of delay circuits. A selection circuit for selecting and outputting one signal from signals, a second latch circuit for latching and outputting a signal output from the selection circuit by a second clock signal, and an output from the first latch circuit Inputting the output signal and the signal output from the second latch circuit, and
And a skew generated between the first clock signal and the second clock signal is selected by the selection circuit based on a pulse width output from the logic gate. A skew amount generated between the first clock signal and the second clock signal by determining whether or not a delay time in a delayed delay circuit has been exceeded. . 3. The clock skew determination circuit according to claim 1, wherein the clock skew determination circuit is built in the microprocessor.