JP3430056B2 - Integrated circuit including delay test facilitating circuit and path delay test method for integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit incorporating a circuit for measuring a signal propagation delay time (path delay) of a specific path, and a path delay test method in the integrated circuit.

[0002]

2. Description of the Related Art As a test method for an integrated circuit, there is a path delay test method for measuring the delay amount of a critical path in a circuit by using a scan-designed circuit. This is because the condition for activating a signal path (critical path) having the largest delay amount in the circuit obtained by the static timing analysis in the process of designing the LSI is found, and the scan path FF (flip-flop) This is a method of activating only the critical path by setting a signal value in the actual circuit by the shift operation, measuring the delay amount, and testing whether there is a problem in the operating speed of the actual circuit.

A specific method will be described with reference to FIG. The circuit example is composed of a scan FF and a simple gate. The critical path in the circuit is the source scan F
The path of F21, AND gate 25, OR gate 26, NOT gate 27, OR gate 28, AND gate 29, and target scan FF 22. At this time, in order to activate the critical path, it is necessary to determine the signal value of the other terminal of each gate in the path.
The other terminal of the AND gate 25 is "1", and the OR gate 2
The other terminal of 6 is set to "0", the other terminal of the OR gate 28 is set to "0", and the other terminal of the AND gate 29 is set to "1". These are performed by back-tracing the circuit connection from each terminal and setting the value of the scan FF 23 that can control each. At this time, all the scan FFs operate with a common external clock, so that it is necessary to determine the value of the scan FF 24 of the second stage (first stage before) so that the activation condition is not destroyed. This is because it is necessary to maintain each set value for one clock period during which the scan test is performed.

Next, the timing waveform of the path delay test will be described with reference to FIG. Each scan FF23
The initial value of the scan FF 24 is assumed to be set to "0" or "1" by the scan shift operation as shown in FIG. At this time, 1 from the external clock terminal
When the generation pulse is input, the source scan FF 21 changes from "0" to "1" with a delay of the circuit delay. Next, in response to the signal of the output value “1” of the source scan FF 21, the output of the AND gate 25 at the next stage is delayed by the delay of the circuit to “0”.
Becomes "1". Similarly, a signal propagates to the OR gate 26, NOT gate 27, OR gate 28, and AND gate 29. After the output of the AND gate 29 at the final stage changes to "0", when the second pulse is input from the external clock terminal, the target scan FF 22 takes in "0". However, when the second pulse is input from the external clock terminal before the output of the AND gate 29 changes to "0", the target scan FF 22 takes in "1". It is possible to obtain the path delay value from the source scan FF 21 to the target scan FF 22 by repeating the test by changing the pulse width 30 input from the external clock terminal in several ways.

However, the number of gate stages of the critical path of an actual LSI is large, and it is not possible to determine the conditions of the scan FFs for two stages connected to them in order to activate the path. The CAD processing for generation becomes complicated, and depending on the circuit configuration, it may not be possible to determine the conditions on the logic.

Therefore, as a method for facilitating the condition setting, some circuits have been proposed in which the activation condition is not destroyed even by setting the scan FF for one stage.

In Japanese Patent Laid-Open No. 3-61872, as shown in FIG. 9, a circuit capable of suppressing the application of a clock to a scan FF other than a source scan FF and a target scan FF is added to perform a path delay test. Sometimes, a clock is supplied only to the source scan FF and the target scan FF so that the activation condition is not destroyed. Further, in Japanese Unexamined Patent Publication No. 8-313597, as shown in FIG. 10, a scan FF having a structure capable of holding the previous data is used to activate one scan FF. It is shown that the conditions of (1) are not destroyed.

[0008]

As a technique for preventing the activation condition of each gate of the critical path from being waved only by setting the scan FF for one stage at the time of performing the path delay test, the above-mentioned Japanese Patent Laid-Open Publication No. Hei 3 (1999) -311. There is a method of adding a circuit capable of suppressing the application of the clock in Japanese Patent Laid-Open No. 61872, but this method requires a control circuit for testing to be inserted in the clock line. Since it is separated into two and recognized as separate clocks, it becomes an asynchronous design. In the asynchronous design, it is difficult to guarantee the clock skew, and there is a problem that the clock tree synthesis, which is an automatic layout technology for LSI, cannot be applied.

Further, in the method using a special scan FF as in Japanese Patent Laid-Open No. 8-313597, it is necessary to newly develop a scan cell, and when it is actually incorporated in an LSI, the number of circuits increases greatly. There was a drawback.

The present invention does not complicate the circuit configuration.
An object of the present invention is to provide a delay test facilitation circuit and a test method capable of performing a path delay test only by setting scan FFs for a number of stages.

[0011]

According to a first aspect of the present invention, there is provided an integrated circuit having a path delay test facilitation circuit for measuring a signal propagation delay time of a specific path from a source flip-flop to a target flip-flop, The state setting flip-flop for setting the state for each gate in the specific path is configured by a flip-flop capable of selectively latching a D input or a shift input, and
When the shift input is set to be latched, each state setting flip-flop is scan-connected so that the output of each state setting flip-flop does not change even if it is shifted once.

According to a second aspect of the present invention, there is provided an integrated circuit having a built-in path delay test facilitating circuit for measuring a signal propagation delay time of a specific path from a source flip-flop to a target flip-flop, wherein each of the specific paths is provided. A state setting flip-flop for setting a state to a gate is formed of a flip-flop capable of selectively latching a D input or a shift input, and the state setting flip-flop has an activation condition of "1". It is characterized in that it is classified into a group of "0" and a group of "0", and scan connection is performed for each group.

According to a third aspect of the present invention, in addition to the state setting flip-flop, the source flip-flop is composed of a flip-flop capable of selectively latching a D input or a shift input in addition to the state setting flip-flop. When the state of the flip-flops is changed from “1” to “0”, the group of “1” s, source flip-flops,
Scan connection is made in the order of “0” groups, and the state of the source flip-flop is set to “0” →
When it is set to "1", it is characterized in that the scan connection is made in the order of the "0" group, the source flip-flop, and the "1" group.

According to a fourth aspect of the present invention, in the integrated circuit of the first, second or third aspect, a condition for activating the specific path is set for each state setting flip-flop, and a source flip-flop is set. After inputting a first clock pulse for inverting the state of the target flip-flop, a second clock pulse for latching the input of the target flip-flop is input after a predetermined time, and the input of the target flip-flop is inspected to check the specific path. The signal propagation delay time is measured.

The invention of claim 5 is characterized in that the measurement procedure of claim 4 is repeatedly executed while changing the interval between the first clock pulse and the second clock pulse.

According to the present invention, the scan connection order of the state setting flip-flops is such that the condition for activating the critical path is not destroyed even if one clock pulse is input from the outside, and the value of the source flip-flop is set. Only "0" that triggers the path delay test
→ Make a configuration that changes from “1” or “1” to “0”.

By using the circuit of the present invention, the path delay test can be performed only by setting the condition of the one-stage state setting flip-flop, so that the condition for activating the critical path can be easily obtained by the CAD tool. . Further, it is not necessary to prepare a special scan cell, the existing scan FF can be used, and the path delay test can be performed by adding only a minimum number of test circuits. Further, in this circuit, since the clock system is not changed at all, the rule of the synchronous circuit design is not violated, and it is easy to suppress the clock skew.

[0018]

1 is a diagram showing a partial configuration of an LSI incorporating a delay test facilitation circuit according to an embodiment of the present invention. This LSI is a source scan FF1.
From the AND gate 11, the OR gate 12, the NOT gate 13, the OR gate 14, the AND gate 15, and the target scan FF 2 the delay value of the path is measured.

In the circuit shown in the figure, the SMC terminal for switching the scan mode / normal mode is connected to each scan FF. However, a test circuit for delay test composed of an AND circuit in the preceding stage of the SMC terminal of the target scan FF2. 3, a delay test mode setting terminal 9 for inputting a signal for controlling the test circuit 3, that is, a signal for opening and closing the AND circuit is provided. Further, the scan FFs for setting the path activation conditions are divided into a group 4 to be set to “1” and a group 5 to be set to “0”,
Connect a scan chain for each group.
That is, the Q terminal of the previous stage is connected to the SIN (scan I
N) Connect to the terminal. Further, in the case of this example, the source scan FF 1 needs a change condition of “0” → “1”.
As a configuration of the entire scan chain, a scan FF value “1” group 4, a source scan FF 1, a scan FF value “0” group 5, and a target scan FF 2
Connect the scan chains in order.

The connection order of scan FFs is such that after the circuit design is completed, the FFs existing in the circuit are replaced with scan FFs, and each scan including the critical path activation condition and the source and target is designed when the scans are connected. The scan order and the connection order with good test efficiency may be determined in consideration of the FF layout and the like.

Here, the scan F used in this circuit
The structure of F is shown in FIG. This scan FF is called a MUX type, and is a combination of a D flip-flop 17 and a multiplexer 16. The source scan FF1 and the target scan FF2 shown in FIG. 1 are of the same type as the scan FF shown in FIG. As shown in FIG. 3, when the SMC is “0”, the scan FF operates by latching the value of the D input at the rising edge of CK, and when SMC is “1”, the value of the SIN input at the rising edge of CK. Latch.

FIG. 4 shows a timing chart when executing a path delay test using the test circuit of the present invention. The timing is broadly divided into scan-in cycle 18, delay test cycle 19 and scan-out cycle 20.
It is classified into three. The timing operation at the time of executing the path delay test of FIG. 4 will be described with reference to the flowchart of FIG. 5 at the time of executing the path delay test using the test circuit of the present invention.

First, at s1, the SMC-IN terminal 7
Is set to "1" and the delay test mode setting terminal 9 is set to "1". As a result, the group 4 of "1", the source scan FF1, the group 5 of "0", and the target scan FF2 are all scan-connected. next,
The scan-in operation sets the state in each scan FF (s2). That is, "000111" is serially input from the SCAN-IN terminal 6 and the CK-IN terminal 8
By inputting a clock, the scan FF value of the group 4 having the scan FF value “1” is set to “111”, the value of the source scan FF 1 is set to “0”, and the scan FF value of the group 5 having the scan FF value “0” is set. To "00". This operation corresponds to the scan-in cycle 18 of FIG. After that, by inputting “0” from the delay test mode terminal 9, only the target scan FF 2 is selected to latch the input of the “D” terminal (s3). This allows a delay test cycle.

The delay test cycle is the operation shown in 19 of FIG. 4, and the source scan FF1 is operated by inputting two pulses of the clock from the external CK-IN8 (s4).
Signal is propagated to the path from the target scan FF2. Specifically, the shift operation occurs in the scan FF in the group 4 having the scan FF value “1”, the source scan FF 1, and the scan FF in the group 5 having the scan FF value “0” with the first pulse. In this operation, the value of the source scan FF1 changes from "0" to "1". The scan FFs in the group 4 having the scan FF value of "1" do not change from "1" even if one shift occurs by inputting "1" from SCAN-IN6. Further, even the scan FFs in the group 5 having the scan FF value “0” are “0” in one shift.
Has never changed. When the value of the source scan FF1 changes from "0" to "1", the output of the AND gate 11 which is the path for performing the target delay test becomes "0" → "1". Further, in response to the change in the output of the AND gate 11, the signal propagates to the next-stage OR gate 12, NOT gate 13, OR gate 14, and AND gate 15. When the second pulse is input from the external CK-IN8 after the propagation is completed, the target scan F
"0" is latched in F2. Before propagating backwards,
When the second pulse is input from the external CK-IN8,
"1" is latched in the target scan FF2.
Therefore, when the clock width of two pulses input from the external CD-IN 8 is longer than the delay value of the path, the value “0” after the change is latched, and when it is shorter than the delay value of the path,
The value "1" before the change is latched.

In the circuit example of FIG. 1, the target scan F
The output of F2 is connected to SCAN-OUT10, and the state of the target scan FF2 can be read directly from this terminal. And the first pulse and 2
The delay time of the path can be specified by repeating the above operation a plurality of times while changing the interval of the pulse of the second time.

If the output of the target scan FF2 cannot be directly taken out, the value of the target scan FF2 is read in the scan-out cycle 20 (s5), and whether "0" is latched or "1" is latched. To judge.

In the embodiment of FIG. 1, the target F
Although F2 has the circuit configuration shown in FIG. 2 and is connected to the end of the scan chain, the target FF2 does not need to be set at the start of the path delay test. Therefore, it is configured by a normal D flip-flop and removed from the scan chain. It is also possible. A circuit example in this case is shown in FIG.

In the above embodiment, the path delay test is performed by inverting the polarity of the input value to the critical path, that is, the source scan FF1 from "0" to "1". Which of the rising edge and the falling edge of the input signal is the worst for the critical path is obtained by simulation, etc., and “0” → “1” or “1” is selected according to the worst condition
→ Decide “0”. When “1” → “0” is set, the connection order of the scan chains is opposite to that shown in FIG. 1, and the group 5, the source scan FF 1, the group 4, and the target scan FF 2 are formed.

[0029]

According to the present invention, with a simple circuit configuration,
It is possible to easily perform a delay test of an integrated circuit,
The influence on the original functional operation of the integrated circuit can be suppressed to be small.

Then, by applying the present invention,
The delay amount of the critical path that actually exists in the integrated circuit can be accurately measured, the shipping quality of the integrated circuit can be improved, and if there is a problem with the delay amount, the pre-process of manufacturing can be performed accurately. You can give us feedback. Therefore, according to the present invention, it is possible to reduce the development cost of the integrated circuit and the shipping test cost at the time of manufacturing.

[Brief description of drawings]

FIG. 1 is a partial configuration diagram of an integrated circuit incorporating a delay test facilitation circuit according to an embodiment of the present invention.

FIG. 2 is a structural diagram of a scan FF.

FIG. 3 is a truth table of a scan FF.

FIG. 4 is a timing chart showing an operation during a path delay test.

FIG. 5 is a flowchart showing an operation during a path delay test.

FIG. 6 is a diagram showing another embodiment of the present invention.

FIG. 7 is a diagram showing a conventional technique of a path delay test method.

FIG. 8 is a timing diagram showing the concept of the path delay test method.

FIG. 9 is a diagram showing a typical example of a countermeasure circuit as a conventional technique.

FIG. 10 is a diagram showing a representative example of a conventional countermeasure circuit.

[Explanation of symbols]

1 ... Source scan FF 2 ... Target scan FF 3 ... Delay test test circuit 4 ... Set scan FF value to “1” when performing path delay test Group 5 ... Set scan FF value when performing path delay test Group set to "0" 6 ... SCAN-IN terminal (scan data input terminal) 7 ... SMC-IN terminal (scan mode control input terminal) 8 ... CK-IN terminal (clock input terminal) 9 ... Delay test mode setting terminal 10 ... SCAN-OUT terminal (scan data output terminal) 11 ... AND gate 12 ... OR gate 13 ... NOT gate 14 ... OR gate 15 ... AND gate 16 ... Multiplexer 17 ... D type flip-flop 18 ... Scan in cycle 19 ... Delay test Cycle 20 ... Scan out Cycle 21 ... Source scan FF 22 ... Target scan FF 23 ... First stage scan FF 24 ... Second stage scan FF 25 ... AND gate 26 ... OR gate 27 ... NOT gate 28 ... OR gate 29 ... AND gate 30 ... Clock Pulse width of

Claims (5)

(57) [Claims] 1. An integrated circuit having a built-in path delay test facilitating circuit for measuring a signal propagation delay time of a specific path from a source flip-flop to a target flip-flop, wherein a state is provided for each gate in the specific path. The state setting flip-flop for setting is configured by a flip-flop capable of selectively latching the D input or the shift input, and when the shift input is set to be latched, even if it is shifted once, the output of each state setting flip-flop An integrated circuit characterized in that each state setting flip-flop is scan-connected so as not to change. 2. An integrated circuit having a built-in path delay test facilitating circuit for measuring a signal propagation delay time of a specific path from a source flip-flop to a target flip-flop, wherein a state is provided for each gate in the specific path. The state setting flip-flop for setting the above is configured by a flip-flop capable of selectively latching the D input or the shift input, and the state setting flip-flop is divided into a group in which the activation condition of the specific path is “1” and a group in which the activation condition is “1”. An integrated circuit characterized by being classified into 0 "groups and being scan-connected for each group. 3. The invention according to claim 2, wherein, in addition to the state setting flip-flop, the source flip-flop is constituted by a flip-flop capable of selectively latching a D input or a shift input, and the state of the source flip-flop is set during a delay test. When setting “1” → “0”, scan connection is made in the order of “1” group, source flip-flop, “0” group, and the state of the source flip-flop is “0” → “1” at the delay test. In this case, the integrated circuit is scan-connected in the order of “0” group, source flip-flop, and “1” group. 4. The integrated circuit according to claim 1, 2, or 3, wherein a condition for activating the specific path is set for each state setting flip-flop, and the state of the source flip-flop is inverted. After inputting the first clock pulse that causes the input, the second clock pulse that latches the input of the target flip-flop after a predetermined time is input, and the input of the target flip-flop is inspected to detect the signal propagation delay time of the specific path. A path delay test method consisting of a measurement procedure for measuring. 5. A path delay test method, wherein the measurement procedure according to claim 4 is repeatedly executed while changing the interval between the first clock pulse and the second clock pulse.