JP2785506B2 - Scan circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan path flip-flop circuit capable of operating a scan clock and a system clock completely asynchronously when constructing a scan path circuit.

[0002]

2. Description of the Related Art In recent years, with the increase in the scale of LSIs, internal tests have become complicated and difficult, and a scan path test method has been used to simplify the internal tests.

A conventional scan path test method and a scan path flip-flop circuit will be described below.

FIG. 6 shows a conventional scan path flip-flop circuit. When used as a normal flip-flop, D is an input, Q is an output, and ck is used as a clock. When Sck is set to 0, when ck is 1, the latch 61 enters the through state, and the normal input D (hereinafter abbreviated as D) is output to the output of the latch 61 as it is. On the other hand, since the latch 62 is held in the holding state by feedback, the previous state is output to the normal output Q (hereinafter abbreviated as Q). When ck becomes 0, the latch 61 is in the holding state, the latch 62 is in the through state, and the value of D remains held. That is, it operates as a flip-flop that holds data at the falling edge of ck. When used as a flip-flop for scanning, SI is used as input, SO is used as output, and Sck is used as a clock. When ck is set to 0, when Sck is 1, the latch 61 enters a through state, and the output of the latch 61 is input to the scan input SI (hereinafter referred to as SI).
Will be output as it is. On the other hand, since the latch 62 is held in the holding state by feedback, the previous state is output to the scanning output SO (hereinafter abbreviated as SO). However, SO and Q are the same output signal. Again Sck
Becomes 1, the latch 61 enters the holding state, the latch 62 enters the through state, and the value of SI remains held in SO. That is, it operates as a flip-flop that holds data at the falling edge of Sck.

FIG. 7 shows an example in which a scan test circuit is configured by using this circuit as one module. 71, 72,
73 is the module FF _n (hereinafter abbreviated as FF _n). ck1 to ckn are set to 0, and the control signal X and the control signal Y are set to 1. The output of FF _n is output to Scan Out,
Observe the internal state. If you enter Scan Clock here,
At the falling edge, each FF _n is shifted. FF _n
In, the output of FF _n-1 is shifted, and the output of FF _n-1 can be observed by Scan Out. The input from the Scan an In is to be shifted to FF _1, it is possible to arbitrarily set the internal state. Therefore, the states of all the FFs _n can be observed and arbitrarily set by repeating the shift n times by the ScanClock.

[0006] This is known as a very simple test method in the sense of simplifying the circuit test.

[0007]

However, in the above-described conventional method, ck must be kept at 0, and in a microprocessor or the like, the state of ck is usually unknown, and its application range is limited. . Further, when a flip-flop held at a rising edge and a flip-flop held at a falling edge coexist in a normal flip-flop, the flip-flop cannot be used. Therefore, an extra circuit must be provided outside.

The present invention solves the above-mentioned conventional problems, and provides a scan path flip-flop circuit capable of testing a circuit by scanning regardless of the state of ck and regardless of the type of flip-flop. It is intended to be.

[0009]

In order to achieve this object, a scan path flip-flop circuit according to the present invention has a plurality of data load type flip-flops, each of which operates independently, and one of which operates normally. During this operation, the other flip-flop is in a data load state, thereby forming a scan path flip-flop circuit that equalizes the outputs of both flip-flops.

[0010]

With this circuit, since a plurality of flip-flops are completely independent and the outputs are always kept equivalent, each flip-flop can realize an asynchronous clock input without being conscious of the other clock. The circuit can be tested by scanning regardless of whether the clock is held at 0 or 1 at all.

[0011]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a scan path flip-flop circuit according to a first embodiment of the present invention.
When S is 0, A is output to Y, and when S is 1, B is output to Y.

[0013]

[Outside 1]

When A is 1, A is in Y,

[0015]

[Outside 2]

Reference numeral 15 denotes a tri-state buffer which is output when the control signal is 1, and 16 denotes a tri-state buffer which is output when the control signal is 0. is there.

When MD is 0, normal flip-flop 1
The multiplexer 7 operates as a flip-flop that holds data at the falling edge of a clock that receives D, inputs ck, and outputs Q, because the multiplexers 11 and 12 output A (hereinafter, abbreviated as a holding state). ). On the other hand, the scan flip-flop 18 is connected to the multiplexers 13, 1
Since 4 outputs B, the data of Q is always read and output to SO (hereinafter abbreviated as a load state). Therefore, the normal flip-flop 17 can be treated as a normal flip-flop ignoring the scan flip-flop 18 at all.

Here, when MD is set to 1, the normal flip-flop 17 always reads the value of SO (hereinafter abbreviated as a load state) because the multiplexers 11 and 12 output B. On the other hand, the scan flip-flop 18 has the SI
, And operates as a flip-flop that holds data at the falling edge of the clock with Sck as the clock and SO as the output (hereinafter, abbreviated to the holding state). Since Q and SO are always equal when the MD changes, Q
And SO data are kept as they are.

FIG. 2 shows a case where the normal flip-flop 17 is replaced with one that retains data at the falling edge. The operation is the same as in the example of FIG.

Here, ck and Sck have opposite phases, but with this circuit, ck and Sck are completely independent and asynchronous, so it does not matter.

FIG. 5 shows an embodiment to which the present invention is actually applied.
FF1 _23, FF1 ₂₅ is scan-path flip-flop circuit shown in FIG. 1, FF2 ₂₄ is scan-path flip-flop circuit shown in FIG.

[0022] When the Mode is set to _{0, FF1 23, FF2 24,} F
F1 ₂₅ because it has independently work at all as a single flip-flop, it is possible to use a completely different type of clock. That is, Clock1, Clock2, Sck
May be completely asynchronous.

When Mode is set to 1, the scan flip-flop shifts from the load state to the hold state.
The normal flip-flop shifts from the holding state to the loading state. Here, the data remains unchanged and does not change.

[0024] In this case, the Scan Out can be observed output of the FF1 ₂₅ is. Now add Scan Clock, each of the scan path flip-flop is shifted, the Scan Out FF2 can output ₂₄ observations, it arbitrary data set from Scan an In the FF1 _23. By repeating this three times, the outputs of all flip-flops can be observed and set arbitrarily.

When Mode is set to 0 again, the scan flip-flop shifts from the hold state to the load state, the normal flip-flop shifts from the load state to the hold state, and returns to the state where the first normal flip-flop operates. . At this time, the value set arbitrarily by the scanning flip-flop remains in each flip-flop,
You can continue testing with this value.

FIG. 3 shows an example of a second embodiment applied to a latch circuit. When MD is 0, multiplexer 1
Since 2 is an output of A, the normal latch 20 operates as a latch for inputting D, an enable of E, and a latch for passing data when the enable with Q as an output is 1. The scanning flip-flop 18 is the same as in the first embodiment.

When MD is 1, the scan flip-flop 18 is in the holding state, and the normal latch 20 is in the load state, so that the circuit test can be performed by scanning regardless of the state of the normal latch 20.

FIG. 4 shows an example of the third embodiment applied to a normal buffer. When MD is 0, since the multiplexer 12 outputs A, the normal buffer 21
, And operates as a buffer with Q as the output. The scanning flip-flop 18 is the same as in the first embodiment.

When MD is 1, the scan flip-flop 18 is in the holding state, the normal buffer 21 outputs the value of SO, and the contents of each buffer can be observed.

[0030]

As described above, the present invention uses a plurality of flip-flops and has a control signal indicating whether a scan flip-flop is valid or a normal flip-flop. When operating as a flip-flop, the other is always in a load state, so that asynchronous flip-flops can be tested by scanning without regard to the state of the system clock.

[Brief description of the drawings]

FIG. 1 is a block diagram of a scan path flip-flop circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram of a scan path flip-flop circuit according to one embodiment of the present invention.

FIG. 3 is a block diagram of a scan path latch circuit according to one embodiment of the present invention;

FIG. 4 is a block diagram of a scan path buffer circuit according to one embodiment of the present invention;

FIG. 5 is a block diagram of an application circuit according to an embodiment of the present invention.

FIG. 6 is a block diagram of a conventional scan path flip-flop circuit.

FIG. 7 is a block diagram of a conventional application circuit.

[Explanation of symbols]

 11, 12, 13, 14 Multiplexer 15, 16 Tri-state buffer 17, 19 Normal flip-flop 18 Scan flip-flop 20 Normal latch 21 Normal buffer 23, 24, 25 Scan path flip-flop circuit 61, 62 Latch 71, 72,73 scan path flip-flop circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H03K 3/02 G01R 31/28 H03K 3/037

Claims (3)

(57) [Claims] An input data is stored based on a clock.
Output flip-flop function and data load input
Output data based on the data loading clock.
First and second flip-flops having
And flop circuit, either the first or second flip-flop circuit-
One with the flip-flop function and the other with the data low
And a control signal for switching whether to use the first flip-flop circuit.
And the data of the second flip-flop circuit
The data is input as load input data, and the second flip
The output of the flip-flop circuit is output to the outside and
Input data for data loading of the first flip-flop circuit
Scanning circuit characterized by being input as data
Road. 2. The method according to claim 1 , wherein input data is transmitted based on an enable signal.
Output latch function and data load input data
Store and output based on data load enable signal
And a flip- flop that stores and outputs input data based on a clock.
Input data for flip-flop function and data loading
Flip-flop with data load function to output as is
Circuit and the latch circuit or the flip-flop circuit
One of them is used for latch function or flip-flop function
And use the other for the data load function
And a control signal, wherein the output of the latch circuit is output to the outside and the
Used as input data for flip-flop circuit data loading
And the output of the flip-flop circuit is externally
Output and input for data loading of the latch circuit.
Scan input as force data.
Circuit. 3. A buffer for outputting input data as it is.
Outputs input data for function and data load as is
And a flip-flop that stores and outputs input data based on a clock.
Input data for flip-flop function and data loading
Flip-flop with data load function to output as is
Circuit and the buffer circuit or the flip-flop circuit
Either one is buffer function or flip-flop function
To use the other and use the other for the data load function
The buffer circuit output is output to the outside and
Input data for data loading of the flip-flop circuit and
And the output of the flip-flop circuit is
And the data load of the buffer circuit.
Characterized by being input as input data for
Circuit for can.