JP6210505B2 - Flip-flop circuit - Google Patents

Description

  The present invention relates to a flip-flop circuit used in various electronic circuits.

  Flip-flop circuits that hold input data are used in various electronic circuits. For example, at the time of data transfer between a plurality of circuits that operate asynchronously, a signal for establishing a communication path is detected and held by a flip-flop circuit. Processing for establishing such a communication path is called handshake or the like. As the handshake, a four-phase handshake protocol and a two-phase handshake protocol are known.

FIG. 19 is a diagram illustrating an example of a four-phase handshake protocol.
As shown in FIG. 19A, when a request signal (req) transmitted from the communication partner side is input to a specific circuit, as shown in FIG. 19B, this circuit sends a response signal (ack). Output to the communication partner.
Here, in the case of the four-phase handshake protocol, the request signal rises from the low level to the high level, and then confirms the rise of the response signal from the low level to the high level, and returns to the low level. The response signal is also returned to the low level after confirming that the request signal has returned to the low level. Thus, in the four-phase handshake protocol, there are four changes: [rising of request signal] → [rising of response signal] → [falling of request signal] → [falling of response signal].
Note that the time from when the request signal changes until the response signal changes varies depending on the signal processing status in the circuit and is not necessarily constant. In the example of FIG. 19, when the first request signal rises, the response signal rises in a relatively short time. On the other hand, when the request signal rises for the second time, the response signal rises after a relatively long time has elapsed, as indicated by the dashed arrow.

FIG. 20 is a diagram illustrating an example of a two-phase handshake protocol.
Also in the case of this two-phase handshake protocol, as shown in FIG. 20A, when a request signal (req) transmitted from the communication partner side is input to a specific circuit, as shown in FIG. This circuit outputs a response signal (ack) to the communication partner.
Here, in the case of the two-phase handshake protocol, the request signal makes a request with any change of the change from the low level to the high level or the change from the high level to the low level. The response signal is also responded with a single state change after the change of the request signal.
Therefore, in the two-phase handshake protocol, there are two changes such as two changes of [request signal rise] → [response signal rise] and two changes of [request signal fall] → [response signal fall]. It is only change.

Conventionally, as a handshake protocol, a four-phase handshake protocol is generally used, and there are few examples to which the two-phase handshake protocol is applied.
Patent Document 1 describes an example in which handshake signals are exchanged between a plurality of circuit blocks.

JP 2008-181170 A

  As described above, conventionally, a handshake protocol is generally a four-phase handshake protocol. However, as can be seen by comparing FIG. 19 and FIG. 20, the two-phase handshake protocol is simpler as a protocol, and contributes to the improvement of data transfer efficiency. However, in order to perform the two-phase handshake protocol, a flip-flop circuit suitable for such processing is required. In other words, it is necessary to detect and hold a change in state when either the rising or falling state of the signal occurs, and the development of a flip-flop circuit used for such applications has been desired. .

  Another problem in the case of using a flip-flop circuit different from that applied to the handshake protocol circuit is that a high-speed clock is required during high-speed operation. That is, the flip-flop circuit has a problem that a high-frequency clock that follows the signal change is necessary to reliably detect the change of the signal input to the circuit. When the clock frequency is low, it is impossible to follow the change of the signal input to the flip-flop circuit. That is, it becomes impossible to detect and hold an appropriate input.

  It is an object of the present invention to provide a flip-flop circuit that solves these problems.

The flip-flop circuit of the present invention has, as input terminals, a first data input terminal to which first data is supplied, and a second data to which second data that is different from the first data is supplied. A data input terminal; a first clock input terminal to which a first clock that defines a sampling timing of the first data obtained at the first data input terminal is supplied; and a first clock input terminal obtained at the second data input terminal. A second clock input terminal for supplying a second clock, which is a clock different from the first clock, defining the sampling timing of the second data, and a sampling operation by the clock obtained at the first clock input terminal A first clock enable input terminal to which a first clock enable signal defining validity or invalidity of the first clock enable signal is supplied, and a sample by a clock obtained at the second clock input terminal And a second clock enable input which the second clock enable signal for defining a valid or invalid grayed operation is supplied.
The memory circuit that holds the sampled signal has the first data when the first clock enable signal obtained at the first clock enable input terminal is valid and the first clock changes to a predetermined state. When the first data obtained at the input terminal is sampled and the second clock enable signal obtained at the second clock enable input terminal is valid and the second clock changes to a predetermined state, the second data The second data obtained at the data input terminal is sampled.
Further, an output terminal for outputting data held by the memory circuit is provided.

  According to the present invention, a flip-flop circuit that obtains output data by sampling two input data with different clock signals is obtained, and various settings can be made by setting two clock signals and two clock enable signals. The operating state is suitable for the application.

It is a block diagram of the flip-flop circuit of the example of the 1st Embodiment of this invention. It is a figure which shows the truth table of the flip-flop circuit of the example of the 1st Embodiment of this invention. It is a wave form diagram which shows the operation example of the flip-flop circuit of the example of the 1st Embodiment of this invention. FIG. 3 is a circuit diagram of a flip-flop circuit according to an example of the first embodiment of the present invention. FIG. 5 is a waveform diagram showing an operation example of the circuit of FIG. 4. It is a block diagram which shows the example of application (example 1) of the flip-flop circuit of the 1st Embodiment of this invention. It is a wave form diagram which shows the operation example by the structure of FIG. It is a block diagram which shows the application example (example 2) of the flip-flop circuit of the 1st Embodiment of this invention. It is a wave form diagram which shows the operation example by the structure of FIG. It is a block diagram of the flip-flop circuit of the example of the 2nd Embodiment of this invention. It is a wave form diagram which shows the operation example of the flip-flop circuit of the example of the 2nd Embodiment of this invention. It is a circuit diagram of the flip-flop circuit of the example of the second embodiment of the present invention. It is a block diagram of the flip-flop circuit of the example of the 3rd Embodiment of this invention. It is a wave form diagram which shows the operation example of the flip-flop circuit of the example of the 3rd Embodiment of this invention. It is a circuit diagram of the flip-flop circuit of the example of the 3rd Embodiment of this invention. It is a block diagram of the flip-flop circuit of the example of the 4th Embodiment of this invention. It is a circuit diagram (the 1) of the flip-flop circuit of the example of the 4th Embodiment of this invention. It is a circuit diagram (the 2) of the flip-flop circuit of the example of the 4th Embodiment of this invention. It is a wave form diagram explaining a 4 phase handshake protocol. It is a wave form diagram explaining a two-phase handshake protocol.

[1. Example of First Embodiment (FIGS. 1 to 8)]
FIG. 1 is a diagram showing a flip-flop circuit 100 according to an example of the first embodiment of the present invention.
The flip-flop circuit 100 includes a first data input terminal 101 and a second data input terminal 102. When the first clock enable signal CE1 obtained at the first clock enable input terminal 103 indicates that the data is valid, the first data D1 obtained at the first data input terminal 101 becomes the first clock input terminal 105. Are sampled by the first clock CK1 obtained.

  In addition, when the second clock enable signal CE2 obtained at the second clock enable input terminal 104 indicates that the second clock enable signal CE2 is valid, the second data D2 obtained at the second data input terminal 102 becomes the second clock input signal. It is sampled by the second clock CK 2 obtained at the end 106.

  A signal Q, which is a signal sampled and held by each clock, is output from the Q output terminal 107. Further, a signal (signal Qn) obtained by inverting the signal Q is output from the inverted Q output terminal 108. The sampling operation is reset by a reset signal RST obtained at the reset input terminal 109.

As timing for sampling the first data D1 with the first clock CK1, the first data D1 is sampled at the timing when the first clock CK1 changes from low level to high level. Furthermore, the first data D1 is also sampled at the timing when the first clock CK1 changes from the high level to the low level.
In FIG. 1, two triangular marks Δ are shown side by side at the input end 105 of the first clock CK1 when changing from a low level to a high level and from a high level to a low level. Indicates that it will be sampled both on change. The same applies to other figures. Further, when only one triangle mark Δ is shown on the side, it indicates that sampling is performed only when one of the clocks changes (for example, when changing from a low level to a high level).

  FIG. 2 is a truth table of the flip-flop circuit 100. The truth table includes the first data D1, the first clock enable signal CE1, the first clock CK1, the second data D2, the second clock enable signal CE2, the second clock CK2, and the reset signal RST. The Q output in each state is shown. In this truth table, “1” indicates a high level state, and “0” indicates a low level state. In addition, “↑” indicates a time when the level changes from a low level to a high level, and “↓” indicates a time when the level changes from a high level to a low level. “1/0” indicates that the signal may be either 1 (high level) or 0 (low level). Further, “*” indicates a case where the signal may change in addition to 1/0. Here, for convenience of explanation, as shown at the left end of the truth table, each state is referred to as state 1 to state 10.

Each state in FIG. 2 will be described. State 1 is when the first data D1 is the value “a” and the first clock enable signal CE1 is at a high level. In this state, when the first clock CK1 changes from the low level to the high level, the value “a” of the first data D1 is sampled. Then, the sampled value “a” is output as the Q output.
State 2 in FIG. 2 is when the first clock enable signal CE1 is at a high level and the first clock CK1 changes from a high level to a low level. Also at this time, the value “a” of the first data D1 is sampled, and the value “a” is output as the Q output.

State 3 in FIG. 2 is when the first clock enable signal CE1 is at a high level and the first clock CK1 is not at a high level or a low level. At this time, the previous Q output is maintained. In FIG. 2, Q ₋₁ indicates a state in which the immediately preceding Q output is maintained.
State 4 in FIG. 2 is when the first clock enable signal CE1 becomes low level, and the state of the second clock CK2 does not change between high level and low level. Also at this time, the immediately preceding Q output is maintained.
State 5 in FIG. 2 is when the second data D2 is the value “b”, the second clock enable signal CE2 is at the high level, and the second clock CK2 is changed from the low level to the high level. At this time, the value “b” of the second data D2 is sampled, and the sampled value “b” is output as the Q output.
State 6 in FIG. 2 is when the second clock enable signal CE2 is at a high level and the second clock CK2 is changed from a high level to a low level. Also at this time, the value “b” of the second data D2 is sampled, and the sampled value becomes the Q output.

State 7 in FIG. 2 is when the second clock enable signal CE2 is at a high level and the second clock CK2 is at a high level or a low level and there is no change. At this time, the previous Q output is maintained.
State 8 in FIG. 2 is when the second clock enable signal CE2 becomes low level, and the state of the first clock CK1 does not change between high level and low level. Also at this time, the immediately preceding Q output is maintained.

State 9 in FIG. 2 is when the reset signal RST is at a high level. At this time, the Q output is reset to zero.
State 10 in FIG. 2 is when the clock enable signals CE1 and CE2 are both at a high level and the first clock CK1 and the second clock CK2 change simultaneously. The flip-flop circuit 100 prohibits the change of the state 10.

FIG. 3 is a waveform diagram illustrating an example when a signal is input to the flip-flop circuit 100. In the example of FIG. 3, the clock enable signals CE1 and CE2 are both at a high level, and the reset signal RST is at a low level.
The first data D1 shown in FIG. 3A is sampled at the change timing of the first clock CK1 shown in FIG. This sampled signal is reflected in the output Q (FIG. 3E) and the inverted output Qn (FIG. 3F).
Also, the second data D2 shown in FIG. 3C is sampled at the change timing of the second clock CK2 shown in FIG. This sampled signal is reflected in the output Q (FIG. 3E) and the inverted output Qn (FIG. 3F).
In the example of FIG. 3, the first clock CK1 is changed to the first half, the second clock CK2 in the second half is changed, as an output Q and an inverted output Q _n, corresponding to the first data D1 in the first half A change appears, and a change corresponding to the second data D2 appears in the second half.

FIG. 4 is an example of a circuit diagram of the flip-flop circuit 100.
The input terminal 101 from which the first data D1 is obtained is connected to the input of the inverter circuit 111 through a parallel circuit between the source and drain of the transistor M101 and between the source and drain of the transistor M102. The input terminal 101 from which the first data D1 is obtained is connected to the input of the inverter circuit 111 via a parallel circuit between the source and drain of the transistor M103 and between the source and drain of the transistor M104. Further, the input terminal 101 from which the first data D1 is obtained is connected to the gate of the transistor M112 and the gate of the transistor M116.
In the figure, a transistor whose gate portion is circled is a P-type transistor, and a transistor whose gate portion is not circled is an N-type transistor. Also in the circuit diagrams of examples of other embodiments, P-type transistors and N-type transistors are similarly distinguished and shown.

  The input terminal 102 from which the second data D2 is obtained is connected to the input of the inverter circuit 111 through a parallel circuit between the source and drain of the transistor M105 and between the source and drain of the transistor M106. The input terminal 102 from which the second data D2 is obtained is connected to the input of the inverter circuit 111 via a parallel circuit between the source and drain of the transistor M107 and between the source and drain of the transistor M108. Further, the input terminal 102 from which the second data D2 is obtained is connected to the gate of the transistor M115 and the gate of the transistor M119.

The output of the inverter circuit 111 is returned to the input of the inverter circuit 111 via the NOR gate circuit 112. In addition to the output of the inverter circuit 111, the NOR gate circuit 112 is supplied with a signal obtained at the input terminal 109 of the reset signal RST.
A loop circuit including the inverter circuit 111 and the NOR gate circuit 112 constitutes a memory circuit that holds a sampled signal. In this memory circuit, when the reset signal RST is at a low level, the signal is held by repeating inversion between the inverter circuit 111 and the NOR gate circuit 112. When the reset signal RST is at a high level, the output of the NOR gate circuit 112 is forcibly reset to a low level.

  The output of the inverter circuit 111 is supplied to the Q output terminal 107 via the inverter circuit 151. Further, the output of the inverter circuit 151 is supplied to the inverted Q output terminal 108 via another inverter circuit 152.

A series circuit in which inverter circuits 121, 122, 123, a delay circuit 124, and inverter circuits 125, 126 are connected in order is connected to the input terminal 105 of the first clock CK1. Then, the output CK1iP of the inverter circuit 122 and the output CK1oP of the inverter circuit 126 are supplied to the NAND gate circuit 127. The first clock enable signal CE1 obtained at the first clock enable input terminal 103 is also supplied to the NAND gate circuit 127.
The output W1PB of the NAND gate circuit 127 is supplied to the gates of the transistors M103 and M111. Further, a signal W1P obtained by inverting the output W1PB of the NAND gate circuit 127 by the inverter circuit 128 is supplied to the gates of the transistor M104 and the transistor M117.

Further, the output CK1iN of the inverter circuit 121 and the output CK1oN of the inverter circuit 125 are supplied to the NAND gate circuit 129. The first clock enable signal CE1 obtained at the first clock enable input terminal 103 is also supplied to the NAND gate circuit 129.
The output W1NB of the NAND gate circuit 129 is supplied to the gates of the transistors M101 and M110. A signal W1N obtained by inverting the output of the NAND gate circuit 129 by the inverter circuit 130 is supplied to the gates of the transistors M102 and M118.

A series circuit in which inverter circuits 131, 132, 133, a delay circuit 134, and inverter circuits 135, 136 are sequentially connected is connected to the input terminal 106 of the second clock CK2. Then, the output CK2iP of the inverter circuit 132 and the output CK2oP of the inverter circuit 136 are supplied to the NAND gate circuit 137. The second clock enable signal CE2 obtained at the second clock enable input terminal 104 is also supplied to the NAND gate circuit 137.
The output W2PB of the NAND gate circuit 137 is supplied to the gates of the transistors M107 and M114. A signal W2P obtained by inverting the output of the NAND gate circuit 137 by the inverter circuit 138 is supplied to the gates of the transistors M108 and M120.

Further, the output CK2iN of the inverter circuit 131 and the output CK2oN of the inverter circuit 135 are supplied to the NAND gate circuit 139. The second clock enable signal CE2 obtained at the second clock enable input terminal 104 is also supplied to the NAND gate circuit 139.
Then, the output W2NB of the NAND gate circuit 139 is supplied to the gates of the transistors M105 and M113. A signal W2N obtained by inverting the output of the NAND gate circuit 139 by the inverter circuit 140 is supplied to the gates of the transistors M106 and M121.

  Between the power supply potential and the ground potential portion, the sources and drains of the transistors M110, M112, M116, and M117 are sequentially connected. A transistor M111 is connected in parallel to the transistor M110. A transistor M118 is connected in parallel to the transistor M117. A connection point between the transistor M112 and the transistor M116 is connected to an output portion of the inverter circuit 111.

  Further, the source and drain of the transistors M113, M115, M119, and M120 are sequentially connected between the power supply potential and the ground potential portion. A transistor M114 is connected in parallel to the transistor M113. A transistor M121 is connected in parallel to the transistor M120. A connection point between the transistor M115 and the transistor M119 is connected to an output portion of the inverter circuit 111.

With the circuit configuration shown in FIG. 4, the flip-flop circuit 100 that performs the operation shown in FIG. 3 is obtained. In this case, in the circuit of FIG. 4, a memory circuit with low power consumption can be obtained by using a circuit in which the inverter circuit 111 and the NOR gate circuit 112 are connected in a loop as the memory circuit that holds the sampled signal. . The NOR gate circuit 112 is used as an inverter circuit, and is configured to hold a signal by a latch formed by two inverter circuits. Here, since the circuit shown in FIG. 4 is used, the write operation is simultaneously performed on the input side and the output side of the two inverter circuits constituting the latch, so that the data can be efficiently rewritten by the two inverter circuits. . Specifically, when the signal is rewritten, among the inverter circuit 111 and the NOR gate circuit 112 constituting the memory circuit, the input of the inverter circuit 111 is rewritten by a circuit using transistors M101 to M108. Further, the input of the NOR gate circuit 112 is rewritten to the opposite value by the circuit of the transistors M110 to M121. Therefore, there is no collision between the inverter circuit 111 and the NOR gate circuit 112 at the time of rewriting, and processing such as temporarily disconnecting the loop of the memory circuit is not necessary at the time of rewriting. This has the effect of operating well with low power consumption.
Note that the loop-shaped memory circuit is configured by the inverter circuit 111 and the NOR gate circuit 112, but when the reset signal RST is not supplied, the loop-shaped memory circuit is configured by two inverter circuits.

FIG. 5 is a diagram illustrating an example of the waveform of each part of the circuit of FIG.
As shown in FIG. 5A, when the first clock CK1 is input to the first clock input terminal 105, the output signal CK1iN of the inverter circuit 121 changes as shown in FIG. 5B. The signal is inverted when the timing rises.
Further, the output signal CK1iP of the inverter circuit 122 becomes a signal obtained by inverting and delaying the signal CK1iN as shown in FIG.

Further, as shown in FIG. 5D, a signal CK1oN that has passed through the inverter circuit 123, the delay circuit 124, and the inverter circuit 125 is obtained. Further, as shown in FIG. 5E, the signal CK1oN is converted into an inverter circuit. By inverting at 126, the signal CK1oP is obtained.
Then, the signal W1PB (FIG. 5G) defined by the rising edge of the signal CK1iP (FIG. 5C) and the falling edge of the signal CK1oP (FIG. 5E) is obtained at the output of the NAND gate circuit 127. It is done. Further, a signal W1P (FIG. 5 (f)) obtained by inverting the signal W1PB by the inverter circuit 128 is obtained.

Further, the signal W1NB (FIG. 5 (i)) defined by the rising edge of the signal CK1iN (FIG. 5 (b)) and the falling edge of the signal CK1oN (FIG. 5 (d)) is obtained at the output of the NAND gate circuit 129. It is done. Further, a signal W1N (FIG. 5 (h)) obtained by inverting the signal W1NB by the inverter circuit 130 is obtained.
Then, the first data D1 obtained at the first data input terminal 101 is sampled by these signals, and the sampled value is held.

  A similar signal is also generated when the second clock CK2 is input. The generation state of each signal is the same as in the case of the first clock CK1 shown in FIG. The second data D2 obtained at the second data input terminal 102 is sampled and held by a signal generated based on the second clock CK2.

Next, a usage example of the flip-flop circuit 100 will be described.
6 and 7 are examples applied to a receiving circuit that receives data transmitted from other circuits. In this example, as shown in FIG. 7A, a header section [header] is transmitted first, followed by a data body section [data], and finally a tail section [tail] as transmission data. Is transmitted.
At this time, it is assumed that a request signal oreq (FIG. 7 (b)) for requesting transmission and a response signal iack (FIG. 7 (c)) for the signal are transmitted and received by a two-phase handshake protocol. In the two-phase handshake protocol, handshaking is performed by [request signal change] → [response signal change].

The flip-flop circuit 100 in FIG. 6 is applied to a receiving circuit in the case of performing a response using this two-phase handshake protocol. In this example, the response signal iack (FIG. 7C) is supplied to the two clock input terminals 105 and 106.
That is, as shown in FIG. 6, the common response signal iack is supplied to the two clock input terminals 105 and 106 of the flip-flop circuit 100. Then, a signal indicating the header section shown in FIG. 7D is supplied to the first clock enable input terminal 103. Further, a signal indicating a tail section shown in FIG. 7E is supplied to the second clock enable input terminal 104.

  By supplying such a signal to the flip-flop circuit 100, the signal obtained at the inverted Q output terminal 108 falls at the timing when the response signal iack changes in the header section as shown in FIG. The gate signal rises at the timing when the response signal iack changes in the tail section. With this gate signal, processing for extracting the received data is executed. Thus, by using the flip-flop circuit 100 of this example, a circuit that performs communication using the two-phase handshake protocol can be realized with a simple configuration.

Next, another usage example of the flip-flop circuit 100 will be described with reference to FIGS. In this example, a clock signal is distributed and high speed operation is performed.
In this example, as shown in FIG. 8, the first data D1 supplied to the first data input terminal 101 and the second data D2 supplied to the second data input terminal 102 are the same data. The clocks supplied to the first clock input terminal 105 and the second clock input terminal 106 are signals having the same clock frequency. However, the first clock CK1 and the second clock CK2 are signals having a phase difference of 90 °.

Here, for example, as shown in FIG. 9A, it is assumed that common data D is supplied to the first data input terminal 101 and the second data input terminal 102.
At this time, sampling of the data D is executed at the change timing of the first clock CK1 shown in FIG. 9B and the change timing of the second clock CK2 shown in FIG. 9C. Q output is obtained as shown in FIG.
Since the output shown in FIG. 9D is a signal sampled by two clocks CK1 and CK2, it is sampled at a frequency twice that of each clock. Therefore, by distributing the low-frequency clock and generating the two clocks CK1 and CK2, input data can be sampled at a high frequency exceeding the original clock frequency, and high-speed operation using the low-frequency clock can be performed. Such a reduction in clock frequency has the effect of facilitating circuit design.

[2. Example of Second Embodiment (FIGS. 10 to 12)]
FIG. 10 is a diagram illustrating a flip-flop circuit 200 according to the second embodiment of the present invention.
The flip-flop circuit 200 includes a first data input terminal 201 and a second data input terminal 202. When the first clock enable signal CE1 obtained at the first clock enable input terminal 203 indicates validity, the first data D1 obtained at the first data input terminal 201 is converted into the first clock input terminal 205. Are sampled by the first clock CK1 obtained. Here, the sampling by the first clock CK1 is performed at the timing when the first clock CK1 rises from the low level to the high level. Data sampling is not performed at the timing when the first clock CK1 changes from the high level to the low level.

  In addition, when the second clock enable signal CE2 obtained at the second clock enable input terminal 204 indicates that the second clock enable signal CE2 is valid, the second data D2 obtained at the second data input terminal 202 becomes the second clock input signal. It is sampled by the second clock CK 2 obtained at the end 206. Here, the sampling by the second clock CK2 is executed both at the timing when the second clock CK2 rises from the low level to the high level and at the timing when the second clock CK2 changes from the high level to the low level. .

  A signal Q, which is a signal sampled and held by each clock, is output from the Q output terminal 207. Further, a signal (signal Qn) obtained by inverting the signal Q is output from the inverted Q output terminal 208. Further, the sampling operation is reset by a reset signal RST obtained at the reset input terminal 209.

FIG. 11 is a waveform diagram showing an operation example of the flip-flop circuit 200 shown in FIG.
FIG. 11A shows the first data D1, and FIG. 11C shows the second data D2. The first data D1 is sampled at the timing when the first clock CK1 shown in FIG. 11B rises from the low level to the high level. The second data D2 is sampled at the timing when the second clock CK2 shown in FIG. 11D rises from the low level to the high level and at the timing when the second clock CK2 changes from the high level to the low level.
The Q output shown in FIG. 11 (e) and the inverted Q output shown in FIG. 11 (f) are signals obtained by holding the results sampled by the two clocks CK1 and CK2.

  As described above, according to the flip-flop circuit 200 shown in FIG. 10, the first clock CK1 of the two clocks is sampled only at the rise of the signal, and the second clock CK2 has the rise and fall of the signal. Sampling is performed on both sides. Therefore, different sampling states can be set for the first data D1 sampled by the first clock CK1 and the second data D2 sampled by the second clock CK2, and sampling suitable for each data is performed. A flip-flop circuit is obtained.

FIG. 12 is an example of a circuit diagram of the flip-flop circuit 200.
The input terminal 201 from which the first data D1 is obtained is connected to the input of the inverter circuit 211 via a parallel circuit between the source and drain of the transistor M201 and between the source and drain of the transistor M202. Further, the input terminal 201 from which the first data D1 is obtained is connected to the gate of the transistor M208 and the gate of the transistor M212.

  The input terminal 202 from which the second data D2 is obtained is connected to the input of the inverter circuit 211 via a parallel circuit between the source and drain of the transistor M203 and between the source and drain of the transistor M204. The input terminal 202 from which the second data D2 is obtained is connected to the gate of the transistor M211 and the gate of the transistor M214.

The output of the inverter circuit 211 is returned to the input of the inverter circuit 211 via the NOR gate circuit 212. In addition to the output of the inverter circuit 211, the NOR gate circuit 212 is supplied with a signal obtained at the input terminal 209 of the reset signal RST.
A loop circuit including the inverter circuit 211 and the NOR gate circuit 212 constitutes a memory circuit that holds the sampled signal. In this memory circuit, when the reset signal RST is at a low level, the signal is held by repeating inversion between the inverter circuit 211 and the NOR gate circuit 112. When the reset signal RST is at a high level, the output of the NOR gate circuit 212 is forcibly reset to a low level.

  Then, the output of the inverter circuit 211 is supplied to the Q output terminal 207 via the inverter circuit 251. Further, the output of the inverter circuit 251 is supplied to the inverted Q output terminal 208 via another inverter circuit 252.

A series circuit in which inverter circuits 221, 222, and 223, a delay circuit 224, and inverter circuits 225 and 226 are sequentially connected is connected to the input terminal 205 of the first clock CK1. Then, the output of the inverter circuit 222 and the output of the inverter circuit 226 are supplied to the NAND gate circuit 227. The first clock enable signal CE1 obtained at the first clock enable input terminal 203 is also supplied to the NAND gate circuit 227.
Then, the output of the NAND gate circuit 227 is supplied to the gates of the transistors M201 and M207. The output of the NAND gate circuit 227 is supplied to the gates of the transistors M202 and M213 via the inverter circuit 228.

A series circuit in which inverter circuits 231, 232, 233, a delay circuit 234, and inverter circuits 235, 236 are sequentially connected is connected to the input terminal 206 of the second clock CK2. Then, the output of the inverter circuit 232 and the output of the inverter circuit 236 are supplied to the NAND gate circuit 237. The second clock enable signal CE2 obtained at the second clock enable input terminal 204 is also supplied to the NAND gate circuit 237.
The output of the NAND gate circuit 237 is supplied to the gates of the transistors M205 and M210. The output of the NAND gate circuit 237 is supplied to the gates of the transistors M206 and M215 via the inverter circuit 238.

Further, the output of the inverter circuit 231 and the output of the inverter circuit 235 are supplied to the NAND gate circuit 239. The second clock enable signal CE2 obtained at the second clock enable input terminal 204 is also supplied to the NAND gate circuit 239.
The output of the NAND gate circuit 239 is supplied to the gates of the transistor M203 and the transistor M209. Further, the output of the NAND gate circuit 239 is supplied to the gates of the transistors M204 and M216 via the inverter circuit 240.

  Further, the source and drain of the transistors M207, M208, M212, and M213 are sequentially connected between the power supply potential and the ground potential portion. A connection point between the transistor M208 and the transistor M212 is connected to an output portion of the inverter circuit 211.

  Further, the sources and drains of the transistors M209, M211, M214, and M215 are sequentially connected between the power supply potential and the ground potential portion. A transistor M210 is connected in parallel to the transistor M209. A transistor M216 is connected in parallel to the transistor M215. A connection point between the transistor M211 and the transistor M214 is connected to an output portion of the inverter circuit 211.

  With the circuit configuration shown in FIG. 12, the flip-flop circuit 200 that performs the operation shown in FIG. 11 is obtained. Also in the case of the circuit shown in FIG. 12, similarly to the circuit of FIG. 4 described in the first embodiment, the input side and output of the loop circuit (inverter circuit 211, NOR gate circuit 212) constituting the memory circuit. Since the write operation is performed at the same time, data can be rewritten efficiently with low power consumption.

[3. Example of Third Embodiment (FIGS. 13 to 15)]
FIG. 13 is a diagram illustrating a flip-flop circuit 300 according to the example of the third embodiment of the present invention.
The flip-flop circuit 300 includes a first data input terminal 301 and a second data input terminal 302. When the validity is indicated by the first clock enable signal CE1 obtained at the first clock enable input terminal 303, the first data D1 obtained at the first data input terminal 301 becomes the first clock input terminal 305. Are sampled by the first clock CK1 obtained. Here, the sampling by the first clock CK1 is performed at the timing when the first clock CK1 rises from the low level to the high level. Data sampling is not performed at the timing when the first clock CK1 changes from the high level to the low level.

  When the second clock enable signal CE2 obtained at the second clock enable input terminal 304 indicates that the second clock enable signal CE2 is valid, the second data D2 obtained at the second data input terminal 302 becomes the second clock input signal. It is sampled by the second clock CK 2 obtained at the end 306. Sampling by the second clock CK2 is also performed at the timing when the second clock CK2 rises from a low level to a high level. Data sampling is not performed at the timing when the second clock CK2 changes from the high level to the low level.

  A signal Q, which is a signal sampled and held by each clock, is output from the Q output terminal 307. Further, a signal (signal Qn) obtained by inverting the signal Q is output from the inverted Q output terminal 308. Also, the sampling operation is reset by a reset signal RST obtained at the reset input terminal 309.

FIG. 14 is a waveform diagram showing an operation example of the flip-flop circuit 300 shown in FIG.
FIG. 14A shows the first data D1, and FIG. 14C shows the second data D2. The first data D1 is sampled at the timing when the first clock CK1 shown in FIG. 14B rises from the low level to the high level. The second data D2 is sampled at the timing when the second clock CK2 shown in FIG. 14 (d) rises from the low level to the high level.
The Q output shown in FIG. 14 (e) and the inverted Q output shown in FIG. 14 (f) are signals in which the results sampled by the two clocks CK1 and CK2 are held.

  In this way, according to the flip-flop circuit 300 shown in FIG. 13, sampling is performed only at the rising edge of each of the two clocks, and a flip-flop circuit that appropriately samples the two data D1 and D2 is obtained.

FIG. 15 is an example of a circuit diagram of the flip-flop circuit 300.
The input terminal 301 from which the first data D1 is obtained is connected to the input of the inverter circuit 311 through a parallel circuit between the source and drain of the transistor M301 and between the source and drain of the transistor M302. An input terminal 301 from which the first data D1 is obtained is connected to the gate of the transistor M310 and the gate of the transistor M311.

  The input terminal 302 from which the second data D2 is obtained is connected to the input of the inverter circuit 311 via a parallel circuit between the source and drain of the transistor M303 and between the source and drain of the transistor M304. The input terminal 302 from which the second data D2 is obtained is connected to the gate of the transistor M306 and the gate of the transistor M307.

The output of the inverter circuit 311 is returned to the input of the inverter circuit 311 via the NOR gate circuit 312. In addition to the output of the inverter circuit 311, the NOR gate circuit 312 is supplied with a signal obtained at the input terminal 309 of the reset signal RST.
A loop circuit including the inverter circuit 311 and the NOR gate circuit 312 constitutes a memory circuit that holds a sampled signal. In this memory circuit, when the reset signal RST is at a low level, the signal is held by repeating inversion between the inverter circuit 311 and the NOR gate circuit 312. When the reset signal RST is at a high level, the output of the NOR gate circuit 312 is forcibly reset to a low level.

  Then, the output of the inverter circuit 311 is supplied to the Q output terminal 307 via the inverter circuit 341. Further, the output of the inverter circuit 341 is supplied to the inverted Q output terminal 308 via another inverter circuit 342.

A series circuit in which inverter circuits 321, 322, 323, a delay circuit 324, and inverter circuits 325, 326 are sequentially connected is connected to the input terminal 305 of the first clock CK1. Then, the output of the inverter circuit 322 and the output of the inverter circuit 326 are supplied to the NAND gate circuit 327. The first clock enable signal CE1 obtained at the first clock enable input terminal 303 is also supplied to the NAND gate circuit 327.
The output of the NAND gate circuit 327 is supplied to the gates of the transistors M301 and M309. The output of the NAND gate circuit 327 is supplied to the gates of the transistors M302 and M312 via the inverter circuit 328.

The input terminal 306 of the second clock CK2 is connected to a series circuit in which inverter circuits 331, 332, 333, a delay circuit 334, and inverter circuits 335, 336 are connected in order. Then, the output of the inverter circuit 332 and the output of the inverter circuit 336 are supplied to the NAND gate circuit 337. The second clock enable signal CE2 obtained at the second clock enable input terminal 304 is also supplied to the NAND gate circuit 337.
The output of the NAND gate circuit 337 is supplied to the gates of the transistors M303 and M305. The output of the NAND gate circuit 337 is supplied to the gates of the transistors M304 and M308 through the inverter circuit 338.

  Further, the source and drain of the transistors M305, M306, M307, and M308 are sequentially connected between the power supply potential and the ground potential portion. A connection point between the transistor M306 and the transistor M307 is connected to the output portion of the inverter circuit 311.

  Further, the sources and drains of the transistors M309, M310, M311, and M312 are sequentially connected between the power supply potential and the ground potential portion. A connection point between the transistor M310 and the transistor M311 is connected to an output portion of the inverter circuit 311.

  With the circuit configuration shown in FIG. 15, the flip-flop circuit 300 that performs the operation shown in FIG. 14 is obtained. In the case of the circuit shown in FIG. 14 as well, the input side and the output of the loop circuit (inverter circuit 311, NOR gate circuit 312) constituting the memory circuit, similarly to the circuit of FIG. 4 described in the first embodiment. Since the write operation is performed at the same time, data can be rewritten efficiently and with low power consumption.

[4. Example of Fourth Embodiment (FIGS. 16 to 18)]
FIG. 16 is a diagram illustrating a flip-flop circuit 400 according to an example of the fourth embodiment of the present invention.
The flip-flop circuit 400 includes four clock input terminals 401 to 404, a Q output terminal 405, an inverted Q output terminal 406, and a reset input terminal 407.
In this example, when one of the four clocks CK1, CK2, CK3, and CK4 changes from a low level to a high level and changes from a high level to a low level, the Q output And an inverted Q output. The four clocks CK1, CK2, CK3, and CK4 change the output regardless of which of them changes unless they change simultaneously.

17 and 18 are examples of circuit diagrams of the flip-flop circuit 400. FIG.
FIG. 17 is a diagram illustrating a circuit that processes the clocks CK1, CK2, CK3, and CK4. That is, the first clock CK1 is supplied to a series circuit in which inverter circuits 411a, 412a, and 413a, a delay circuit 414a, and inverter circuits 415a and 416a are connected in order. Then, the output CK1iP of the inverter circuit 412a and the output CK1oP of the inverter circuit 416a are supplied to the NAND gate circuit 421a. The output signal W1PB of the NAND gate circuit 421a is supplied to the inverter circuit 422a. The signal output from the inverter circuit 422a is the signal W1P.

  Further, the output CK1iN of the inverter circuit 411a and the output CK1oN of the inverter circuit 415a are supplied to the NAND gate circuit 431a. The output signal W1NB of the NAND gate circuit 431a is supplied to the inverter circuit 432a. The signal output from the inverter circuit 432a is the signal W1N.

  The circuit that processes the second clock CK2, the third clock CK3, and the fourth clock CK4 has the same configuration as the circuit that processes the first clock CK1. In FIG. 17, a circuit for processing the n-th clock (n is any one of 2, 3 and 4) is shown with n added to the end of the reference numeral. 17 and 18 show two systems of a circuit that processes the first clock CK1 and a circuit that processes the n-th clock, but actually includes four systems corresponding to the four clocks.

  FIG. 18 shows an example of a circuit to which a signal obtained by processing these clocks is supplied. In FIG. 18 as well, a circuit prepared for each of the four clocks is a system circuit (a circuit with “a” at the end of the symbol) for processing a signal based on the first clock CK1, and an nth clock. A circuit of a system for processing a signal based on CKn (a circuit with n added to the end of the reference numeral) is shown, and a part thereof is omitted.

In the circuit of FIG. 18, the signal W1NB generated based on the first clock CK1 is supplied to the gate of the transistor M401a and the gate of the transistor M412a. In addition, the signal W1PB generated based on the first clock CK1 is supplied to the gate of the transistor M403a and the gate of the transistor M411a.
In addition, the signal W1N generated based on the first clock CK1 is supplied to the gate of the transistor M402a and the gate of the transistor M416a. In addition, the signal W1P generated based on the first clock CK1 is supplied to the gate of the transistor M404a and the gate of the transistor M415a.

Similarly, a signal WnNB generated based on the nth clock (n is one of 2, 3 and 4) CKn is supplied to the gate of the transistor M401n and the gate of the transistor M412n. A signal WnPB generated based on the nth clock CKn is supplied to the gate of the transistor M403n and the gate of the transistor M411n.
A signal WnN generated based on the nth clock CKn is supplied to the gate of the transistor M402n and the gate of the transistor M416n. A signal WnP generated based on the nth clock CKn is supplied to the gate of the transistor M404n and the gate of the transistor M415n.

The output signal of the inverter circuit 445 is supplied to the input of the inverter circuit 441 through a parallel circuit between the source and drain of the transistor M401a and between the source and drain of the transistor M402a. Similarly, the output signal of the inverter circuit 445 is supplied to the input of the inverter circuit 441 through a parallel circuit between the source and drain of the transistor M403a and between the source and drain of the transistor M404a.
Similarly, the output signal of the inverter circuit 445 is supplied to the input of the inverter circuit 441 through a parallel circuit between the source and drain of the transistor M401n and between the source and drain of the transistor M402n. Similarly, the output signal of the inverter circuit 445 is supplied to the input of the inverter circuit 441 through a parallel circuit between the source and drain of the transistor M403n and between the source and drain of the transistor M404n.

The output of the inverter circuit 441 is returned to the input of the inverter circuit 441 through the NOR gate circuit 442. In addition to the output of the inverter circuit 441, the NOR gate circuit 442 is supplied with a signal obtained at the input terminal 407 of the reset signal RST.
A loop circuit including the inverter circuit 441 and the NOR gate circuit 442 constitutes a memory circuit that holds a signal. In this memory circuit, when the reset signal RST is at a low level, the signal is held by repeating inversion between the inverter circuit 441 and the NOR gate circuit 442. When the reset signal RST is at a high level, the output of the NOR gate circuit 442 is forcibly reset to a low level.

Then, the output of the inverter circuit 441 is supplied to the Q output terminal 405 via the inverter circuit 443. Further, the output of the inverter circuit 443 is supplied to the inverted Q output terminal 406 via another inverter circuit 444.
Further, the output of the inverter circuit 443 is supplied to the inverter circuit 445.

Between the power supply potential and the ground potential portion, the sources and drains of the transistors M411a, M413, M414, and M415a are sequentially connected. A connection point between the transistor M413 and the transistor M414 is connected to the output portion of the inverter circuit 441.
The transistor M412a is connected in parallel to the transistor M411a. Furthermore, transistors M411n and M412n controlled by a system signal other than the first clock CK1 are connected in parallel to the transistor M411a.

A transistor M416a is connected in parallel to the transistor M415a. Further, transistors M415n and M416n controlled by a system signal other than the first clock CK1 are connected in parallel to the transistor M415a.
The output signal of the inverter circuit 445 is supplied to the gate of the transistor M413 and the gate of the transistor M414.

  With the circuit configuration shown in FIGS. 17 and 18, the flip-flop circuit 400 shown in FIG. 16 is obtained. In the case of the circuits shown in FIGS. 17 and 18, similarly to the circuit of FIG. 4 described in the first embodiment, the write operation is simultaneously performed on the input side and the output side of the loop constituting the memory circuit. Therefore, data can be rewritten efficiently with low power consumption.

Note that the specific circuit configuration described in each of the embodiments described so far is a preferable example, and the same processing may be performed with other circuit configurations.
In addition, the application examples of the flip-flop circuit described with reference to FIGS. 6 and 8 are examples, and the flip-flop circuit of the present invention may be applied to other circuits.

  100, 200, 300, 400 ... flip-flop circuit, 101, 201, 301 ... first data input terminal, 102, 202, 302 ... second data input terminal, 103, 203, 303 ... first clock enable input End, 104, 204, 304 ... second clock enable input end, 105, 205, 305 ... first clock input end, 106, 206, 306 ... second clock input end, 107, 207, 307 ... Q output End, 108, 208, 308 ... inverted Q output end, 109, 209, 309 ... reset input end, 401 ... first clock input end, 402 ... second clock input end, 403 ... third clock input end, 404 ... fourth clock input terminal, 405 ... Q output terminal, 406 ... inverted Q output terminal, 407 ... reset input terminal

Claims (5)

A first data input to which first data is supplied;
A second data input terminal to which second data that is different from the first data is supplied;
A first clock input terminal to which a first clock defining a sampling timing of the first data obtained at the first data input terminal is supplied;
A second clock input terminal to which a second clock that is a clock different from the first clock, which defines a sampling timing of the second data obtained at the second data input terminal, is supplied;
A first clock enable input terminal to which a first clock enable signal for specifying validity or invalidity of the sampling operation by the first clock obtained at the first clock input terminal is supplied;
A second clock enable input terminal to which a second clock enable signal for specifying validity or invalidity of the sampling operation by the second clock obtained at the second clock input terminal is supplied;
The first data obtained at the first data input terminal when the first clock enable signal obtained at the first clock enable input terminal is valid and the first clock changes to a predetermined state. When the second clock enable signal obtained at the second clock enable input terminal is valid and the second clock changes to a predetermined state, the second data enable input terminal obtains the second clock enable input terminal. A storage circuit that samples the second data and holds the sampled data;
A flip-flop circuit comprising: an output terminal for outputting data held by the memory circuit. The memory circuit samples the first data at a timing when the first clock changes from a low level to a high level, and at the timing when the second clock changes from a low level to a high level. The flip-flop circuit according to claim 1, wherein the data is sampled. The memory circuit further samples the first data at a timing when the first clock changes from a high level to a low level, and at a timing when the second clock changes from a high level to a low level. The flip-flop circuit according to claim 2, wherein the second data is sampled. 3. The flip-flop circuit according to claim 2, wherein the storage circuit further samples the second data at a timing when the second clock changes from a high level to a low level. As the first clock enable signal, a signal indicating a header period of received data, and as the second clock enable signal, a signal indicating a tail period of received data,
The common clock is supplied to the first clock input terminal and the second clock input terminal so that the storage circuit performs sampling of a header period and a tail period of received data. The flip-flop circuit described.

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