JP2009077059A - Flip-flop circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a double edge trigger type flip-flop circuit needs to be provided with many transistors turning on and off with a clock signal and then charging and discharging electric power of a capacitor increases because of the clock signal. <P>SOLUTION: In the double edge trigger type flip-flop circuit 200, a first latch circuit 10 latches input data with one of a leading edge and a trailing edge of the clock signal. A second latch circuit 20 is provided in parallel to the first latch circuit 10, and latches the input data with the other of the leading edge and the trailing edge of the clock CLK. At least one of the first latch circuit 10 and the second latch circuit 20 is composed of an SRAM (Static Random Access Memory) type. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a double edge triggered flip-flop circuit.

  Various digital devices such as digital audio players are becoming widespread, and the demand for LSI (Large Scale Integration) that performs digital signal processing is increasing. In such an LSI, a large number of flip-flop circuits are mounted as basic elements of a sequential circuit.

  As energy saving is promoted, reduction of power consumption for LSI is required. Further, LSIs mounted on battery-driven devices such as portable devices are required to reduce power consumption from the viewpoint of extending driving time.

  Since 20% to 45% of the power consumed by the LSI is consumed as charge / discharge power of the capacity by the clock signal, this charge / discharge power reduction is effective in reducing the power consumption of the LSI. A double edge triggered flip-flop circuit has been proposed as a technique for reducing power consumption due to clock signal transitions.

  The double-edge triggered flip-flop circuit includes two latch circuits in parallel, one latch circuit latches input data at the rising edge of the clock signal, and the other latch circuit inputs at the falling edge of the clock signal. Latch data. The double edge triggered flip-flop circuit can achieve the same operation speed at half the clock frequency as compared with the single edge triggered flip-flop circuit. If the clock frequency is halved, the power consumed by the clock signal can be halved.

Patent Document 1 discloses a state machine. The state machine includes first latch means and second latch means, and the first latch means and the second latch means are alternately enabled according to the state of the clock signal.
JP-A-2-27811

  In the double edge trigger type flip-flop circuit, it is necessary to provide a large number of transistors that are turned on / off by a clock signal, and the charge / discharge power of the capacitor due to the clock signal increases.

  The present invention has been made in view of such circumstances, and an object thereof is to reduce power consumption in a double edge triggered flip-flop circuit.

  A flip-flop circuit according to an aspect of the present invention includes a first latch circuit that latches input data on one of a rising edge and a falling edge of a clock signal, and is provided in parallel with the first latch circuit. And a second latch circuit that latches input data at the other falling edge, and at least one of the first latch circuit and the second latch circuit is formed of an SRAM type.

  According to the present invention, power consumption can be reduced in a double edge triggered flip-flop circuit.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  FIG. 1 is a block diagram showing a basic configuration of a double edge triggered flip-flop circuit 100. The flip-flop circuit 100 includes a first latch circuit 10, a second latch circuit 20, and a multiplexer 30. The flip-flop circuit 100 includes an input terminal 40 to which input data D is input, a clock terminal 42 to which a clock signal CLK is input, and an output terminal 44 to which output data Q is output as input / output terminals.

  In the following description, it is assumed that the amplitude of the input data D is designed such that the low level is the ground potential as the low potential side fixed voltage source and the high level is the power supply potential Vdd as the high potential side fixed voltage source. Similarly, the amplitudes of the clock signal CLK and the inverted clock signal CLKB are designed such that the low level is the ground potential as the low potential side fixed voltage source and the high level is the power supply potential Vdd as the high potential side fixed voltage source. To do.

  The first latch circuit 10 and the second latch circuit 20 are provided in parallel between the input terminal 40 and the multiplexer 30. The first latch circuit 10 and the second latch circuit 20 are controlled so that the activated state and the deactivated period are alternately repeated, and at the same time point, either one is the activated period and the other is the deactivated period. Is done. Here, the activation period is a period for holding the latched data regardless of the input data D. The inactivation period is a period following the input data D. The activation period and the inactivation period may be read as an activated state and an inactivated state, respectively.

  In the flip-flop circuit 100 shown in FIG. 1, the first latch circuit 10 latches the input data D at the rising edge of the inverted clock signal CLKB, that is, the falling edge of the clock signal CLK. The second latch circuit 20 latches the input data D at the rising edge of the clock signal CLK. Thereby, the input data D can be latched at both the rising edge and falling edge of the clock signal CLK.

  The multiplexer 30 selectively outputs the output data of the first latch circuit 10 and the output data of the second latch circuit 20 according to the clock signal CLK.

  FIG. 2 is a diagram comparing the clock signal (S) supplied to the single edge triggered flip-flop circuit and the clock signal (D) supplied to the double edge triggered flip-flop circuit. In FIG. 2, in the former clock signal (S), the rising edge is the latch timing. On the other hand, in the latter clock signal (D), both the rising edge and the falling edge are the latch timing. As described above, the double edge trigger type flip-flop circuit can realize an operation speed equivalent to that of the single edge trigger type at half the frequency.

  FIG. 3 is a circuit diagram showing a configuration of a general double edge triggered flip-flop circuit 100. The flip-flop circuit 100 includes a first latch circuit 10, a second latch circuit 20, a first output switch OS1, a second output switch OS2, and a fifth inverter IN5. The first output switch OS1 and the second output switch OS2 implement the function of the multiplexer 30 shown in FIG. The first output switch OS1 is connected to the output terminal of the first latch circuit 10, and the second output switch OS2 is connected to the output terminal of the second latch circuit 20.

  The fifth inverter IN5 is for outputting the input data D input or latched to the first latch circuit 10 and the second latch circuit 20 in the same phase. When input or latched input data D is output in reverse phase, it is not necessary to provide it. In addition, the structure which outputs both output data Q and the inversion output data of the reverse phase may be sufficient.

  The first latch circuit 10 latches the input data D on one of the rising edge and falling edge of the clock signal. The first latch circuit 10 includes a first inverter IN1, a second inverter IN2, a first input switch IS1, and a first feedback switch FS1.

  The first input switch IS1 is connected to the input terminal of the first inverter IN1. The first inverter IN1 receives the input data D, inverts it, and outputs it. The second inverter IN2 receives the output data of the first inverter IN1, inverts it, and feeds it back to the input of the first inverter IN1. The first feedback switch FS1 is provided between the output terminal of the second inverter IN2 and the input terminal of the first inverter IN1.

  The second latch circuit 20 is provided in parallel with the first latch circuit 10 and latches the input data D at the other of the rising edge and the falling edge of the clock signal. The second latch circuit 20 includes a third inverter IN3, a fourth inverter IN4, a second input switch IS2, and a second feedback switch FS2.

  The second input switch IS2 is connected to the input terminal of the third inverter IN3. The third inverter IN3 receives the input data D, inverts it, and outputs it. The fourth inverter IN4 receives the output data of the third inverter IN3, inverts it, and feeds it back to the input of the third inverter IN3. The second feedback switch FS2 is provided between the output terminal of the fourth inverter IN4 and the input terminal of the third inverter IN3.

  The first input switch IS1, the second input switch IS2, the first output switch OS1, the second output switch OS2, the first feedback switch FS1, and the second feedback switch FS2 are composed of complementary switches. The complementary switch is composed of a combination of an N channel transistor (hereinafter referred to as an Nch transistor) and a P channel transistor (hereinafter referred to as a Pch transistor). These transistors employ MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The complementary switch utilizes the fact that the increase characteristic of the ON resistance of the Nch transistor and the Pch transistor has a characteristic opposite to the input voltage level. By adopting the complementary switch, the restriction due to the threshold voltage of the transistor can be relaxed and the dullness of the output voltage level can be suppressed.

  In the flip-flop circuit 100 shown in FIG. 3, when the first latch circuit 10 is controlled to be in the activated state and the second latch circuit 20 is inactivated, the first input is generated by the clock signal CLK and the inverted clock signal CLKB. The switch IS1, the second output switch OS2, and the second feedback switch FS2 are turned off, and the second input switch IS2, the first output switch OS1, and the first feedback switch FS1 are turned on.

  On the other hand, when the first latch circuit 10 is controlled to be inactive and the second latch circuit 20 is controlled to be active, the first input switch IS1, the second output switch OS2, and the clock signal CLK and the inverted clock signal CLKB The second feedback switch FS2 is turned on, and the second input switch IS2, the first output switch OS1, and the first feedback switch FS1 are turned off.

  FIG. 4 is a timing chart showing an operation example of the flip-flop circuit 100 shown in FIG. Referring to FIG. 4, it can be seen that when the clock signal CLK is at a high level, the input data D is latched by the first latch circuit 10 and the data latched by the second latch circuit 20 is output. On the contrary, when the clock signal CLK is at the low level, the input data D is latched by the second latch circuit 20 and the data latched by the first latch circuit 10 is output.

  FIG. 5 is a circuit diagram showing a configuration of the double edge triggered flip-flop circuit 110 according to the first embodiment of the present invention. Compared with the flip-flop circuit 100 shown in FIG. 3, the flip-flop circuit 110 has a configuration in which a feedback inverter in the first latch circuit 10 and the second latch circuit 20 is shared. That is, the second inverter IN2 and the fourth inverter IN4 shown in FIG. 3 are shared, and the fourth inverter IN4 is omitted.

  The basic configuration of the flip-flop circuit 110 according to the first embodiment is the same as that of the flip-flop circuit 100 shown in FIG. 3, and differences will be described below. The second latch circuit 20 includes a third inverter IN3, a second input switch IS2, and a second feedback switch FS2. The second latch circuit 20 uses the second inverter IN2 included in the first latch circuit 10 when in the activated state.

  The second inverter IN2 is disconnected from the first inverter IN1 and connected to the third inverter IN3 when the first latch circuit 10 is inactive and the second latch circuit 20 is activated. The output data is received, inverted, and fed back to the input of the third inverter IN3. Conversely, when the first latch circuit 10 is in the activated state and the second latch circuit 20 is in the inactivated state, it is disconnected from the third inverter IN3 and connected to the first inverter IN1, and the output data of the first inverter IN1 is used. It receives, inverts, and returns to the input of 1st inverter IN1.

  The first output switch OS1 is provided between the output terminal of the first inverter IN1 and the input terminal of the second inverter IN2. The second output switch OS2 is provided between the output terminal of the third inverter IN3 and the input terminal of the second inverter IN2.

  The operation of the flip-flop circuit 110 according to Embodiment 1 is similar to the operation of the flip-flop circuit 100 illustrated in FIG.

  As described above, according to the first embodiment, the circuit scale can be reduced in the double edge triggered flip-flop circuit. That is, as compared with the flip-flop circuit 100 shown in FIG. 3, one inverter can be omitted while realizing the same operation. Further, power consumption by the inverter can be reduced.

  Further, in the flip-flop circuit 100 shown in FIG. 3, no switch is provided between the output terminal of the first inverter IN1 and the input terminal of the second inverter IN2, and it is not possible to electrically disconnect them. Therefore, when the first latch circuit 10 is inactive, the first inverter IN1 and the second inverter IN2 operate in synchronization with the input data D in the flip-flop circuit 100 shown in FIG. On the other hand, in the flip-flop circuit 110 according to the first embodiment, the first output switch OS1 is provided between the output terminal of the first inverter IN1 and the input terminal of the second inverter IN2. Therefore, when the first latch circuit 10 is in an inactive state, in the flip-flop circuit 110 according to the first embodiment, the second inverter IN2 is cut off by the first output switch OS1, and only the first inverter IN1 receives the input data D. Operates synchronously.

  Therefore, according to the first embodiment, when the first latch circuit 10 is in an inactive state, the number of transistors driven in synchronization with the input data D can be reduced, and power consumption can be reduced accordingly. can do. For example, when the second inverter IN2 is composed of two transistors, the number of transistors driven in synchronization with the input data D can be reduced by two as compared with the flip-flop circuit 100 shown in FIG. . In particular, when the transition frequency of the input data D in FIG. 4 at irregular intervals is high, the effect of reducing the power consumption due thereto is further increased. Note that the hatched period of the input data D in FIG. 4 represents an indefinite period.

  FIG. 6 is a circuit diagram showing a configuration of a double edge triggered flip-flop circuit 120 according to the first modification of the first embodiment. Compared with the flip-flop circuit 110 shown in FIG. 5, the flip-flop circuit 120 has a configuration in which the fifth inverter IN5 is omitted. Instead, the output data of the flip-flop circuit 120 is supplied from the output terminal of the second inverter IN2.

  As described above, according to the first modification of the first embodiment, the circuit scale can be reduced in the double edge triggered flip-flop circuit. That is, as compared with the flip-flop circuit 100 shown in FIG. 3, two inverters can be omitted while realizing the same operation. Moreover, the power consumption by these inverters can be reduced. However, as compared with the flip-flop circuit 110 shown in FIG. 5, the first feedback switch FS1, the second feedback switch FS2, and the subsequent elements are all driven by the output voltage of the second inverter IN2. In this respect, the flip-flop circuit 110 shown in FIG. 5 can drive a subsequent element with the output voltage of the fifth inverter IN5, and thus can be designed flexibly. For example, the size of the fifth inverter IN5 can be designed larger than that of the third inverter IN3 in order to improve the accuracy of signal transition to the subsequent stage. The effect of providing the first output switch OS1 between the output terminal of the first inverter IN1 and the input terminal of the second inverter IN2 is the same as that of the flip-flop circuit 110 shown in FIG.

  FIG. 7 is a circuit diagram showing a configuration of a double edge triggered flip-flop circuit 130 according to the second modification of the first embodiment. Compared with the flip-flop circuit 120 shown in FIG. 6, the flip-flop circuit 130 includes a first Pch transistor PM1 and a second Pch transistor PM2, and the first feedback switch FS1 and the second feedback switch FS2 are changed from the complementary switch. In this configuration, the 1Nch transistor NM1 and the second Nch transistor NM2 are replaced.

The basic configuration of the flip-flop circuit 130 according to the second modification of the first embodiment is the same as the configuration of the flip-flop circuit 120 shown in FIG. 6, and differences will be described below.
The first latch circuit 10 further includes a first Pch transistor PM1. The first Pch transistor PM1 is provided between the input terminal of the first inverter IN1 and the power supply potential Vdd. Its source terminal is connected to the power supply potential Vdd, its drain terminal is connected to the input terminal of the first inverter IN1, and its gate terminal receives the output data of the first inverter IN1. The first feedback switch FS1 is not a complementary switch but includes a first Nch transistor NM1.

  The second latch circuit 20 further includes a second Pch transistor PM2. The second Pch transistor PM2 is provided between the input terminal of the third inverter IN3 and the power supply potential Vdd. Its source terminal is connected to the power supply potential Vdd, its drain terminal is connected to the input terminal of the third inverter IN3, and its gate terminal receives the output data of the third inverter IN3. The second feedback switch FS2 is not a complementary switch, but includes a second Nch transistor NM2.

  When the first feedback switch FS1 and the second feedback switch FS2 are configured by the first Nch transistor NM1 and the second Nch transistor NM2, when the output data of the first inverter IN1 and the third inverter IN3 transition from the high level to the low level, that is, When the output data of the second inverter IN2 transitions from the low level to the high level, the input voltages of the first inverter IN1 and the third inverter IN3 become dull.

  Therefore, in the second modification, when the output data of the first inverter IN1 and the third inverter IN3 transition from the high level to the low level, the first inverter IN1 and the third inverter are passed through the first Pch transistor PM1 and the second Pch transistor PM2. The output data of the inverter IN3 is fed back to its input. Specifically, the first Pch transistor PM1 and the second Pch transistor PM2 become conductive when a low level is input to their gate terminals, and charge the third node N3 and the fourth node N4. On the other hand, when a high level is input to the gate terminal, the gate node is cut off and the third node N3 and the fourth node N4 are not charged.

  That is, when the output data of the first inverter IN1 and the third inverter IN3 transition from the high level to the low level, the first Pch transistor PM1 and the second Pch transistor PM2 are used as a feedback system. On the other hand, when the output data transitions from the low level to the high level, the first Nch transistor NM1 and the second Nch transistor NM2 are used as a feedback system.

  As described above, according to the second modification of the first embodiment, the same effect as that of the first modification of the first embodiment is obtained. In addition, the following effects are achieved. That is, the number of MOS switches whose gate capacitance is charged / discharged by the clock signal CLK and the inverted clock signal CLKB can be reduced. Specifically, since the complementary switch is composed of two MOS switches, in the first modification, twelve MOS switches are controlled by the clock signal CLK and the inverted clock signal CLKB, but in the second modification, ten MOS switches. The switch is controlled by the clock signal CLK and the inverted clock signal CLKB.

  In the second modification, two MOS switches, that is, a first Pch transistor PM1 and a second Pch transistor PM2 are added, but these MOS switches are driven by output data of the first inverter IN1 and the third inverter IN3. Generally, the former is higher in clock signal transition frequency and data transition frequency. Therefore, the gate load of the entire MOS switch is reduced, and the power consumption of the entire flip-flop circuit 130 can be reduced.

  FIG. 8 is a circuit diagram showing a configuration of a double edge triggered flip-flop circuit 140 according to the third modification of the first embodiment. Compared with the flip-flop circuit 130 shown in FIG. 7, the flip-flop circuit 140 has a configuration in which the second inverter IN2 is replaced with a third Nch transistor NM3 and a fifth inverter IN5 is added.

The basic configuration of the flip-flop circuit 140 according to the third modification of the first embodiment is the same as the configuration of the flip-flop circuit 130 shown in FIG. 7, and differences will be described below.
The first latch circuit 10 includes a third Nch transistor NM3 instead of the second inverter IN2.

  The source terminal of the third Nch transistor NM3 is connected to the ground potential, its drain terminal is connected to the input terminals of the first inverter IN1 and the third inverter IN3 via the first Nch transistor NM1 and the second Nch transistor NM2, and its gate terminal is The output data of the first inverter IN1 and the third inverter IN3 are received. The third Nch transistor NM3 becomes conductive when a high level is input to its gate terminal, and discharges the charge of the fifth node N5.

  The fifth inverter IN5 is connected to the output terminals of the first inverter IN1 and the third inverter IN3 via the first output switch OS1 and the second output switch OS2. A configuration in which the output voltage level of the fifth node N5 is used as output data of the flip-flop circuit 140 without providing the fifth inverter IN5 is also possible.

  As described above, according to the third modification of the first embodiment, the same effect as that of the second modification of the first embodiment is obtained. In addition, the following effects are achieved. That is, the number of transistors can be reduced by replacing the second inverter IN2 with the third Nch transistor NM3. This is because an inverter usually needs to be configured by combining two or more transistors. Therefore, in modification 3, the circuit scale and power consumption can be further reduced.

  FIG. 9 is a circuit diagram showing a configuration of a double edge triggered flip-flop circuit 150 according to the fourth modification of the first embodiment. Compared with the flip-flop circuit 140 shown in FIG. 8, the flip-flop circuit 150 has a configuration in which the first input switch IS1 and the second input switch IS2 are replaced by the fourth Nch transistor NM4 and the fifth Nch transistor NM5 from the complementary switches. is there.

  When the first input switch IS1 and the second input switch IS2 are configured by the fourth Nch transistor NM4 and the fifth Nch transistor NM5, when the input data D transitions from the low level to the high level, the third node N3 and the fourth node N4 Is transmitted with dull input data D. The third node N3 and the fourth node N4 are nodes of a loop circuit configured by the first inverter IN1 and the first Pch transistor PM1, and a loop circuit configured by the third inverter IN3 and the second Pch transistor PM2, respectively. is there. Therefore, the potentials of the third node N3 and the fourth node N4 reach the high level when they exceed the threshold voltages of the first inverter IN1 and the third inverter IN3, respectively. Therefore, the influence of the blunting mentioned above is greatly relieved.

  As described above, according to the fourth modification of the first embodiment, the same effect as that of the third modification of the first embodiment is obtained. In addition, the following effects are achieved. That is, by replacing the first input switch IS1 and the second input switch IS2 with the fourth Nch transistor NM4 and the fifth Nch transistor NM5 from the complementary switches, the number of transistors can be reduced. Therefore, in Modification 4, the circuit scale and power consumption can be further reduced.

  FIG. 10 is a circuit diagram showing a configuration of a double edge triggered flip-flop circuit 200 according to Embodiment 2 of the present invention. The flip-flop circuit 200 includes a first latch circuit 10, a second latch circuit 20, a first output switch OS1, a second output switch OS2, a fifth inverter IN5, and a sixth inverter IN6.

  The first output switch OS1 is connected to the output terminal of the first latch circuit 10. The second output switch OS2 is connected to the output terminal 44 of the second latch circuit. The first output switch OS1 and the second output switch OS2 are each configured by a complementary switch in which an N-channel transistor and a P-channel transistor are combined.

  The sixth inverter IN6 receives the input data D, inverts it, and outputs it to both the first latch circuit 10 and the second latch circuit 20. The fifth inverter IN5 inverts and outputs the output data of the first latch circuit 10 and the second latch circuit 20. In the second embodiment, the output data of the first latch circuit 10 and the second latch circuit 20 are in phase with the input data D. Of course, a configuration in which the fifth inverter IN5 is not provided is also possible.

  The first latch circuit 10 latches input data on one of the rising edge and falling edge of the clock signal. The second latch circuit 20 is provided in parallel with the first latch circuit 10 and latches input data at the other of the rising edge and the falling edge of the clock signal. At least one of the first latch circuit 10 and the second latch circuit 20 is an SRAM type. In the following description, an example in which both are configured with SRAM type will be described. Note that either one of the latch circuits described in Embodiment 1 or other latch circuits may be used.

  The first latch circuit 10 includes a first inverter IN1, a second inverter IN2, a first transistor pair MP1, and a first activation transistor EM1. The first transistor pair MP1 includes a sixth Nch transistor NM6 and a seventh Nch transistor NM7. Input data D is input to the gate terminal of the sixth Nch transistor NM6, and output data of the sixth inverter IN6, that is, inverted data of the input data D, is input to the gate terminal of the seventh Nch transistor NM7. Therefore, the sixth Nch transistor NM6 and the seventh Nch transistor NM7 are turned on and off in a complementary manner.

  The drain terminal of the sixth Nch transistor NM6 is connected to the input terminal of the first inverter IN1 and the output terminal of the second inverter IN2. The drain terminal of the seventh Nch transistor NM7 is connected to the input terminal of the second inverter IN2 and the output terminal of the first inverter IN1. The source terminals of the sixth Nch transistor NM6 and the seventh Nch transistor NM7 are commonly connected.

  The first activation transistor EM1 activates the first transistor pair MP1 in the conductive state. The first activation transistor EM1 is composed of an Nch transistor, and the inverted clock signal CLKB is input to its gate terminal. Its source terminal is connected to the ground potential, and its drain terminal is connected to the common source terminal of the first transistor pair MP1.

  The first latch circuit 10 operates as follows. When the first transistor pair MP1 is activated, the entire first latch circuit 10 is deactivated, and when the first transistor pair MP1 is deactivated, the entire first latch circuit 10 is activated.

  More specifically, when the first activation transistor EM1 becomes conductive, the first transistor pair MP1 is activated. In this state, one of the sixth Nch transistor NM6 and the seventh Nch transistor NM7 constituting the first transistor pair MP1 is turned on. The drain terminal voltage of the conductive transistor becomes low level, and the input terminal voltage of the first inverter IN1 or the second inverter IN2 connected to the drain terminal becomes low level.

  More specifically, when the input data D is at a high level, the sixth Nch transistor NM6 is turned on, and the input terminal of the first inverter IN1 is at a low level. Therefore, the first inverter IN1 outputs a high level. When the input data D is at a low level, the seventh Nch transistor NM7 conducts, the second inverter IN2 outputs a high level, and the first inverter IN1 outputs a low level. As described above, the output of the first latch circuit 10 follows the input data D in phase.

  On the other hand, when the first activation transistor EM1 is cut off, the first transistor pair MP1 is deactivated. In this state, the first inverter IN1 and the second inverter IN2 form a loop circuit, and latch the input data D when the first transistor pair MP1 is deactivated.

  The second latch circuit 20 includes a third inverter IN3, a fourth inverter IN4, a second transistor pair MP2, and a second activation transistor EM2. The second transistor pair MP2 includes an eighth Nch transistor NM8 and a ninth Nch transistor NM9. The configuration and operation of the second latch circuit 20 are the same as the configuration and operation of the first latch circuit 10 except that the signal input to the gate terminal of the second activation transistor EM2 is the clock signal CLK. Description is omitted.

  Based on the above description, the overall operation of the flip-flop circuit 200 will be described below. When the first latch circuit 10 is controlled to be activated and the second latch circuit 20 is controlled to be inactivated, the first activation transistor EM1 and the second output switch OS2 are turned off and the second activation is performed by the clock signal. The transistor EM2 and the first output switch OS1 are controlled to be on. On the other hand, when the first latch circuit 10 is inactivated and the second latch circuit 20 is activated, the first activation transistor EM1 and the second output switch OS2 are turned on by the clock signal, and the second latch circuit 20 is activated. The activation transistor EM2 and the first output switch OS1 are controlled to be turned off. A specific example of the operation timing is the same as the timing chart shown in FIG. 4 except that the output data of the first latch circuit 10 and the second latch circuit 20 are in phase with the input data D.

  As described above, according to the second embodiment, power consumption can be reduced in the double edge triggered flip-flop circuit. That is, compared with the flip-flop circuit 100 shown in FIG. 3, the number of MOS switches whose gate capacitances are charged / discharged by the clock signal CLK and the inverted clock signal CLKB can be reduced while realizing the same operation. Thereby, the charge / discharge power of the capacity by the clock signal can be reduced. Compared with the flip-flop circuit 100 shown in FIG.

  In the second embodiment, four MOS switches, that is, a sixth Nch transistor NM6, a seventh Nch transistor NM7, an eighth Nch transistor NM8, and a ninth Nch transistor NM9 are added. These MOS switches are driven by input data D or its inverted data. Generally, the former is higher in clock signal transition frequency and data transition frequency. Therefore, the gate load of the entire MOS switch is reduced, and the power consumption of the entire flip-flop circuit 200 can be reduced.

  Next, a third embodiment will be described. The third embodiment relates to a clock control circuit that generates a clock signal to be supplied to a double edge triggered flip-flop circuit in which a non-use period is set.

  FIG. 11 is a block diagram showing a configuration of a general clock control circuit 50 that controls a clock signal to be supplied to the flip-flop circuit and a semiconductor integrated device 300 on which the clock control circuit 50 is mounted. The semiconductor integrated device 300 includes a clock control circuit 50 and a flip-flop circuit 100.

  The flip-flop circuit 100 is a double edge triggered flip-flop circuit in which a non-use period is set. The flip-flop circuit 100 is not limited to the configuration shown in FIG. 3, but may have any configuration shown in FIGS. Further, the configuration is not limited to the above-described configuration, and any configuration may be used as long as it is a double edge trigger flip-flop circuit in which a non-use period is set. In FIG. 11, one flip-flop circuit 100 is drawn for convenience, but a circuit block including a plurality of flip-flop circuits 100 may be a unit controlled by an output signal of the clock control circuit 50.

  The clock control circuit 50 includes an AND gate 51. The AND gate 51 receives the first clock signal CLK1 and the enable signal E, and outputs a second clock signal CLK2. The second clock signal CLK2 is supplied to the flip-flop circuit 100.

  The first clock signal CLK1 may be a system clock or a clock obtained by multiplying the system clock. Any signal having periodicity may be used. The enable signal E indicates the usage state of the flip-flop circuit 100. For example, a significant signal is output when the flip-flop circuit 100 is in use, and a non-significant signal is output when not in use. Here, the non-use period may be a standby period. In the following description, a significant signal is a high level and an insignificant signal is a low level. Of course, the reverse setting is also possible.

  FIG. 12 is a timing chart showing an operation example of the clock control circuit 50 shown in FIG. Since the clock control circuit 50 includes an AND gate 51, the first clock signal CLK1 is output from the AND gate 51 as it is when the enable signal E is at a high level, and the AND gate 51 when the enable signal E is at a low level. Outputs a low level. Thereby, the transition of the second clock signal CLK2 can be stopped while the flip-flop circuit 100 is not used.

  Referring to FIG. 12, the second clock signal CLK2 also changes from the high level to the low level at the falling edge when the enable signal E changes from the high level to the low level. This edge e1 is a useless transition. That is, when the flip-flop circuit 100 transitions to the non-use period, it is not necessary to change the data held by the flip-flop circuit 100. Rather, the data should be retained during the non-use period, and when returning to the use period, the operation should be resumed from the state where the data was retained.

  In the single edge triggered flip-flop circuit shown in FIG. 2, the falling edge of the clock signal is not triggered, but in the double edge triggered flip-flop circuit, the falling edge of the clock signal is also triggered. Therefore, the content of the data held in the flip-flop circuit 100 is updated by the falling edge e1 of the second clock signal CLK2, which causes a malfunction when returning to the use period.

  FIG. 13 is a block diagram showing a configuration of a clock control circuit 60 for controlling a clock signal to be supplied to the flip-flop circuit and a semiconductor integrated device 310 having the clock control circuit 60 according to the third embodiment. The semiconductor integrated device 310 includes a clock control circuit 60 and a flip-flop circuit 100. The clock control circuit 60 includes an edge detection circuit 61, an AND gate 64, and a T-type flip-flop circuit 65.

  The edge detection circuit 61 receives the first clock signal CLK1 and outputs a pulse signal having a predetermined width to the AND gate 64 when detecting the edge. Here, the detection target edges are both rising edges and falling edges.

  For example, the edge detection circuit 61 includes a delay circuit 62 and an XOR gate 63. The delay circuit 62 delays the first clock signal CLK1 for a predetermined period and outputs it to the XOR gate 63. The delay circuit 62 may be configured by cascading even-numbered inverters. By adjusting the number of stages, the width of the pulse signal can be adjusted. The XOR gate 63 receives the output signal of the delay circuit 62 and the first clock signal CLK1, and outputs the calculation result to the AND gate 64. This calculation result is that a pulse signal having a predetermined width is generated each time an edge of the first clock signal CLK1 is detected.

  The AND gate 64 receives the output signal of the edge detection circuit 61 and the enable signal E, and outputs a signal that follows the output signal of the edge detection circuit 61 to the T-type flip-flop circuit 65 while the enable signal E is significant. A signal of a non-significant level is output to the T-type flip-flop circuit 65 while the enable signal E is non-significant. Specifically, the output signal of the edge detection circuit 61 is output as it is when the enable signal E is at a high level, and the low level is output when the enable signal E is at a low level.

  The T-type flip-flop circuit 65 receives the output signal of the AND gate 64 and outputs a signal whose logic level is inverted to the double-edge triggered flip-flop circuit 100 every time a pulse signal having a predetermined width is detected.

  FIG. 14 is a timing chart illustrating an operation example of the clock control circuit 50 according to the third embodiment. The XOR gate 63 outputs a low level when the logic levels of the two input signals are the same level, and outputs a high level at different levels. Therefore, when the delay period by the delay circuit 62 has passed, the logic levels of the two input signals become the same level, so the XOR gate 63 outputs a low level. Therefore, the output signal of the XOR gate 63 generates a pulse signal having a predetermined width every time the edge of the first clock signal CLK1 is detected.

  The AND gate 64 masks the output signal of the XOR gate 63 while the enable signal E is at a low level. The T-type flip-flop circuit 65 inverts the logic level of the output signal of the T-type flip-flop circuit 65 itself at the rising edge of the output signal of the AND gate 64, and at its falling edge of the output signal of the AND gate 64. Maintain the logic level of the output signal. Therefore, in the T-type flip-flop circuit 65, when one pulse signal is detected, the logic level of the output signal is inverted once.

  Comparing FIG. 14 with FIG. 12, it can be seen that the useless edge e1 does not occur in FIG. Note that after the flip-flop circuit 100 returns from the inactive state to the active state, the phase of the second clock signal CLK2 is opposite to that of the first clock signal CLK1. In this respect, in the double edge trigger type flip-flop circuit 100, only the data D latched by the first latch circuit 10 and the second latch circuit 20 is switched, and the output signal of the flip-flop circuit 100 has a latch timing. If they are the same, it is the same whether the first latch circuit 10 or the second latch circuit 20 is latched.

  As described above, according to the third embodiment, when generating a clock signal to be supplied to a double edge triggered flip-flop circuit in which a non-use period is set, a malfunction of the flip-flop circuit can be reduced with a simple configuration. Can be suppressed. That is, the second clock signal CLK2 transitions in synchronization with the edge detection of the first clock signal CLK1 during a period when the enable signal E is significant. On the other hand, when the enable signal E transitions insignificantly, the second clock signal CLK2 maintains the previous logic level.

  Therefore, useless logic level transition of the second clock signal CLK2 due to logic level transition of the enable signal E can be suppressed, and malfunction of the flip-flop circuit 100 can be prevented.

  Further, the logic level of the second clock signal CLK2 when the supply of the second clock signal CLK2 is stopped is compared with the logic level of the first clock signal CLK1 when the supply is resumed, and according to the result. There is also a method for controlling the phase of the second clock signal CLK2. However, it is necessary to maintain the logic level of the second clock signal CLK2 when the supply of the second clock signal CLK2 is stopped, which increases the circuit area.

  On the other hand, in the third embodiment, it is not necessary to store the logic level, and the circuit configuration can be simplified. Further, the clock control circuit 60 according to the third embodiment is simple in that it only inverts the logic level of the second clock signal CLK2 every time the edge of the first clock signal CLK1 is detected during a period when the enable signal E is significant. Based on a simple algorithm. Therefore, malfunction in the clock control circuit 60 can be suppressed and the highly reliable second clock signal CLK2 can be generated.

  It will be understood by those skilled in the art that the above-described embodiment is an exemplification, and that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. By the way.

  In the first embodiment, an example in which an Nch transistor is used instead of a complementary switch has been described. However, a Pch transistor may be used instead of an Nch transistor. In that case, a signal input to the gate terminal may be appropriately changed from the clock signal CLK to the inverted clock signal CLKB and from the inverted clock signal CLKB to the clock signal CLK.

  In addition, each logic gate described in Embodiment 3 can be appropriately replaced as long as it is a logic gate having the same truth table.

It is a block diagram which shows the basic composition of a double edge trigger type flip-flop circuit. It is the figure which compared the clock signal (S) supplied to a single edge trigger type flip-flop circuit, and the clock signal (D) supplied to a double edge trigger type flip-flop circuit. It is a circuit diagram which shows the structure of a general double edge trigger type flip-flop circuit. 4 is a timing chart illustrating an operation example of the flip-flop circuit illustrated in FIG. 3. 1 is a circuit diagram showing a configuration of a double edge triggered flip-flop circuit according to a first embodiment of the present invention. 6 is a circuit diagram showing a configuration of a double edge triggered flip-flop circuit according to a first modification of the first embodiment. FIG. FIG. 6 is a circuit diagram showing a configuration of a double edge trigger flip-flop circuit according to a second modification of the first embodiment. FIG. 10 is a circuit diagram showing a configuration of a double edge triggered flip-flop circuit according to a third modification of the first embodiment. FIG. 10 is a circuit diagram showing a configuration of a double edge triggered flip-flop circuit according to a fourth modification of the first embodiment. It is a circuit diagram which shows the structure of the double edge trigger type flip-flop circuit which concerns on Embodiment 2 of this invention. 1 is a block diagram showing a configuration of a general clock control circuit that controls a clock signal to be supplied to a flip-flop circuit and a semiconductor integrated device in which the clock control circuit is mounted. 12 is a timing chart illustrating an operation example of the clock control circuit illustrated in FIG. 11. FIG. 6 is a block diagram showing a configuration of a clock control circuit for controlling a clock signal to be supplied to a flip-flop circuit and a semiconductor integrated device having the clock control circuit according to a third embodiment. 12 is a timing chart illustrating an operation example of the clock control circuit according to the third embodiment.

Explanation of symbols

  IS1 first input switch, OS1 first output switch, FS1 first feedback switch, IN1 first inverter, PM1 first Pch transistor, NM1 first Nch transistor, MP1 first transistor pair, EM1 first activation transistor, IS2 second input Switch, OS2 second output switch, FS2 second feedback switch, IN2 second inverter, PM2 second Pch transistor, NM2 second Nch transistor, MP2 second transistor pair, EM2 second activation transistor, IN3 third inverter, NM3 third Nch Transistor, IN4 fourth inverter, NM4 fourth Nch transistor, IN5 fifth inverter, NM5 fifth Nch transistor, IN6 sixth inverter, NM6 6th Nch transistor, NM7 7th Nch transistor, NM8 8th Nch transistor, NM9 9th Nch transistor, 10 1st latch circuit, 20 2nd latch circuit, 30 multiplexer, 40 input terminal, 42 clock terminal, 44 output terminal, 50 clock control circuit 51 AND gate, 60 clock control circuit, 61 edge detection circuit, 62 delay circuit, 63 XOR gate, 64 AND gate, 65 T-type flip-flop circuit, 100 flip-flop circuit, 110 flip-flop circuit, 120 flip-flop circuit, 130 Flip-flop circuit, 140 flip-flop circuit, 150 flip-flop circuit, 200 flip-flop circuit, 300 semiconductor integrated device, 310 Semiconductor integrated device.

Claims (3)

A first latch circuit that latches input data on one of a rising edge and a falling edge of a clock signal;
A second latch circuit provided in parallel with the first latch circuit and latching the input data at the other of the rising edge and the falling edge of the clock signal;
A flip-flop circuit in which at least one of the first latch circuit and the second latch circuit is configured as an SRAM (Static Random Access Memory) type. A first output switch connected to an output terminal of the first latch circuit;
A second output switch connected to the output terminal of the second latch circuit,
The first latch circuit includes:
A first transistor pair to which the input data and its inverted data are input;
A first activation transistor that activates the first transistor pair in a conductive state;
The second latch circuit includes:
A second transistor pair to which the input data and its inverted data are input;
A second activation transistor that activates the second transistor pair in a conductive state;
When the first latch circuit is controlled to be in an activated state in which the latched data is held and in an inactivated state in which the second latch circuit follows the input data, the first active circuit is activated by the clock signal And the second activation transistor and the first output switch are controlled to be turned on.
When the first latch circuit is controlled to the inactive state and the second latch circuit is controlled to the active state, the clock signal causes the first activation transistor and the second output switch to be turned on, and 2. The flip-flop circuit according to claim 1, wherein the second activation transistor and the first output switch are controlled to be off. The first output switch and the second output switch are each composed of a complementary switch in which an N-channel transistor and a P-channel transistor are combined,
3. The flip-flop circuit according to claim 2, wherein each of the first activation transistor and the second activation transistor includes one transistor.

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