CN110635784A

CN110635784A - Hold-free dynamic D flip-flop

Info

Publication number: CN110635784A
Application number: CN201810667264.0A
Authority: CN
Inventors: 刘杰尧; 张楠赓; 吴敬杰; 马晟厚
Original assignee: Canaan Creative Co Ltd
Current assignee: Canaan Creative Co Ltd
Priority date: 2018-06-25
Filing date: 2018-06-25
Publication date: 2019-12-31
Also published as: EA202092706A1

Abstract

The invention provides a hold-free dynamic D trigger applied in computing equipment, which comprises an input end, an output end and a clock signal end, wherein the input end is connected with the clock signal end; the first latch unit is used for transmitting the data of the input end and latching the data under the control of a clock signal; the second latch unit is used for latching the data at the output end and transmitting the data latched by the first latch unit in an inverted way under the control of a clock signal; an output driving unit for inverting and outputting the data received from the second latch unit; the first latch unit, the second latch unit and the output driving unit are sequentially connected in series between the input end and the output end; the second latch unit outputs three states of high level, low level and high resistance through a single element under the control of a clock signal; the first latch unit adopts a delay unit. The back-end layout wiring process can be simplified, the design difficulty is reduced, the performance is improved, and the practicability is improved.

Description

Hold-free dynamic D flip-flop

Technical Field

The present invention relates to a clocked memory device, and more particularly, to a hold-free dynamic D flip-flop for use in a computing device.

Background

Virtual currency (e.g., bitcoin, ethernet) is a digital currency in the form of P2P, which has received much attention since the 2009 bitcoin system. The system constructs the distributed shared general ledger based on the block chain, thereby ensuring the safety, reliability and decentralization of the system operation.

In hashing and proof of workload, bitcoin is the only correct hash value calculated to prove the workload to obtain accounting packed block right and thus the reward, which is proof of workload (Pow).

At present, no effective algorithm is available for hash operation except for brute force calculation. The bitcoin mining starts with low-cost hardware such as a CPU or a GPU, but with the prevalence of bitcoins, the mining process changes greatly. Today, excavation activities are transferred to Field Programmable Gate Arrays (FPGAs) or application specific chips (ASICs), which are very efficient in excavation mode.

The D trigger has wide application and can be used as a register of a digital signal, a shift register, a frequency division generator, a waveform generator and the like. The D flip-flop has two inputs, Data and Clock (CLK), with one output (Q), into or from which Data can be written or read.

CN1883116A discloses a positive feedback D flip-flop circuit 106 as shown in fig. 1, comprising an analog switch 300, an inverter 302, an analog switch 304, an inverter 306, an inverter 308, an analog switch 310, an inverter 312, and an analog switch 314. The

analog switches

300, 304, 310, and 314 are analog switches using P-channel/N-channel transistors, and perform switching operations by CKP in phase with CK and CKN in phase opposite to CK.

Inverters

302, 306,

inverters

308, and 312 are CMOS inverters. It can be seen that a conventional D flip-flop basically needs 16 PMOS/NMOS transistors, which occupies a large area.

For a new generation of computing devices for mining virtual digital currency, the mining process is a logical computing pipeline that performs a large number of iterations, requiring several D-flip-flops to store data. Therefore, in a computing device requiring a large number of D flip-flops, the defects of increased chip area, slow operation speed and poor control of leakage can be caused.

CN1883116A also discloses a dynamic D flip-flop circuit 102 as shown in fig. 2, where the dynamic D flip-flop circuit 102 includes a 1 st analog switch 200, a 1 st inverter 202, a 2 nd analog switch 204, and a 2 nd inverter 206. The dynamic D flip-flop circuit 102 constitutes a sample-and-hold circuit by an analog switch of the 1 st analog switch 200 and the 2 nd analog switch 204, and a parasitic capacitance such as a gate capacitance and a wiring capacitance of the 1 st inverter 202 and the 2 nd inverter 206.

The register composed of the dynamic D trigger has the problems that an analog switch is difficult to control and the access speed is low.

Disclosure of Invention

In order to solve the above problems, the present invention provides a hold-free dynamic D flip-flop for a computing device, which can effectively reduce design difficulty, reduce chip area, reduce power consumption, and implement clock synchronization.

In order to achieve the above object, the present invention provides a hold-free dynamic D flip-flop, comprising:

an input terminal, an output terminal and a clock signal terminal;

the first latch unit is used for transmitting the data of the input end and latching the data under the control of a clock signal;

the second latch unit is used for latching the data at the output end and transmitting the data latched by the first latch unit in an inverted way under the control of a clock signal;

an output driving unit for inverting and outputting the data received from the second latch unit;

the first latch unit, the second latch unit and the output driving unit are sequentially connected in series between the input end and the output end;

the second latch unit outputs three states of high level, low level and high resistance through a single element under the control of a clock signal; the first latch unit adopts a delay unit.

In the hold-free dynamic D flip-flop, the clock signal terminal is connected to a clock buffer, and the clock buffer adopts an ultra-low threshold unit.

In the above-mentioned hold-free dynamic D flip-flop, the second latch unit is a tri-state inverter.

In the above-mentioned hold-free dynamic D flip-flop, the tri-state inverter further includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor, and the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are sequentially connected in series between the power supply and the ground.

In the above-mentioned hold-free dynamic D flip-flop, the first PMOS transistor and the second NMOS transistor perform switching control according to a clock signal, and clock signals of the first PMOS transistor and the second NMOS transistor are inverted.

In the hold-free dynamic D flip-flop, the second PMOS transistor and the first NMOS transistor are switched according to a clock signal, and the clock signals of the second PMOS transistor and the first NMOS transistor are inverted.

By using the hold-free dynamic D trigger, the area of a chip can be reduced by nearly 30 percent, so that the production cost of the chip is reduced, and the product competitiveness is increased. The back-end layout and wiring design process can be simplified, the design difficulty is reduced, the performance is improved, and the practicability is improved.

In order to better achieve the above object, the present invention further provides a data operation unit, which includes a control circuit, an operation circuit, and a plurality of hold-free dynamic D flip-flops connected in series and/or in parallel; wherein the plurality of keep-free dynamic D flip-flops are any one of the keep-free dynamic D flip-flops.

In order to better achieve the above object, the present invention further provides a chip, which employs any one of the above data operation units.

In order to better achieve the above object, the present invention further provides a computing board for a computing device, which employs any one of the above chips.

In order to better achieve the above object, the present invention further provides a computing device, which includes a power board, a control board, a connecting board, a heat sink, and a plurality of computing boards, wherein the control board is connected to the computing boards through the connecting board, the heat sink is disposed around the computing boards, and the power board is configured to provide power to the connecting board, the control board, the heat sink, and the computing boards are any one of the computing boards.

Preferably, the computing device is for operations to mine virtual digital currency.

The computing equipment can better save the chip area, reduce the production cost and further reduce the power consumption of the computing equipment.

The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.

Certain terms are used throughout the description and following claims to refer to particular components. As one of ordinary skill in the art will appreciate, manufacturers may refer to a component by different names. This specification and the claims that follow do not intend to distinguish between components that differ in name but not function.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. In addition, the term "connected" is intended to encompass any direct or indirect electrical connection. Indirect electrical connection means include connection by other means.

Drawings

FIG. 1 is a schematic diagram of a conventional positive feedback D flip-flop;

FIG. 2 is a diagram of a conventional dynamic D flip-flop;

FIG. 3A is a diagram illustrating a structure of a hold-free dynamic D flip-flop according to an embodiment of the present invention;

FIG. 3B is a schematic diagram of a keeper-free dynamic D flip-flop with clock control according to an embodiment of the present invention;

FIG. 4A is a circuit diagram of a hold-free dynamic D flip-flop according to an embodiment of the present invention;

FIG. 4B is a circuit diagram of a hold-free dynamic D flip-flop according to another embodiment of the present invention;

FIG. 5A is an equivalent circuit diagram of the hold-free dynamic D flip-flop writing data according to the present invention;

FIG. 5B is an equivalent circuit diagram of the data retention state of the retention-free dynamic D flip-flop according to the present invention;

FIG. 6 is a timing diagram of a hold-free dynamic D flip-flop according to the present invention;

FIG. 7 is a schematic diagram of a data operation unit according to the present invention;

FIG. 8 is a diagram of a chip according to the present invention;

FIG. 9 is a schematic view of a force computation plate according to the present invention;

FIG. 10 is a schematic diagram of a computing device of the present invention.

Wherein, the reference numbers:

100: parasitic capacitance 102: dynamic D flip-flop

106: positive feedback D flip-flop circuit

200, 204, 300, 304, 310, 314: analog switch

400, 400',500, 600: hold-free dynamic D flip-flop

401: the first latch unit 402: second latch unit

403: output drive unit 404: input terminal

405: output terminal 406: clock buffer

501, 601: transmission gates 502, 602: three-state inverter

202, 206, 302, 306, 308, 312, 503, 603: inverter with a capacitor having a capacitor element

506, 510, 511: PMOS transistors 507, 512, 513: NMOS transistor

508, 509, 514, 515: gate terminals 550, 551, 650, 651: node point

504, 604: input terminals 505, 605: output end

CLK, CLKN, CLKP, clock signal

Detailed Description

The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:

fig. 3A is a schematic diagram of a hold-free dynamic D flip-flop according to an embodiment of the present invention. Referring to fig. 3A, a hold-free dynamic D flip-flop 400 is composed of a first latch unit 401, a second latch unit 402, and an output driving unit 403. The first latch unit 401, the second latch unit 402, and the output driving unit 403 are sequentially connected in series between the input terminal 404 and the output terminal 405 of the hold-free dynamic D flip-flop 400.

FIG. 3B is a diagram of a keeper-free dynamic D flip-flop with clock control according to an embodiment of the present invention. Referring to fig. 3B, the retention-free dynamic D flip-flop 400' with clock control is composed of the retention-free dynamic D flip-flop 400 and a clock buffer 406. The clock signal CLK provides a clock control signal to the hold-free dynamic D flip-flop 400 after being buffered by the clock buffer 406.

The first latch unit 401 of the hold-free dynamic D flip-flop of the present invention is designed as a delay unit, and the clock buffer 406 is designed as a high-speed unit. The following is a detailed description.

The first embodiment is as follows:

fig. 4A is a circuit diagram of a hold-free dynamic D flip-flop according to an embodiment of the present invention.

As shown in fig. 4A, the first latch unit 401 of the hold-free dynamic D flip-flop 500 is a transmission gate 501, and the transmission gate 501 is connected in parallel with an NMOS transistor 507 by using a PMOS transistor 506, and forms an analog switch under the control of a clock signal. One end of the transmission gate 501 is connected to the input terminal 504 of the hold-free dynamic D flip-flop 500, the gate terminal 508 of the PMOS transistor 506 is controlled by the clock signal CLKP, and the gate terminal 509 of the NMOS transistor 507 is controlled by the clock signal CLKN having the opposite phase to CLKP. The clock signals CLKP and CLKN are provided through a clock buffer (not shown). When the CLKP is at a high level, the CLKN is at a low level, the PMOS transistor 506 and the NMOS transistor 507 of the transmission gate 501 are not turned on, the transmission gate 501 is turned off, the data of the input terminal 504 cannot be transmitted to the other end of the transmission gate 501, that is, the data at the first node 550 at the other end of the transmission gate 501 is latched and kept in the original state; when CLKP is at a low level, CLKN is at a high level, PMOS transistor 506 and NMOS transistor 507 of transmission gate 501 are turned on, transmission gate 501 is turned on, data at input terminal 504 is transmitted to the other end of transmission gate 501 through transmission gate 501, and data at first node 550 is rewritten to the same data as data at input terminal 504.

As shown in fig. 4A, the first latch unit 402 of the hold-free dynamic D flip-flop 500 is a tri-state inverter 502, and the tri-state inverter 502 includes PMOS transistors 510 and 511 and NMOS transistors 512 and 513. The gates of PMOS transistor 511 and NMOS transistor 512 are connected together to form the input of tri-state inverter 502. The source of the PMOS transistor 510 is connected to the power supply VDD, and the source of the NMOS transistor 513 is connected to ground GND. The drains of PMOS transistor 511 and NMOS transistor 512 are connected together to form the output of tri-state inverter 502. The source of PMOS transistor 511 is connected to the drain of PMOS transistor 510, and the source of NMOS transistor 512 is connected to the drain of NMOS transistor 513.

The gate terminal 514 of PMOS transistor 510 is controlled by clock signal CLKN and the gate terminal 515 of NMOS transistor 513 is controlled by clock signal CLKP as the clock control terminal of tri-state inverter 502.

When CLKP is low, CLKN is high, both PMOS transistor 510 and NMOS transistor 513 are in a non-conducting state, tristate inverter 502 is in a high-impedance state, data at first node 550 cannot pass through tristate inverter 502, data at second node 551 is latched, and the original state is maintained, which plays a role of data registration.

When CLKP is high, CLKN is low, PMOS transistor 510 and NMOS transistor 513 are both in a conducting state, and tristate inverter 502 acts to invert the data at its input, i.e., invert the data at first node 550 and output it to second node 551, rewriting the data at second node 551.

As shown in fig. 4A, wherein the output driving unit is an inverter 503, the data received from the tri-state inverter 502 is inverted again to form data of the same phase as the data of the input terminal 504 of the dynamic D flip-flop, and the data is output through the output terminal 505. Meanwhile, the output driving unit can also improve the driving capability of data.

Example two:

as shown in fig. 4B, the first latch unit 401 of the hold-free dynamic D flip-flop 600 is a transmission gate 601, and the transmission gate 601 is connected in parallel with an NMOS transistor 607 by using a PMOS transistor 606 and constitutes an analog switch under the control of a clock signal. One end of the transmission gate 601 is connected to the input terminal 604 of the hold-free dynamic D flip-flop 600, the gate terminal 608 of the PMOS transistor 606 is controlled by the clock signal CLKP, and the gate terminal 609 of the NMOS transistor 607 is controlled by the clock signal CLKN having the opposite phase to CLKP. The clock signals CLKP and CLKN are provided through a clock buffer (not shown). When CLKP is at a high level, CLKN is at a low level, PMOS transistor 606 and NMOS transistor 607 of transmission gate 601 are not turned on, the transmission gate is closed, data at input terminal 604 cannot be transmitted to the other end of transmission gate 601, data at first node 650 is latched and kept in the original state; when CLKP is at a low level, CLKN is at a high level, PMOS transistor 606 and NMOS transistor 607 of transmission gate 601 are turned on, transmission gate 601 is turned on, data at input terminal 604 is output to the other terminal through transmission gate 601, and data at first node 650 is rewritten to the same data as data at input terminal 604.

As shown in fig. 4B, wherein the first latch unit 402 of the hold-free dynamic D flip-flop 600 is a tri-state inverter 602, the tri-state inverter 602 includes

PMOS transistors

610 and 611 and

NMOS transistors

612 and 613. The gates of PMOS transistor 610 and NMOS transistor 613 are connected together to form the input of tri-state inverter 602. The source of the PMOS transistor 610 is connected to the power supply VDD and the source of the NMOS transistor 613 is connected to ground GND. The drains of PMOS transistor 611 and NMOS transistor 612 are connected together to form the output of tri-state inverter 602. The source of the PMOS transistor 611 is connected to the drain of the PMOS transistor 610, and the source of the NMOS transistor 612 is connected to the drain of the NMOS transistor 613.

The gate terminal 614 of the PMOS transistor 611 is controlled by the clock signal CLKN, and the gate terminal 615 of the NMOS transistor 612 is controlled by the clock signal CLKP as the clock control terminal of the tri-state inverter 602.

When the CLKP is at a low level, the CLKN is at a high level, the PMOS transistor 611 and the NMOS transistor 612 are both in a non-conducting state, the tristate inverter 602 is in a high-impedance state, the data at the first node 650 cannot pass through the tristate inverter 602, and the data at the second node 651 is latched, and the original state is maintained, thereby playing a role of data registration.

When CLKP is at a high level, CLKN is at a low level, PMOS transistor 611 and NMOS transistor 612 are both in a conducting state, and tristate inverter 602 acts to invert the data at its input, i.e., invert the data at first node 650 and output it to second node 651, rewriting the data at second node 651.

As shown in fig. 4B, in which the output driving unit is an inverter 603, the data received from the tri-state inverter 602 is inverted again to form data of the same phase as the data of the input terminal 604 of the dynamic D flip-flop, and the data is output through the output terminal 605. Meanwhile, the output driving unit can improve the driving capability of data.

The operation principle of the hold-free dynamic D flip-flop of the present invention is specifically described below.

Fig. 5A is an equivalent circuit diagram of the hold-free dynamic D flip-flop writing data according to the present invention, and fig. 5B is an equivalent circuit diagram of the hold-free dynamic D flip-flop in a data hold state according to the present invention.

As shown in fig. 4A, 4B and 5A, when CLKP is at high level and CLKN is at low level, the clocked transistors of the tri-state inverters 502 and 602 are turned on, and the data transmitted from the transmission gates 501 and 601 is written into the parasitic capacitor 100. When the input data is "0", the

PMOS transistors

510, 511, 610, 611 of the tri-state inverters 502, 602 are all in the on state, forming a pull-up path, charging the parasitic capacitor 100, the second nodes 551, 651 becoming high level, and the data becoming "1"; when the input data is "1", the

NMOS transistors

512, 513, 612, 613 of the tri-state inverters 502, 602 are all turned on, and a pull-down path is formed, so that the parasitic capacitor 100 is discharged, the second nodes 551, 651 become low, and the data becomes "0".

As shown in fig. 5B, after the parasitic capacitor 100 is charged, if the tri-state inverters 502, 602 are in a high impedance state under the control of the clock signal, the parasitic capacitor 100 is not further charged and the data at the second nodes 551, 651 is in a hold state. On the other hand, due to the leakage current of the

NMOS transistors

512, 513, 612, 613, the charges on the parasitic capacitor 100 will gradually leak, the high level on the second nodes 551, 651 will be inverted to the low level after a certain period of time, and the data stored in the parasitic capacitor 100 will change from "1" to "0", which eventually results in data error.

Assuming that the charge generated on the parasitic capacitor 100 is Q, the capacitance of the parasitic capacitor 100 is C, and the voltage across the plates of the parasitic capacitor is V, the voltage across the plates of the parasitic capacitor is V

Q＝C*V。

If the leakage current is I_leakageWhen the leakage time t is equal to

t＝Q/I_leakage＝C*V/I_leakage。

Under the existing production process, the data stored by the parasitic capacitor 100 can be kept about 5 ns. That is, if the data stored in the parasitic capacitance is periodically updated during the data holding period, a data error does not occur. The working frequency of the existing computing equipment is generally more than 500MHz, and far exceeds the required data updating frequency, so that the dynamic D trigger provided by the invention can be applied to the computing equipment.

FIG. 6 is a timing diagram of a hold-free dynamic D flip-flop according to the present invention. As shown in fig. 6, when CLKP is at a low level and CLKN is at a high level, the first latch unit 401 is turned on, the data of the input terminal D passes through the first latch unit 401, the first latch unit 402 is turned off, and the output of the dynamic D flip-flop is kept in the original state. When the CLKP rising edge approaches, the CLKP jumps to a high level and the CLKN jumps to a low level, the first latch unit 401 is not turned on, the data input of the input terminal D is cut off, the first latch unit 402 is turned on, and the held data of the input terminal D is output through the output terminal Q. Therefore, the state change of the output end of the dynamic D trigger provided by the invention is generated when the rising edge of the clock signal CLKP comes, and the output state is kept unchanged when the CLKP is at a high level and the CLKN is at a low level.

As shown in fig. 6, the setup time (setup time) of the hold-free dynamic D flip-flop refers to the time that the data at the input of the data of the flip-flop must remain unchanged before the clock edge arrives; the setup time determines the maximum delay of the combinational logic between the flip-flops. The hold time (hold time) of a dynamic D flip-flop refers to the time that the data at its data input must remain unchanged after the arrival of a clock edge of the flip-flop; the hold time determines the minimum delay of the combinational logic between the flip-flops.

In the hold-free dynamic D flip-flop 400, the increase of the hold time will cause the data reading speed of the hold-free dynamic D flip-flop 400 to become slow, and in a serious case, a data reading error will be generated.

For this reason, it is necessary to increase the data transmission time of the hold-free dynamic D flip-flop. The first latch unit 401 of the hold-free dynamic D trigger, namely the transmission gates 501 and 601, adopts a delay unit design, reduces the speed by adopting a high-threshold device, reduces the leakage and the transmission speed by adopting a small size, and reduces the transmission speed by utilizing layout parasitic resistance and capacitance. Thereby reducing the hold time of the dynamic D flip-flop.

In addition, the clock buffer 406 in the invention adopts a high-speed unit design, and comprises at least one cascaded clock buffer unit, and the driving capability is enhanced by using a low-threshold voltage device and increasing the size of the device; and a scheme of reasonably distributing clock delay is adopted, so that the driving balance among loads is balanced, and the overall driving speed is increased. Thereby reducing the hold time of the dynamic D flip-flop.

The first latch unit 401 with a delay unit design and the clock buffer 406 with a high-speed unit design can be applied to the hold-free dynamic D flip-flop circuit of the present invention alone or simultaneously.

The invention also provides a data operation unit, and fig. 7 is a schematic diagram of the data operation unit. As shown in fig. 7, the data operation unit 700 includes a control circuit 701, an operation circuit 702, and a plurality of hold-free dynamic D flip-flops 500 and 600. The control circuit 701 refreshes the data in the hold-free dynamic D flip-flops 500 and 600, reads the data from the hold-free dynamic D flip-flops 500 and 600, and the arithmetic circuit 702 performs arithmetic on the read data, and the control circuit 701 outputs the arithmetic result.

The invention also provides a chip, and fig. 8 is a schematic diagram of the chip of the invention. As shown in fig. 8, the chip 800 includes a control unit 801, and one or more data operation units 700. The control unit 801 inputs data to the data operation unit 700 and processes the data output by the data operation unit 700.

The invention also provides a force calculating board, and fig. 9 is a schematic diagram of the force calculating board. As shown in fig. 9, each computing board 900 includes one or more chips 800 for performing hash operations on the work data sent from the mine.

The invention also provides a computing device, which is preferably used for operations of mining virtual digital currency, and of course, the computing device can be used for any other massive operations, and fig. 10 is a schematic diagram of the computing device of the invention. As shown in fig. 10, each computing device 1000 includes a connection board 1001, a control board 1002, a heat sink 1003, a power board 1004, and one or more computing boards 900. The control board 1002 is connected to the force calculation board 900 through a connection board 1001, and the heat sink 1003 is disposed around the force calculation board 900. The power board 1004 is used to provide power to the connection board 1001, the control board 1002, the heat sink 1003, and the computing board 900.

It should be noted that in the description of the present invention, the terms "lateral", "longitudinal", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

While embodiments of the invention have been described above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the invention pertains, and further modifications may readily be made by those skilled in the art, it being understood that the invention is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.

In other words, the present invention may have other embodiments, and those skilled in the art can make various corresponding changes and modifications according to the present invention without departing from the spirit and the essence of the present invention, and these corresponding changes and modifications should fall within the protection scope of the appended claims.

Claims

1. A hold-free dynamic D flip-flop, comprising:

an input terminal, an output terminal and a clock signal terminal;

2. The hold-free dynamic D flip-flop of claim 1, wherein: the clock signal end is connected with a clock buffer, and the clock buffer adopts an ultra-low threshold unit.

3. The hold-free dynamic D flip-flop of claim 2, wherein: the second latch unit is a tri-state inverter.

4. The hold-free dynamic D flip-flop of claim 3, wherein: the tri-state inverter further comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are sequentially connected in series between a power supply and the ground.

5. The hold-free dynamic D flip-flop of claim 4, wherein: and the first PMOS transistor and the second NMOS transistor are subjected to switch control according to a clock signal, and the clock signals of the first PMOS transistor and the second NMOS transistor are in opposite phases.

6. The hold-free dynamic D flip-flop of claim 4, wherein: and the second PMOS transistor and the first NMOS transistor are subjected to switch control according to clock signals, and the clock signals of the second PMOS transistor and the first NMOS transistor are in reverse phase.

7. A data arithmetic unit comprises a control circuit, an arithmetic circuit and a plurality of hold-free dynamic D triggers which are connected in an interconnecting way, wherein the hold-free dynamic D triggers are connected in series and/or in parallel; the method is characterized in that: the plurality of keep-free dynamic D flip-flops are the keep-free dynamic D flip-flops of any one of claims 1-6.

8. A chip comprising a data arithmetic unit as claimed in any one of claim 7.

9. An algorithm board for a computing device comprising a plurality of said chips of any one of claim 8.

10. A computing device comprises a power panel, a control panel, a connecting plate, a radiator and a plurality of computing plates, wherein the control panel is connected with the computing plates through the connecting plate, the radiator is arranged around the computing plates, the power panel is used for providing power for the connecting plate, the control panel, the radiator and the computing plates, and the computing plates are characterized in that: the force calculation board is any one of the force calculation boards described in claim 9.

11. The computing device of claim 10, wherein: the computing device is for mining operations of virtual digital currency.