EA202092706A1 - D-TRIGGER WITH DYNAMIC CONTROL, DATA PROCESSING UNIT, MICROCIRCUIT, HASHING BOARD AND COMPUTER - Google Patents

D-TRIGGER WITH DYNAMIC CONTROL, DATA PROCESSING UNIT, MICROCIRCUIT, HASHING BOARD AND COMPUTER

Info

Publication number
EA202092706A1
EA202092706A1 EA202092706A EA202092706A EA202092706A1 EA 202092706 A1 EA202092706 A1 EA 202092706A1 EA 202092706 A EA202092706 A EA 202092706A EA 202092706 A EA202092706 A EA 202092706A EA 202092706 A1 EA202092706 A1 EA 202092706A1
Authority
EA
Eurasian Patent Office
Prior art keywords
latch unit
output
microcircuit
hashing
processing unit
Prior art date
Application number
EA202092706A
Other languages
Russian (ru)
Inventor
Цзеяо Лю
Нанэн Чжан
Цзинцзе Ву
Шэнхоу Ма
Original Assignee
Канаан Креатив Ко., Лтд.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Канаан Креатив Ко., Лтд. filed Critical Канаан Креатив Ко., Лтд.
Priority claimed from PCT/CN2019/085893 external-priority patent/WO2020001167A1/en
Publication of EA202092706A1 publication Critical patent/EA202092706A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356017—Bistable circuits using additional transistors in the input circuit
    • H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration

Abstract

В настоящем изобретении предложен D-триггер с динамическим управлением, а также блок обработки данных, микросхема, платы хэширования и вычислительное устройство с его использованием. D-триггер с динамическим управлением содержит: входной вывод, выходной вывод и по меньшей мере один вывод сигнала синхронизации; блок первой защелки для передачи данных с входного вывода и сохранения данных под управлением сигнала синхронизации; блок второй защелки для сохранения данных для выходного вывода и передачи с инвертированием данных, хранящихся в блоке первой защелки, под управлением сигнала синхронизации; и выходной буферный блок для инвертирования и вывода данных, полученных с блока второй защелки; причем выход блока второй защелки может принимать состояния с высоким уровнем, низким уровнем и высоким выходным импедансом с помощью единственного элемента под управлением сигналом синхронизации. Следовательно, настоящее изобретение может эффективно уменьшить занимаемую на микросхеме площадь, потребляемую мощность и задержку срабатывания логики.The present invention provides a dynamically controlled D-flip-flop, as well as a data processing unit, a microcircuit, hashing boards and a computing device using it. D-flip-flop with dynamic control contains: an input terminal, an output terminal and at least one terminal of the synchronization signal; a first latch unit for transmitting data from an input terminal and storing data under the control of a synchronization signal; a second latch unit for storing data for output and inverting data stored in the first latch unit under the control of a synchronization signal; and an output buffer unit for inverting and outputting data obtained from the second latch unit; wherein the output of the second latch unit can take on high-level, low-level, and high-output impedance states with a single element controlled by the clock signal. Therefore, the present invention can effectively reduce the chip footprint, power consumption, and logic lag.

EA202092706A 2018-06-25 2019-05-07 D-TRIGGER WITH DYNAMIC CONTROL, DATA PROCESSING UNIT, MICROCIRCUIT, HASHING BOARD AND COMPUTER EA202092706A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810667264.0A CN110635784A (en) 2018-06-25 2018-06-25 Hold-free dynamic D flip-flop
PCT/CN2019/085893 WO2020001167A1 (en) 2018-06-25 2019-05-07 Dynamic d flip-flop, data operation unit, chip, hash board and computing device

Publications (1)

Publication Number Publication Date
EA202092706A1 true EA202092706A1 (en) 2021-03-31

Family

ID=68968270

Family Applications (1)

Application Number Title Priority Date Filing Date
EA202092706A EA202092706A1 (en) 2018-06-25 2019-05-07 D-TRIGGER WITH DYNAMIC CONTROL, DATA PROCESSING UNIT, MICROCIRCUIT, HASHING BOARD AND COMPUTER

Country Status (2)

Country Link
CN (1) CN110635784A (en)
EA (1) EA202092706A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111600577A (en) * 2020-06-22 2020-08-28 深圳比特微电子科技有限公司 Inverted output dynamic D flip-flop
CN113437961B (en) * 2021-08-26 2021-12-07 成都爱旗科技有限公司 Latch and odd frequency division circuit
CN116760403A (en) * 2023-06-26 2023-09-15 上海奎芯集成电路设计有限公司 High-speed D trigger circuit and high-speed D trigger chip

Also Published As

Publication number Publication date
CN110635784A (en) 2019-12-31

Similar Documents

Publication Publication Date Title
EA202092706A1 (en) D-TRIGGER WITH DYNAMIC CONTROL, DATA PROCESSING UNIT, MICROCIRCUIT, HASHING BOARD AND COMPUTER
CN107911104B (en) Clock gating circuit
KR20130125036A (en) System on chip (soc), method of operating the soc, and system having the soc
US20150358004A1 (en) D-type flip-flop and clock generating circuit
US9971717B2 (en) Bus interface circuit
WO2016114892A3 (en) Clock-gating cell with low area, low power, and low setup time
US20170294903A1 (en) Dynamic clock switching method and apparatus as well as computer readable medium
DE602005001266D1 (en) MEMORY BLOCK WITH MULTI-FUNCTION STROBE CONNECTIONS
SG10201805776PA (en) Sequential circuit having increased negative setup time
KR102432457B1 (en) Clock Generation Circuit having De-skew function and Semiconductor Integrated Circuit Device including the same
US10177901B2 (en) Serializer, and semiconductor apparatus and system including the same
US9385696B1 (en) Generating a pulse clock signal based on a first clock signal and a second clock signal
US20160182031A1 (en) Semiconductor apparatus
SG10201804069TA (en) Nonvolatile memory including duty correction circuit and storage device including the nonvolatile memory
KR20130130478A (en) Input buffer
KR101041278B1 (en) Apparatus of outputting a complementary signal using bootstrapping technology
US9450587B2 (en) Test circuit and test method of semiconductor apparatus
US10140058B2 (en) Memory controller and memory module
US9590596B1 (en) Receiving circuit, semiconductor apparatus and system using the same
CN103873031A (en) Non-clock trigger register
KR20190051314A (en) Electronic circuit for ouputting post emphasis signal
US9292295B2 (en) Voltage droop reduction by delayed back-propagation of pipeline ready signal
TWI505595B (en) Power integrated device and power control method thereof
KR20170049839A (en) Semiconductor system and electronic device capable of capturing high speed signal
KR20180013451A (en) Semiconductor Apparatus