SG10201805776PA - Sequential circuit having increased negative setup time - Google Patents

Sequential circuit having increased negative setup time

Info

Publication number
SG10201805776PA
SG10201805776PA SG10201805776PA SG10201805776PA SG10201805776PA SG 10201805776P A SG10201805776P A SG 10201805776PA SG 10201805776P A SG10201805776P A SG 10201805776PA SG 10201805776P A SG10201805776P A SG 10201805776PA SG 10201805776P A SG10201805776P A SG 10201805776PA
Authority
SG
Singapore
Prior art keywords
signal
circuit
input
clock signal
setup time
Prior art date
Application number
SG10201805776PA
Inventor
Hwang Hyun-Chul
Ryu Jong-Kyu
Kim Min-Su
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201805776PA publication Critical patent/SG10201805776PA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse

Abstract

A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit. FIG. 1
SG10201805776PA 2017-09-06 2018-07-04 Sequential circuit having increased negative setup time SG10201805776PA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020170114032A KR102369635B1 (en) 2017-09-06 2017-09-06 Sequential circuit having increased negative setup time

Publications (1)

Publication Number Publication Date
SG10201805776PA true SG10201805776PA (en) 2019-04-29

Family

ID=65518270

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201805776PA SG10201805776PA (en) 2017-09-06 2018-07-04 Sequential circuit having increased negative setup time

Country Status (4)

Country Link
US (1) US10938383B2 (en)
KR (1) KR102369635B1 (en)
CN (1) CN109462394B (en)
SG (1) SG10201805776PA (en)

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US10847211B2 (en) * 2018-04-18 2020-11-24 Arm Limited Latch circuitry for memory applications
KR20210109354A (en) * 2020-02-27 2021-09-06 삼성전자주식회사 High speed flipflop circuit
US11171659B1 (en) * 2021-01-05 2021-11-09 Micron Technology, Inc. Techniques for reliable clock speed change and associated circuits and methods
CN114567301B (en) * 2022-04-28 2022-08-23 深圳比特微电子科技有限公司 Hybrid phase D flip-flop with multiplexer function
US11916556B1 (en) * 2022-08-26 2024-02-27 Advanced Micro Devices, Inc. Method of operation for a data latch circuit

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US5719878A (en) * 1995-12-04 1998-02-17 Motorola Inc. Scannable storage cell and method of operation
JP2000236062A (en) 1999-02-16 2000-08-29 Kawasaki Steel Corp Semiconductor integrated circuit
WO2001048493A2 (en) 1999-12-24 2001-07-05 Koninklijke Philips Electronics N.V. Low power scan flipflop
US6438023B1 (en) * 2000-08-31 2002-08-20 Micron Technology, Inc. Double-edged clocked storage device and method
US6466049B1 (en) 2000-09-14 2002-10-15 Xilinx, Inc. Clock enable control circuit for flip flops
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US6686775B2 (en) * 2002-04-22 2004-02-03 Broadcom Corp Dynamic scan circuitry for B-phase
US6956405B2 (en) * 2002-07-09 2005-10-18 Ip-First, Llc Teacher-pupil flip-flop
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Also Published As

Publication number Publication date
KR20190027225A (en) 2019-03-14
US10938383B2 (en) 2021-03-02
US20190074825A1 (en) 2019-03-07
CN109462394A (en) 2019-03-12
CN109462394B (en) 2023-10-20
KR102369635B1 (en) 2022-03-03

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