SG10201905139XA - Input/output circuit, memory device having the same, and operating method thereof - Google Patents

Input/output circuit, memory device having the same, and operating method thereof

Info

Publication number
SG10201905139XA
SG10201905139XA SG10201905139XA SG10201905139XA SG10201905139XA SG 10201905139X A SG10201905139X A SG 10201905139XA SG 10201905139X A SG10201905139X A SG 10201905139XA SG 10201905139X A SG10201905139X A SG 10201905139XA SG 10201905139X A SG10201905139X A SG 10201905139XA
Authority
SG
Singapore
Prior art keywords
input
same
memory device
output circuit
operating method
Prior art date
Application number
SG10201905139XA
Inventor
Ha Hwang Jin
Original Assignee
Sk Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sk Hynix Inc filed Critical Sk Hynix Inc
Publication of SG10201905139XA publication Critical patent/SG10201905139XA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
SG10201905139XA 2018-08-07 2019-06-06 Input/output circuit, memory device having the same, and operating method thereof SG10201905139XA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020180092031A KR20200016667A (en) 2018-08-07 2018-08-07 Input-output circuit, memory device having the same and operating method thereof

Publications (1)

Publication Number Publication Date
SG10201905139XA true SG10201905139XA (en) 2020-03-30

Family

ID=69406358

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201905139XA SG10201905139XA (en) 2018-08-07 2019-06-06 Input/output circuit, memory device having the same, and operating method thereof

Country Status (4)

Country Link
US (1) US10991401B2 (en)
KR (2) KR20200016667A (en)
CN (1) CN110827871B (en)
SG (1) SG10201905139XA (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022010951A (en) * 2020-06-29 2022-01-17 キオクシア株式会社 Semiconductor storage device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100597633B1 (en) * 2004-01-06 2006-07-05 삼성전자주식회사 Impedance controller and method for control therefore
KR100667594B1 (en) 2004-10-19 2007-01-11 삼성전자주식회사 Pre-emphasis Output Buffer and Semiconductor Memory Device for Driving Output Pin connected Pull-Up Termination, Method for driving Output
JP3985002B2 (en) * 2005-07-15 2007-10-03 三菱電機株式会社 In-vehicle electronic control unit
JP4398945B2 (en) * 2006-02-23 2010-01-13 シャープ株式会社 Nonvolatile semiconductor memory device and data rewriting method
KR100808598B1 (en) 2006-12-27 2008-03-03 주식회사 하이닉스반도체 Data output driver
KR101035407B1 (en) * 2009-06-04 2011-05-20 주식회사 하이닉스반도체 Semiconductor device
WO2011121970A1 (en) * 2010-03-30 2011-10-06 パナソニック株式会社 Forming method for variable resistance non-volatile memory element and variable resistance non-volatile memory device
CN102253287A (en) * 2011-05-27 2011-11-23 青岛大学 LABview-based method for measuring temperature-resistivity
CN103339681B (en) * 2011-12-13 2015-09-23 松下电器产业株式会社 The driving method of electro-resistance element and Nonvolatile memory devices
KR102529968B1 (en) * 2016-05-11 2023-05-08 삼성전자주식회사 Impedance calibration circuit of semiconductor memory device, semiconductor memory device and method of operating the same
KR101870840B1 (en) * 2016-11-02 2018-06-26 삼성전자주식회사 Output buffer circuit and memory device comprising that

Also Published As

Publication number Publication date
CN110827871B (en) 2024-01-26
KR20200016667A (en) 2020-02-17
KR20240032804A (en) 2024-03-12
US20200051600A1 (en) 2020-02-13
US10991401B2 (en) 2021-04-27
CN110827871A (en) 2020-02-21

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