JP2022010951A - Semiconductor storage device - Google Patents

Abstract

To provide a semiconductor storage device that operates with high speed.SOLUTION: A semiconductor storage device includes a memory cell array and a peripheral circuit that is connected to the memory cell array and inputs/outputs user data in response to input of a command set including command data and address data. The peripheral circuit includes a command register, an address register, and a queue register. The command register includes an n-bit first register sequence capable of holding n-bit data constituting the command data. The address register includes an n-bit second register sequence capable of holding n-bit data constituting the address data. The queue register includes a plurality of third register sequences capable of holding at least n+1 bit data, the third register sequence can hold n-bit data constituting the command data, and n-bit data constituting the address data.SELECTED DRAWING: Figure 7

Description

The present embodiment relates to a semiconductor storage device.

A semiconductor storage device including a memory cell array including a plurality of memory cells and a peripheral circuit connected to the memory cell array and output user data in response to input of a command set including command data and address data is known. ..

JP-A-2015-176309A

Provided is a semiconductor storage device that operates at high speed.

The semiconductor storage device according to one embodiment is connected to a memory cell array including a plurality of memory cells and a peripheral circuit that is connected to the memory cell array and inputs / outputs user data in response to input of a command set including command data and address data. And. The peripheral circuit includes a command register, an address register, and a queue register. The command register includes an n-bit first register sequence capable of holding n (n is a natural number) bit of data constituting the command data. The address register includes an n-bit second register sequence capable of holding n-bit data constituting the address data. The queue register includes a plurality of third register columns that can hold at least n + 1-bit data, and the third register column can hold n-bit data that constitutes command data and n-bit data that constitutes address data. Is.

The semiconductor storage device according to one embodiment is connected to a memory cell array including a plurality of memory cells and a peripheral circuit that is connected to the memory cell array and inputs / outputs user data in response to input of a command set including command data and address data. And. The peripheral circuit includes a queue register that can hold the input command set, and the command held in the queue register in response to the input of the first command data without erasing the command set held in the queue register. It is configured to be able to perform internal operations corresponding to the set.

The semiconductor storage device according to one embodiment is connected to a memory cell array including a plurality of memory cells and a peripheral circuit that is connected to the memory cell array and inputs / outputs user data in response to input of a command set including command data and address data. And. The peripheral circuit includes a queue register capable of holding a command set input during the busy period during the execution of the first internal operation, and corresponds to the command set held in the queue register after the execution of the first internal operation. The second internal operation is configured to be automatically executable.

It is a schematic block diagram which shows the structure of the memory system 10 which concerns on 1st Embodiment. It is a schematic side view which shows the configuration example of the memory system 10. It is a schematic plan view which shows the same configuration example. It is a schematic block diagram which shows the structure of the memory die MD which concerns on 1st Embodiment. It is a schematic circuit diagram which shows the structure of a part of the memory die MD. It is a schematic block diagram which shows the structure of a part of the memory die MD. It is a schematic block diagram which shows the structure of a part of the memory die MD. It is a timing chart for demonstrating the operation of the memory die MD. It is a timing chart for demonstrating the operation of the memory die MD. It is a timing chart for demonstrating the operation of the memory die MD. It is a timing chart for demonstrating the operation of the memory die MD. It is a timing chart for demonstrating the operation of the memory die MD. It is a timing chart for demonstrating the operation of the memory die MD. It is a timing chart for demonstrating the operation of the memory die MD. It is a timing chart for demonstrating the operation of the memory die which concerns on 2nd Embodiment. It is a timing chart for demonstrating the operation of the memory die which concerns on 3rd Embodiment. It is a timing chart for demonstrating the operation of the memory die which concerns on 3rd Embodiment. It is a timing chart for demonstrating the operation of the memory die which concerns on 4th Embodiment. It is a schematic block diagram which shows the structure of the memory die MD ′ which concerns on 5th Embodiment. It is a timing chart for demonstrating the operation of the memory die MD ′ which concerns on 5th Embodiment. It is a schematic block diagram which shows the structure of the memory die MD ″ which concerns on 6th Embodiment. 6 is a timing chart for explaining the operation of the memory die MD ″ according to the sixth embodiment. It is a schematic block diagram which shows the structure of a part of the memory die which concerns on 7th Embodiment. It is a timing chart for demonstrating the operation of the memory die which concerns on 7th Embodiment. It is a timing chart for demonstrating the operation of the memory die which concerns on 7th Embodiment. It is a schematic block diagram which shows the structure of a part of the memory die which concerns on 8th Embodiment. It is a timing chart for demonstrating the operation of the memory die which concerns on 8th Embodiment.

Next, the semiconductor storage device according to the embodiment will be described in detail with reference to the drawings. The following embodiments are merely examples, and are not intended to limit the present invention.

Further, when the term "semiconductor storage device" is used in the present specification, it may mean a memory die (memory chip) or a memory system including a controller die such as a memory card or SSD. .. Further, it may mean a configuration including a host computer such as a smart phone, a tablet terminal, and a personal computer.

Further, in the present specification, when the first configuration is said to be "electrically connected" to the second configuration, the first configuration may be directly connected to the second configuration. The first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, or the like. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor, even if the second transistor is in the OFF state.

Further, in the present specification, when the first configuration is said to be "connected between" the second configuration and the third configuration, the first configuration, the second configuration, and the third configuration are used. It may mean that they are connected in series and that the second configuration is connected to the third configuration via the first configuration.

Further, in the present specification, when it is said that a circuit or the like "conducts" two wirings or the like, for example, this circuit or the like includes a transistor or the like, and the transistor or the like includes a current between the two wirings or the like. It is provided in the path and may mean that this transistor or the like is turned on.

[First Embodiment]
[Memory system 10]
FIG. 1 is a schematic block diagram showing the configuration of the memory system 10 according to the first embodiment.

The memory system 10 reads, writes, erases, and the like user data according to the signal transmitted from the host computer 20. The memory system 10 is, for example, a system capable of storing a memory card, SSD or other user data. The memory system 10 includes a plurality of memory die (memory chip) MDs for storing user data, the plurality of memory die MDs, and a controller die (controller chip) CD connected to the host computer 20. The controller die CD includes, for example, a processor, RAM, and the like, and performs processing such as conversion between a logical address and a physical address, bit error detection / correction, garbage collection (compacting), and wear leveling.

FIG. 2 is a schematic side view showing a configuration example of the memory system 10 according to the present embodiment. FIG. 3 is a schematic plan view showing the same configuration example. For convenience of explanation, some configurations are omitted in FIGS. 2 and 3.

As shown in FIG. 2, the memory system 10 according to the present embodiment includes a mounting board MSB, a plurality of memory die MDs stacked on the mounting board MSB, and a controller die CD stacked on the memory die MD. A pad electrode P is provided in the region of the end portion in the Y direction of the upper surface of the mounting substrate MSB, and a part of the other regions is adhered to the lower surface of the memory die MD via an adhesive or the like. A pad electrode P is provided in the region of the end portion of the upper surface of the memory die MD in the Y direction, and the other region is adhered to the lower surface of another memory die MD or controller die CD via an adhesive or the like. A pad electrode P is provided in the region of the end portion in the Y direction on the upper surface of the controller die CD.

As shown in FIG. 3, the mounting board MSB, the plurality of memory die MDs, and the controller die CDs each include a plurality of pad electrodes P arranged in the X direction. The mounting board MSB, the plurality of memory die MDs, and the plurality of pad electrodes P provided on the controller die CD are each connected to each other via a bonding wire B.

The configurations shown in FIGS. 2 and 3 are merely examples, and the specific configurations can be adjusted as appropriate. For example, in the example shown in FIGS. 2 and 3, controller die CDs are stacked on a plurality of memory die MDs, and these configurations are connected by bonding wires B. In such a configuration, a plurality of memory die MDs and controller die CDs are included in one package. However, the controller die CD may be included in a package different from the memory die MD. Further, the plurality of memory die MDs and controller die CDs may be connected to each other via through electrodes or the like instead of the bonding wire B.

[Configuration of memory die MD]
FIG. 4 is a schematic block diagram showing the configuration of the memory die MD according to the first embodiment. FIG. 5 is a schematic circuit diagram showing a partial configuration of the memory die MD. 6 and 7 are schematic block diagrams showing a partial configuration of the memory die MD.

Note that FIG. 4 illustrates a plurality of control terminals and the like. These plurality of control terminals are represented as a control terminal corresponding to a high active signal (positive logic signal), a control terminal corresponding to a low active signal (negative logic signal), and a high active signal. And there are cases where it is expressed as a control terminal corresponding to both a low active signal. In FIG. 4, the code of the control terminal corresponding to the low active signal includes an overline (overline). In the present specification, the code of the control terminal corresponding to the low active signal includes a slash (“/”). The description in FIG. 4 is an example, and the specific embodiment can be adjusted as appropriate. For example, a part or all of the high active signal may be regarded as a low active signal, or a part or all of the low active signal may be regarded as a high active signal.

As shown in FIG. 4, the memory die MD includes a memory cell array MCA for storing data and a peripheral circuit PC connected to the memory cell array MCA. The peripheral circuit PC includes a voltage generation circuit VG, a row decoder RD, a sense amplifier module SAM, a cache memory CM, and a sequencer SQC. Further, the peripheral circuit PC includes an input / output control circuit I / O and a logic circuit CTR. The peripheral circuit PC includes an address register ADR, a command register CMR, a queue register QR connected to the address register ADR and the command register CMR, and a queue register control circuit QRC (FIG. 7) that controls the queue register QR. To prepare for.

[Configuration of memory cell array MCA]
As shown in FIG. 5, the memory cell array MCA includes a plurality of memory blocks BLK. Each of these plurality of memory blocks BLK includes a plurality of string units SU. Each of these plurality of string units SU includes a plurality of memory string MSs. One end of each of these plurality of memory string MSs is connected to a peripheral circuit PC via a bit line BL. Further, the other ends of the plurality of memory string MSs are each connected to the peripheral circuit PC via a common source line SL.

The memory string MS includes a drain side selection transistor STD, a plurality of memory cells MC (memory transistors), a source side selection transistor STS, and a source side selection transistor STSb connected in series between the bit line BL and the source line SL. Be prepared. Hereinafter, the drain side selection transistor STD, the source side selection transistor STS, and the source side selection transistor STSb may be simply referred to as selection transistors (STD, STS, STSb).

The memory cell MC is a field-effect transistor having a semiconductor layer that functions as a channel region, a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge storage film. The memory cell MC stores one-bit or a plurality of bits of data. A word line WL is connected to each of the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS. Each of these word line WLs is commonly connected to all memory string MSs in one memory block BLK.

The selection transistor (STD, STS, STSb) is a field effect transistor including a semiconductor layer, a gate insulating film, and a gate electrode that function as a channel region. Selected gate wires (SGD, SGS, SGSb) are connected to the gate electrodes of the selective transistors (STD, STS, STSb), respectively. The drain side selection gate line SGD is provided corresponding to the string unit SU and is commonly connected to all the memory string MSs in one string unit SU. The source-side selection gate line SGS is commonly connected to all memory string MSs in the plurality of string units SU. The source-side selection gate line SGSb is commonly connected to all the memory string MSs in the plurality of string units SU.

[Voltage generation circuit VG configuration]
The voltage generation circuit VG (FIG. 4) is connected to a plurality of voltage supply lines 31 as shown in FIG. 5, for example. The voltage generation circuit VG includes, for example, a step-down circuit such as a regulator and a booster circuit such as a charge pump circuit 32. These step-down circuit and step-up circuit are connected to a voltage supply line to which a power supply voltage _VCC and a ground voltage _VSS (FIG. 4) are supplied, respectively. These voltage supply lines are connected to, for example, the pad electrodes P described with reference to FIGS. 2 and 3. The voltage generation circuit VG, for example, according to a control signal from the sequencer SQC, performs a bit line BL, a source line SL, a word line WL, and a selection gate line (SGD, SGS,) in a read operation, a write operation, and an erase operation for the memory cell array MCA. A plurality of operating voltages applied to SGSb) are generated and output to a plurality of voltage supply lines 31 at the same time. The operating voltage output from the voltage supply line 31 is appropriately adjusted according to the control signal from the sequencer SQC.

[Structure of Row Decoder RD]
As shown in FIG. 5, for example, the row decoder RD (FIG. 4) has an address decoder 22 that decodes the address data D _ADD and a block selection circuit that transfers an operating voltage to the memory cell array MCA according to the output signal of the address decoder 22. 23 and a voltage selection circuit 24 are provided.

The address decoder 22 includes a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 33. For example, the address decoder 22 refers to the row address RA of the address register ADR (FIG. 4) sequentially according to the control signal from the sequencer SQC, decodes the row address RA, and determines a predetermined block selection transistor corresponding to the row address RA. The 35 and the voltage selection transistor 37 are turned on, and the other block selection transistors 35 and the voltage selection transistor 37 are turned off. For example, the voltage of the predetermined block selection line BLKSEL and the voltage selection line 33 is set to the “H” state, and the other voltages are set to the “L” state. When a P-channel type transistor is used instead of an N-channel type transistor, a reverse voltage is applied to these wirings.

In the illustrated example, the address decoder 22 is provided with one block selection line BLKSEL for each memory block BLK. However, this configuration can be changed as appropriate. For example, one block selection line BLKSEL may be provided for each of two or more memory blocks BLK.

The block selection circuit 23 includes a plurality of block selection units 34 corresponding to the memory block BLK. Each of the plurality of block selection units 34 includes a plurality of block selection transistors 35 corresponding to the word line WL and the selection gate line (SGD, SGS, SGSb). The block selection transistor 35 is, for example, a field effect type withstand voltage transistor. The drain electrode of the block selection transistor 35 is electrically connected to the corresponding word line WL or selection gate line (SGD, SGS, SGSb), respectively. The source electrodes are electrically connected to the voltage supply line 31 via the wiring CG and the voltage selection circuit 24, respectively. The gate electrode is commonly connected to the corresponding block selection line BLKSEL.

The block selection circuit 23 further includes a plurality of transistors (not shown). These plurality of transistors are field effect type withstand voltage transistors connected between the selection gate line (SGD, SGS, _SGSb ) and the voltage supply line to which the ground voltage VSS is supplied. These plurality of transistors supply the ground voltage VSS to the selection gate lines (SGD, SGS, _SGSb ) included in the non-selection memory block BLK. The plurality of word lines WL included in the non-selected memory block BLK are in a floating state.

The voltage selection circuit 24 includes a plurality of voltage selection units 36 corresponding to the word line WL and the selection gate line (SGD, SGS, SGSb). Each of the plurality of voltage selection units 36 includes a plurality of voltage selection transistors 37. The voltage selection transistor 37 is, for example, a field effect type withstand voltage transistor. The drain terminal of the voltage selection transistor 37 is electrically connected to the corresponding word line WL or selection gate line (SGD, SGS, SGSb) via the wiring CG and the block selection circuit 23, respectively. Each source terminal is electrically connected to the corresponding voltage supply line 31. Each gate electrode is connected to the corresponding voltage selection line 33.

[Configuration of sense amplifier module SAM]
The sense amplifier module SAM includes, for example, a plurality of sense amplifier units SAU (FIG. 6) corresponding to a plurality of bit line BLs. The sense amplifier unit SAU includes a sense amplifier SA connected to the bit line BL, a wiring LBUS connected to the sense amplifier SA, and a plurality of latch circuits DL connected to the wiring LBUS, respectively. The sense amplifier SA includes a sense circuit connected to the bit line BL, a voltage transfer circuit connected to the bit line BL, and a latch circuit connected to the sense circuit and the voltage transfer circuit. The sense circuit includes a sense transistor that is turned on or off according to the voltage or current of the bit line BL and discharges the electric charge in the wiring LBUS according to this state. The voltage transfer circuit conducts the bit line BL with either of the two voltage supply lines according to the data latched by the latch circuit in the sense amplifier SA. The wiring LBUS in the sense amplifier unit SAU is connected to the wiring dbus constituting the bus DBUS via the switch transistor DSW.

[Configuration of cache memory CM]
The cache memory CM includes a plurality of latch circuits XDL (FIG. 6) connected to a latch circuit in the sense amplifier module SAM via a plurality of wiring dbus constituting the bus DBUS. The latch circuit XDL stores, for example, user data written in the memory cell MC or user data read from the memory cell MC. The data DAT included in the plurality of latch circuits XDL is sequentially transferred to the sense amplifier module SAM or the input / output control circuit I / O.

Further, a decoding circuit and a switch circuit (not shown) are connected to the cache memory CM. The decoding circuit decodes the column address CA stored in the address register ADR (FIG. 4). The switch circuit conducts the latch circuit XDL corresponding to the column address CA with the bus DB (FIG. 4) according to the output signal of the decoding circuit.

[Structure of sequencer SQC]
The sequencer SQC (FIG. 4) outputs an internal control number to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG according to the command data D _CMD stored in the command register CMR. Further, the sequencer SQC outputs the status data D _ST indicating the state of the memory die MD to the status register STR as appropriate.

Further, the sequencer SQC generates a ready / busy signal and outputs it to the terminal RY // BY. During the period (busy period) when the signal of the terminal RY // BY is in the "L" state, access to the memory die MD is basically prohibited. Further, during the period (ready period) when the signal of the terminal RY // BY is in the "H" state, access to the memory die MD is permitted. The signal of the terminal RY // BY is realized by, for example, the pad electrode P described with reference to FIGS. 2 and 3. The signal output from the terminal RY // BY may be referred to as a ready / busy signal RY // BY.

[I / O control circuit I / O configuration]
The input / output control circuit I / O includes data signal input / output terminals DQ0 to DQ7, toggle signal input / output terminals DQS, / DQS, input circuits such as comparators connected to data signal input / output terminals DQ0 to DQ7, and OCD ( Off Chip Driver) Equipped with an output circuit such as a circuit. Further, the input / output circuit I / O includes a shift register connected to these input circuits and output circuits, and a buffer circuit. The input circuit, output circuit, shift register, and buffer circuit are connected to terminals to which the power supply voltage V _CCQ and the ground voltage _VSS are supplied, respectively. The data signal input / output terminals DQ0 to DQ7, the toggle signal input / output terminals DQS, / DQS, and the terminals to which the power supply voltage _VCCQ is supplied are realized by, for example, the pad electrodes P described with reference to FIGS. 2 and 3. ..

The data input via the data signal input / output terminals DQ0 to DQ7 is output from the buffer circuit to the cache memory CM, the address register ADR, or the command register CMR according to the internal control signal from the logic circuit CTR. Further, the data output via the data signal input / output terminals DQ0 to DQ7 is input to the buffer circuit from the cache memory CM or the status register STR according to the internal control signal from the logic circuit CTR.

[Configuration of logic circuit CTR]
The logic circuit CTR (FIG. 4) receives an external control signal from the controller die CD via the external control terminal / Cen, CLE, ALE, / WE, RE, / RE, and the input / output control circuit I / The internal control signal is output to O. The external control terminals / CEn, CLE, ALE, / WE, RE, / RE are realized by, for example, the pad electrodes P described with reference to FIGS. 2 and 3.

The external control terminal / CEn is used when selecting the memory die MD. The input / output control circuit I / O of the memory die MD in which "L" is input to the external control terminal / CEn performs input / output of data via the data signal input / output terminals DQ0 to DQ7. The input / output control circuit I / O of the memory die MD in which "H" is input to the external control terminal / CEn does not input / output data via the data signal input / output terminals DQ0 to DQ7. The signal input to the external control terminal / CEn may be referred to as a chip enable signal / CEn.

Further, the external control terminal CLE is used when using the command register CMR. When "H" is input to the external control terminal CLE, the data input via the data signal input / output terminals DQ0 to DQ7 is stored in the buffer memory in the input / output control circuit I / O as command data D _CMD . Transferred to the command register CMR. The signal input to the external control terminal CLE may be referred to as a command latch enable signal CLE.

Further, the external control terminal ALE is used when the address register ADR is used. When "H" is input to the external control terminal ALE, the data input via the data signal input / output terminals DQ0 to DQ7 is stored in the buffer memory in the input / output control circuit I / O as address data D _ADD . Transferred to the address register ADR. The signal input to the external control terminal ALE may be referred to as an address latch enable signal ALE.

When "L" is input to both the external control terminals CLE and ALE, the data DAT input via the data signal input / output terminals DQ0 to DQ7 is used as user data in the buffer in the input / output control circuit I / O. It is stored in the memory and transferred to the cache memory CM via the bus DB.

The external control terminal / WE is used when inputting data via the data signal input / output terminals DQ0 to DQ7. The data input via the data signal input / output terminals DQ0 to DQ7 is taken into the shift register in the input / output control circuit I / O at the timing of the rise of the voltage of the external control terminal / WE (switching of the input signal). .. The signal input to the external control terminal / WE may be referred to as a write enable signal / WE.

The toggle signal input / output terminals DQS and / DQS are used when data is input via the data signal input / output terminals DQ0 to DQ7. Data input via the data signal input / output terminals DQ0 to DQ7 is the rising edge of the voltage of the toggle signal input / output terminal DQS (switching of the input signal) and the falling edge of the voltage of the toggle signal input / output terminal / DQS (input signal). Input / output control circuit It is taken into the shift register in the I / O. The signal input to the toggle signal input / output terminal DQS, / DQS may be referred to as a data strobe signal DQS, / DQS.

When inputting data, the external control terminal / WE may be used, or the toggle signal input / output terminals DQS and / DQS may be used.

The external control terminals RE and / RE are used when outputting data via the data signal input / output terminals DQ0 to DQ7. The data output from the data signal input / output terminals DQ0 to DQ7 includes the timing of the voltage drop of the external control terminal RE (switching of the input signal) and the timing of the voltage rise of the external control terminal / RE (switching of the input signal). , The voltage of the external control terminal RE is switched at the rising edge (switching of the input signal) and the voltage of the external control terminal / RE is falling (switching of the input signal). The signals input to the external control terminals RE, / RE may be referred to as read enable signals RE, / RE.

[Configuration of address register ADR]
As shown in FIG. 7, the address register ADR is connected to the input / output control circuit I / O via the path S101 and stores the address data _DADD input from the input / output control circuit I / O. The address register ADR includes, for example, register circuit sets RG101 and RG102 including 6 sets of 8-bit register sequences including an 8-bit register circuit Register [7: 0]. The 8-bit register circuit Register [7: 0] may include, for example, eight latch circuits that hold 1-bit data using a pair of CMOS inverters. When an internal operation such as a read operation, a write operation, or an erase operation is executed, the register circuit set RG101 holds the address data D _ADD corresponding to the internal operation being executed. The register circuit set RG102 temporarily saves the address data D _ADD corresponding to the write operation or the erase operation when, for example, the write operation or the erase operation is temporarily suspended and the read operation is executed. It can be used in some cases.

[Command register CMR configuration]
The command register CMR is connected to the input / output control circuit I / O via the path S102, and stores the command data D _CMD input from the input / output control circuit I / O. The command register CMR includes, for example, a register circuit set RG103 including one set of 8-bit register sequences including an 8-bit register circuit Register [7: 0]. The 8-bit register circuit Register [7: 0] may include, for example, eight latch circuits that hold 1-bit data using a pair of CMOS inverters. When the command data D _CMD is stored in the command register CMR, a control signal is transmitted to the sequencer SQC via the path S108, or a control circuit is transmitted to the queue register control circuit QRC via the path S107.

[Cue register QR configuration]
The queue register QR is connected to the address register ADR via the path S103 and the path S104, and to the command register CMR via the path S105 and the path S106, and inputs / outputs data to / from the address register ADR and the command register CMR in both directions. ..

The path S103 and the path S105 are routes for transferring data from the address register ADR and the command register CMR to the queue register QR.

The path S104 and the path S106 are routes for transferring data from the queue register QR to the address register ADR and the command register CMR.

The configurations of paths S103, S104, S105, and S106 can be adjusted as appropriate. For example, the paths S103, S104, S105, and S106 are turned on according to the eight wires for transferring data and the Q set operation described later, and are turned off according to the Q end operation described later. It may include a switch circuit. Further, the paths S103 and S104 may include a switch circuit such as a MOS transistor that is turned on when the address data is transferred and turned off when the command data is transferred. Further, the paths S105 and S106 may include a switch circuit such as a MOS transistor that is turned off when the address data is transferred and turned on when the command data is transferred. Further, the path S103 and the path S104 may be realized by a common configuration. Further, the path S105 and the path S106 may be realized by a common configuration.

The queue register QR is a register including 10 sets of a total of 9-bit register strings including, for example, an 8-bit register circuit Register [7: 0] for storing address command data and a 1-bit register circuit ADDnCMD for determining an address command. The circuit set RG104 is provided. The 8-bit register circuit Register [7: 0] may include, for example, eight latch circuits that hold 1-bit data using a pair of CMOS inverters. The 1-bit register circuit ADDnCMD may include, for example, one latch circuit that holds 1-bit data using a pair of CMOS inverters.

The 8-bit register circuit Register [7: 0] for storing address / command data stores 8-bit data constituting the address data D _ADD or the command data D _CMD . The 1-bit register circuit ADDnCMD for determining the address command is a 1-bit indicating whether the data stored in the 8-bit register circuit Register [7: 0] for storing the address command data is address data or command data. Store the data of. For example, when the data stored in the 8-bit register circuit Register [7: 0] for storing address and command data is command data D _CMD , "H" is stored, and the stored data is address data D _ADD . When there is, "L" is stored.

When neither the address data nor the command data is stored in the register column, for example, the same data as the command data C999 described later is stored in the 8-bit register circuit Register [7: 0] of this register sequence. “H” is stored in the 1-bit register circuit ADDnCMD of the register sequence.

The data storage operation in the queue register QR is a FIFO (First In First Out) operation, and the first input data is output first. The specific configuration of the queue register QR can be adjusted as appropriate. The queue register QR may be configured as, for example, a shift register that updates data according to the rising edge of the signal line QueCLK. In such a case, for example, the data stored in the first register string to the ninth register string is transferred from the second register string to the tenth register string according to the rising edge of the signal line QueCLK. .. Further, when the path S103 or the path S105 is open, the data stored in the address register ADR or the command register CMR is transferred to the first register string. Further, when neither the path S103 nor the path S105 is open, the data stored in the tenth register string is transferred to the first register string. Further, when the path S104 or the path S106 is open, the data stored in the tenth register string is transferred to the address register ADR or the command register CMR. However, even when the path S104 or the path S106 is open, if the data stored in the tenth register string is the command data C999, this data is stored in the address register ADR and the command register CMR. Is not transferred.

It should be noted that the data input to the cue register QR is the command data D _CMD or the address data D between the cue register QR and the command register CMR, and at least one of the cue register QR and the address register ADR. A circuit for storing "H" or "L" may be provided in the 1-bit register circuit ADDnCMD depending on whether it is _ADD . Such a circuit may be realized, for example, by connecting a signal line for controlling at least one of the switch circuit included in the path S103 and the switch circuit included in the path S105 to the 1-bit register circuit ADDnCMD. The input terminal may be connected to such a signal line, and the output terminal may be provided with a CMOS inverter connected to the 1-bit register circuit ADDnCMD. Further, for example, the queue register control circuit QRC acquires the signal levels of the external control terminal CLE and / or the external control terminal ALE from the logic circuit CTR, and "H" is added to the 1-bit register circuit ADDnCMD according to those signal levels. "Or" L "may be stored.

Further, between the queue register QR and the command register CMR and the address register ADR, a queue register is used depending on whether the data output from the queue register QR is command data D _CMD or address data D _ADD . A circuit may be provided for connecting the 8-bit register circuit Register [7: 0] in the QR to the 8-bit register circuit Register [7: 0] in the command register CMR or the address register ADR. Such a circuit is realized, for example, by connecting a signal line for controlling the switch circuit included in the path S104 and a signal line for controlling the switch circuit included in the path S106 to the 1-bit register circuit ADDnCMD. Alternatively, a CMOS inverter or the like in which the output terminal is connected to such a signal line and the input terminal is connected to the 1-bit register circuit ADDnCMD may be provided.

[Configuration of queue register control circuit QRC]
The queue register control circuit QRC is connected to the command register CMR via the path S107. The queue register control circuit QRC is configured to be able to execute a Q set operation, a Q end operation, a Q execution operation, and a Q reset operation based on the command data input from the command register CMR.

The Q set operation is an operation of opening the path S103 and the path S105 through the path S201 and permitting the transfer of data from the command register CMR and the address register ADR to the queue register QR.

The Q-end operation is an operation of blocking the path S103 and the path S105 through the path S202 and prohibiting the transfer of data from the command register CMR and the address register ADR to the queue register QR.

The Q execution operation is an operation of opening the path S104 and the path S106 through the path S203 and sequentially transferring all the data stored in the queue register QR to the command register CMR and the address register ADR.

The Q reset operation is an operation of erasing all the data stored in the queue register QR. When the Q reset operation is executed, the command data C999 is stored in all the 8-bit register circuits Register [7: 0] in the queue register QR. Further, "H" is stored in all the 1-bit register circuits ADDnCMD in the queue register QR.

The configurations of paths S201 and S202 can be adjusted as appropriate. For example, the path S201 and the path S202 are connected to the switch circuit included in the path S103 and the path S105, and the switch circuit is made conductive according to the execution of the Q set operation (when the switch circuit is composed of an nanotube transistor, ". Even if it has one common wiring that becomes H "state" and does not conduct the switch circuit according to the execution of Q-end operation (when the switch circuit is composed of an NaCl transistor, it becomes "L" state). good. Further, for example, the path S201 and the path S202 include a flip-flop circuit, an RS flip-flop circuit, or other circuit in which an output terminal is connected to such a wiring and the output signal is inverted in response to a rectangular wave input. Is also good.

Further, the configuration of the path S203 can be adjusted as appropriate. For example, the path S203 is connected to the path S104 and the switch circuit included in the path S106, and the switch circuit is made conductive according to the start of the Q execution operation (when the switch circuit is composed of an NaCl transistor, the “H” state. ), And the switch circuit may be provided with one common wiring that is in a state where the switch circuit is not conducted (“L” state when the switch circuit is composed of an NaCl transistor) according to the end of the Q execution operation. Further, for example, the path S203 may include a flip-flop circuit, an RS flip-flop circuit, or other circuit in which the output terminal is connected to such a wiring and the output signal is inverted according to the input of the rectangular wave.

Further, when the switch circuits included in the paths S103 and S104 are realized by a common configuration, and when the switch circuits included in the paths S105 and S106 are realized by a common configuration, the paths S201 and the path are realized. A part or all of the configuration included in S202 and a part or all of the configuration included in the path S203 may be realized by a common configuration.

Although the cue register control circuit QRC is shown as an independent circuit in FIG. 7, the cue register control circuit QRC may be configured as a part of the sequencer SQC.

[Read operation]
Next, the reading operation of the semiconductor storage device according to the present embodiment will be described with reference to FIG.

At the timing t101, the controller die CD inputs the command data C101 as the command data D _CMD to the memory die MD. The command data C101 is a command indicating the start of input of the command set CmdOP0 corresponding to the read operation.

When inputting data as command data D _CMD , set the voltage of data signal input / output terminals DQ0 to DQ7 to "H" or "L" according to each bit of the input data, and set it to the external control terminal CLE. With "H" input and "L" input to the external control terminal ALE, the external control terminal / WE is started from "L" to "H". At this time, instead of raising the signal of the external control terminal / WE, the signals of the toggle signal input / output terminals DQS and / DQS may be switched (toggled).

At the timings t102, t103, t104, t105, t106, the controller die CD inputs the address data A101, A102, A103, A104, _A105 as the address data DADD to the memory die MD.

When inputting data as address data D _ADD , set the voltage of the data signal input / output terminals DQ0 to DQ7 to "H" or "L" according to each bit of the input data, and set it to the external control terminal CLE. With "L" input and "H" input to the external control terminal ALE, the external control terminal / WE is started from "L" to "H". At this time, instead of raising the signal of the external control terminal / WE, the signals of the toggle signal input / output terminals DQS and / DQS may be switched (toggled).

The address data A101 to A105 include, for example, a column address CA (FIG. 4) and a row address RA (FIG. 4). The row address RA specifies, for example, a block address that specifies the memory block BLK (FIG. 5), a page address that specifies the string unit SU and the word line WL, a plane address that specifies the memory cell array MCA, and a memory die MD. Includes chip address and.

At the timing t107, the controller die CD inputs the command data C102 as the command data D _CMD to the memory die MD. The command data C102 is a command indicating that the input of the command set corresponding to the read operation is completed.

At the timing t108, the signal of the terminal RY // BY changes from the “H” state to the “L” state, access to the memory die MD is prohibited, and the read operation commanded by the command set CmdOP0 is executed in the memory die MD. As a result, the data stored in the memory cell array MCA (FIG. 4) is read out to the cache memory CM (FIG. 4).

At the timing t109, the read operation in the memory die MD ends, the signal of the terminal RY // BY changes from the “L” state to the “H” state, and access to the memory die MD is permitted.

[Write operation]
Next, the writing operation of the semiconductor storage device according to the present embodiment will be described with reference to FIG. 9.

At the timing t111, the controller die CD inputs the command data C111 as the command data D _CMD to the memory die MD. The command data C111 is a command indicating the start of input of the command set corresponding to the write operation.

At the timings t112, t113, t114, t115, t116, the controller die CD inputs the address data A111, A112, A113, A114, A115 as the address data D _ADD to the memory die MD.

The address data A111 to A115 include, for example, a column address CA (FIG. 4) and a row address RA (FIG. 4). The row address RA specifies, for example, a block address that specifies the memory block BLK (FIG. 5), a page address that specifies the string unit SU and the word line WL, a plane address that specifies the memory cell array MCA, and a memory die MD. Includes chip address and.

From the timing t117 to the timing before the timing t120, the controller die CD inputs the data D111, D112, D113 ... As the data DAT to the memory die MD. The data D111, D112, D113 ... Are user data stored in the memory cell array MCA by the write operation.

When inputting data as a data DAT, the voltage of the data signal input / output terminals DQ0 to DQ7 is set to "H" or "L" according to each bit of the input data, and "L" is set to the external control terminal CLE. Is input, and with "L" input to the external control terminal ALE, the external control terminal / WE is started from "L" to "H". At this time, instead of raising the signal of the external control terminal / WE, the signals of the toggle signal input / output terminals DQS and / DQS may be switched (toggled).

At the timing t120, the controller die CD inputs the command data C112 as the command data D _CMD to the memory die MD. The command data C112 is a command indicating that the input of the command set CmdOP1 corresponding to the write operation has been completed.

At the timing t121, the signal of the terminal RY // BY changes from the “H” state to the “L” state, access to the memory die MD is prohibited, and the write operation commanded by the command set CmdOP1 is executed in the memory die MD. As a result, the data D111, D112, D113 ... Input from the timing t117 to the timing before the timing t120 are stored in the memory cell array MCA (FIG. 4).

At the timing t122, the writing operation in the memory die MD ends, the signal of the terminal RY // BY changes from the “L” state to the “H” state, and access to the memory die MD is permitted.

At the timing t123, the controller die CD inputs the command data C113 as the command data D _CMD to the memory die MD. The command data C113 is a command corresponding to the status read operation. The status read operation is an operation of outputting status data _DST (FIG. 4) from the memory die MD.

[Erase operation]
Next, with reference to FIG. 10, the erasing operation of the semiconductor storage device according to the present embodiment will be described.

At the timing t131, the controller die CD inputs the command data C121 as the command data D _CMD to the memory die MD. The command data C121 is a command indicating the start of input of the command set corresponding to the erase operation.

At the timings t132, t133, and t134, the controller die CD inputs the address data A121, A122, and A123 as the address data D _ADD to the memory die MD.

The address data A121 to A123 include, for example, a row address RA (FIG. 4). The row address RA includes, for example, a block address for specifying the memory block BLK (FIG. 5), a plane address for specifying the memory cell array MCA, and a chip address for specifying the memory die MD.

At the timing t135, the controller die CD inputs the command data C122 as the command data D _CMD to the memory die MD. The command data C122 is a command indicating that the input of the command set corresponding to the erase operation has been completed.

At the timing t136, the signal of the terminal RY // BY changes from the “H” state to the “L” state, access to the memory die MD is prohibited, and the erase operation commanded by the command set CmdOP2 is executed in the memory die MD. As a result, the data stored in the predetermined memory block BLK (FIG. 5) of the memory cell array MCA (FIG. 4) is erased.

At the timing t137, the erasing operation in the memory die MD ends, the signal of the terminal RY // BY changes from the “L” state to the “H” state, and access to the memory die MD is permitted.

At the timing t138, the controller die CD inputs the command data C113 as the command data D _CMD to the memory die MD.

[Operation using queue register QR]
Next, an example of the operation of the semiconductor storage device according to the present embodiment using the queue register QR will be described with reference to FIG. FIG. 11 is a timing chart for explaining an example of such an operation, and a schematic diagram showing data stored in the queue register QR when such an operation is executed.

In the example of FIG. 11, during the ready period (RY // BY = “H”), the command data C811 instructing the Q set operation and the command data C812 instructing the Q end operation are input. As a result, the command set CmdOP0 described with reference to FIG. 8 is stored in the queue register QR. Next, the command data C813 instructing the Q execution operation is input. As a result, the command set CmdOP0 stored in the queue register QR is transferred to the command register CMR and the address register ADR, and the read operation (internal operation OP0) is executed. When the command data C816 instructing the Q reset operation is input, the command set CmdOP0 stored in the queue register QR is deleted.

Hereinafter, the operation will be described according to the timing chart in FIG.

At the timing t140, the signal of the terminal RY // BY is in the “H” state. Further, at the timing t140, the command data C999 is stored in the 8-bit register circuit Register [7: 0] corresponding to all the register sequences in the queue register QR, and is stored in the 1-bit register circuit ADDnCMD corresponding to all the register sequences. "H" is stored.

At the timing t141, the controller die CD inputs the command data C811 instructing the Q set operation as the command data D _CMD to the memory die MD. The command data C811 is input to the register circuit set RG103 in the command register CMR through the path S102 (FIG. 7).

When the command data C811 is input to the command register CMR, the queue register control circuit QRC is controlled through the path S107. The queue register control circuit QRC performs a Q set operation via the path S201 to open the paths S103 and S105 (FIG. 7).

At the timing t142, the controller die CD inputs the command data C101 as the command data D _CMD to the memory die MD. Here, at the timing t142, the path S103 and the path S105 are open. When the command data C101 is input in this state, the pulse signal is input once to the signal line QueCLK of the semiconductor storage device. Along with this, the command data C101 input to the command register CMR is transferred to the 8-bit register circuit Register [7: 0] corresponding to the first register string in the queue register QR through the path S105. Further, at this time, since the command data C101 is the command data D _CMD , "H" is stored in the 1-bit register circuit ADDnCMD for the address command determination.

At the timing t143, the controller die CD inputs the address data A101 to the memory die MD as a part of the address data D _ADD . Here, at the timing t142, the path S103 and the path S105 are open. When the address data A101 is input in this state, the pulse signal is input once to the signal line QueCLK of the semiconductor storage device. Along with this, the address data A101 input to the address register ADR is transferred to the 8-bit register circuit Register [7: 0] corresponding to the first register string in the queue register QR through the path S103. Further, at this time, since the address data A101 is the address data D _ADD , "L" is stored in the 1-bit register ADDnCMD for the address command determination. The command data C101 and "H" stored in the first register string are transferred to the second register string.

At the timing t144, the controller die CD inputs the address data A102 to the memory die MD as a part of the address data D _ADD . Along with this, the address data A102 and "L" are stored in the first register column in the queue register QR, the address data A101 and "L" are stored in the second register column, and the address data A101 and "L" are stored in the third register column. Command data C101 and "H" are stored.

At the timing t145, the controller die CD inputs the address data A103 to the memory die MD as a part of the address data D _ADD . Along with this, the address data A103 and "L" are stored in the first register column and the address data A102 and "L" are stored in the second register column in the queue register QR, and the address data A102 and "L" are stored in the third register column. Address data A101 and "L" are stored, and command data C101 and "H" are stored in the fourth register string.

At the timing t146, the controller die CD inputs the command data C102 as the command data D _CMD to the memory die MD. Along with this, the command data C112 and "H" are stored in the first register column in the queue register QR, the address data A113 and "L" are stored in the second register column, and the third register column is stored. Address data A112 and "L" are stored, address data A111 and "L" are stored in the fourth register column, and command data C111 and "H" are stored in the fifth register column.

At the timing t147, the controller die CD inputs the command data C812 instructing the Q-end operation as the command data D _CMD to the memory die MD.

When the command data C812 is input to the command register CMR, the queue register control circuit QRC is controlled through the path S107. The queue register control circuit QRC performs a Q-end operation via the path S202 and shuts off the path S103 and the path S105 (FIG. 7).

At the timing t148, the controller die CD inputs the command data C813 instructing the Q execution operation as the command data D _CMD to the memory die MD. The command data C813 is input to the register circuit set RG103 in the command register CMR through the path S102 (FIG. 7).

When the command data C813 is input to the command register CMR, the queue register control circuit QRC is controlled through the path S107. The queue register control circuit QRC opens the path S104 and the path S106 via the path S203. Further, the pulse signal is input to the signal line QueCLK of the semiconductor storage device 10 times. When the pulse signal is input once, the data stored in the tenth register string of the queue register QR is transferred to the command register CMR or the address register ADR and the first register string of the queue register QR. However, of the data stored in the queue register QR, the command data C999 is not transferred to the command register CMR. Further, when the pulse signal is input once, the data stored in the 1st to 9th register strings of the queue register QR is transferred to the 2nd to 10th register strings of the queue register QR. Therefore, when the pulse signal is input 10 times in the illustrated example, the command data C101 stored in the fifth register string to the command data C102 stored in the first register string are the command register CMR and the address register ADR. The data is sequentially transferred to, and the read operation (internal operation OP0) is executed at the timing t149.

Whether or not the data is stored in the queue register QR can be determined, for example, by executing the status read operation by inputting the command data C113 (FIG. 9). For example, as illustrated in FIG. 11, at the timing t150 after the read operation (internal operation OP0) is completed, the controller die CD inputs the command data C816 instructing the Q reset operation as the command data D _CMD to the memory die MD. do. When the command data C816 is input, the command data C999 is stored in all the 8-bit register circuits Register [7: 0] in the queue register QR, and "H" is stored in all the 1-bit register circuits ADDnCMD in the queue register QR. Is stored.

Further, the data stored in the queue register QR is held in the queue register QR until the Q reset operation is executed. Therefore, for example, as illustrated in FIG. 12, when the command data C813 is input again at the timing t149 after the timing t148, the read operation (internal operation OP0) is executed again.

Further, even if the timing is after the command data C811 is input and before the command data 812 is input, when the command data C999 is input to the semiconductor storage device, the command data C999 is the queue register QR. The operation corresponding to the command data C999 is executed by the sequencer SQC without being transferred to. For example, in the example of FIG. 13, at such timing t151, the command data C999 instructing the internal reset operation is input as the command data D _CMD . Further, the command data C999 is not transferred to the queue register QR, but is stored in the register circuit set RG103 in the command register CMR. After that, the internal reset operation by the sequencer SQC is executed. As a result, for example, even if it becomes necessary to perform an internal reset operation while the command set is being stored in the queue register QR, the sequencer SQC can immediately execute the internal reset operation, so that the operation of the memory die MD can be performed. Can improve the reliability of.

Further, FIGS. 11 to 13 show an example in which the command set CmdOP0 corresponding to the read operation is stored in the queue register QR. However, the queue register QR may store a part or all of another command set such as a part of the command set CmdOP1 corresponding to the write operation or the command set CmdOP2 corresponding to the erase operation.

For example, in the example of FIG. 14, the command data C811 instructing the Q set operation is input at the timing t151, the command set CmdOP1 is input from the timing t152 to the timing t153, and the command data C812 instructing the Q end operation is input at the timing t154. It has been entered. Here, in the present embodiment, in the command set CmdOP1 (FIG. 9), only the command data C111 and the command data C112 corresponding to the command data and the address data A111 to A115 corresponding to the address data are in the queue register QR. It is stored, and the data DAT1 (data D111, D112, D113 ...) Is not stored in the queue register QR.

Further, for example, in the example of FIG. 14, the command data C814 instructing the start of data input is input at the timing t155, and the data DAT1 (data D111, D112) included in the command set CmdOP1 from the timing t156 to the timing before the timing t158. ...) Is input, and the command data C815 instructing the end of data input is input at the timing t158. Here, in the present embodiment, the data D111, D112 ... Input from the timing t156 to the timing before the timing t158 are stored in the cache memory CM (FIG. 4).

Further, for example, in the example of FIG. 14, the command data C813 instructing the Q execution operation is input at the timing t159. Along with this, the writing operation (internal operation OP1) is started at the timing t160.

[effect]
According to the semiconductor storage device according to the present embodiment, by storing the command set in the queue register QR in advance, the same internal operation can be executed a plurality of times only by inputting a command for the Q execution operation. Therefore, for example, when the same internal operation is executed a plurality of times, the time required for inputting the command set to the memory die MD can be significantly reduced. This makes it possible to increase the speed of operation of the semiconductor storage device.

[Second Embodiment]
Next, the semiconductor storage device according to the second embodiment will be described with reference to FIG. FIG. 15 is a timing chart for explaining the operation of the semiconductor storage device according to the present embodiment, and a schematic diagram showing data stored in the queue register QR when this operation is executed.

The semiconductor storage device according to the second embodiment is basically configured in the same manner as the semiconductor storage device according to the first embodiment. However, the queue register control circuit QRC according to the first embodiment is configured to execute an operation such as a Q set operation based on the command data input from the command register CMR. On the other hand, the cue register control circuit according to the second embodiment is configured to automatically execute an operation such as a Q set operation according to the state of the semiconductor storage device.

Further, the semiconductor storage device according to the present embodiment disables, for example, an operation mode that enables automatic execution of such a Q-set operation and automatic execution of such a Q-set operation. The operation mode may be configured to be selectable by, for example, the set_feature function. When the automatic execution of the Q set operation or the like is enabled, for example, the set_feature command set modeset for setting the operation mode is input to the memory die MD to enable "QueueBusyMode".

When "QueueBusyMode" is enabled, the input command set is the sequencer SQC via the command register CMR and the address register ADR if the signal (ready busy signal) of the terminal RY // BY is in the "H" state. The first internal operation corresponding to the command input by the sequencer SQC is executed. At this time, the input command set is not transferred to the queue register QR.

In the semiconductor storage device according to the present embodiment, when the execution of the first internal operation is started, the signal of the terminal RY // BY drops from the “H” state to the “L” state. Further, this makes it possible to execute the Q set operation.

When "QueueBusyMode" is enabled, the input command set is a queue register via the command register CMR and the address register ADR if the signal (ready busy signal) of the terminal RY // BY is in the "L" state. It is transferred to the QR and stored in the queue register QR.

When the first internal operation executed during the input of the command set is completed, the Q-end operation and the Q execution operation are automatically executed, and the second internal operation corresponding to the command set stored in the queue register QR is executed. Is started. Further, after the execution of the Q execution operation, the Q reset operation may be automatically executed during the execution of the second internal operation. During the execution of the second internal operation, the signal of the terminal RY // BY is in the “L” state.

When the second internal operation is completed, the signal of the terminal RY // BY rises from the “L” state to the “H” state.

Hereinafter, the operation will be described according to the timing chart in FIG.

At the timing t2111, the controller die CD inputs the set_feature command set modeset as the command data D _CMD to the memory die MD, and enables "QueueBusyMode".

At the timing t212, the controller die CD inputs the command data C121 as the command data D _CMD to the memory die MD. Here, at the timing t212, the signal of the terminal RY // BY is in the “H” state. Therefore, the command data C121 is not transferred to the queue register QR but is stored in the command register CMR.

At the timings t213, t214 and t215, the controller die CD inputs the address data A121, A122, A123 as the address data D _ADD to the memory die MD. Here, at the timings t213, 214, 215, the signal of the terminal RY // BY is in the “H” state. Therefore, the address data A121, A122, and A123 are not transferred to the queue register QR but are stored in the address register ADR.

At the timing t216, the controller die CD inputs the command data C122 as the command data D _CMD to the memory die MD. Here, at the timing t216, the signal of the terminal RY // BY is in the “H” state. Therefore, the command data C122 is not transferred to the queue register QR but is stored in the command register CMR.

At the timing t217, the execution of the internal operation OP2 is started according to the command set CmdOP2. Along with this, the signal of the terminal RY // BY is in the “L” state.

At the timing t218, the controller die CD inputs the command data C121 as the command data D _CMD to the memory die MD. Here, at the timing t218, the signal of the terminal RY // BY is in the “L” state. Therefore, with the input of the command data C121, the command data C221 and "H" are stored in the first register string in the queue register QR.

At the timings t219, t220 and t221, the controller die CD inputs the address data A121 ′, A122 ′, A123 ′ as the address data D _ADD to the memory die MD. The address data A121', A122', A123'may specify, for example, an address different from the address data A121, A122, A123 input from the timing t213 to the timing t215. Here, at the timing t219, 220, 221, the signal of the terminal RY // BY is in the “L” state. Therefore, with the input of the address data A121', A122', and A123', the address data A123'and "L" are stored in the first register column in the queue register QR, and the address data A122'is stored in the second register column. ´ and “L” are stored, address data A121 ′ and “L” are stored in the third register column, and command data C121 and “H” are stored in the fourth register column.

At the timing t222, the controller die CD inputs the command data C122 as the command data D _CMD to the memory die MD. Here, at the timing t222, the signal of the terminal RY // BY is in the “L” state. Therefore, with the input of the command data C122, the command data C122 and "H" are stored in the first register column in the queue register QR, and the address data A123'and "L" are stored in the second register column. Address data A122'and "L" are stored in the third register column, address data A121'and "L" are stored in the fourth register column, and command data C121 and "H" are stored in the fifth register column. Is stored.

At the timing t223, the execution of the internal operation OP2 ends. Along with this, the Q-end operation and the Q-execution operation are automatically executed, and the execution of the internal operation OP2'corresponding to the command set CmdOP2' stored in the queue register QR is started.

In the example of FIG. 15, the Q execution operation is executed at the timing when the execution of the internal operation OP2 is completed, but the timing at which the Q execution operation is executed is the timing immediately before the execution of the internal operation OP2 is completed. May be. Such timing is, for example, a period during which the execution of the internal operation OP2 is substantially completed and the voltage of the wiring in the memory cell array MCA is returned to the voltage or the like when the internal operation is not executed (hereinafter, “recovery”). It may be a predetermined timing in "period" or the like.

[effect]
According to the semiconductor storage device according to the present embodiment, it is not necessary to input the command data C811 and C812 in order to store the data in the queue register QR according to the signal of the terminal RY // BY. Further, it is not necessary to input the command data C813 in the Q execution operation. Therefore, it is possible to input the command set to the queue register QR by inputting the same number of commands as before. Therefore, it is possible to realize high-speed operation of the semiconductor storage device.

Further, according to the semiconductor storage device according to the present embodiment, it is possible to input a command set when the signal of the terminal RY // BY is in the “L” state. Therefore, it is possible to realize high-speed operation of the semiconductor storage device as compared with the case where the command set is input after waiting for the signal of the terminal RY // BY to rise to the “H” state.

[Third Embodiment]
Next, the semiconductor storage device according to the third embodiment will be described with reference to FIG. FIG. 16 is a timing chart for explaining the operation of the semiconductor storage device according to the present embodiment.

The semiconductor storage device according to the third embodiment is basically configured in the same manner as the semiconductor storage device according to the first embodiment. However, the semiconductor storage device according to the first embodiment is configured so that the command set can be input to the queue register QR only during the ready period. On the other hand, the semiconductor storage device according to the third embodiment is configured so that the command set can be input to the queue register QR even during the busy period.

Hereinafter, the operation will be described according to the timing chart in FIG.

The operation illustrated in FIG. 16 is executed in the same manner as the operation illustrated in FIG. 15 up to the timing t217.

At the timing t311 the command data C811 instructing the Q set operation is input, the command set CmdOP2'is input from the timing t312 to the timing t316, and the command data C812 instructing the Q end operation is input at the timing t317.

At the timing t318, the execution of the internal operation OP2 ends. Along with this, the signal of the terminal RY // BY rises from the "L" state to the "H" state.

At the timing t319, the controller die CD inputs the command data C813 instructing the Q execution operation as the command data D _CMD to the memory die MD.

At the timing t320, the execution of the internal operation OP2'is started. Further, with the start of execution of the internal operation OP2', the signal of the terminal RY // BY drops from the "H" state to the "L" state.

In the present embodiment, when the command set CmdOP1 instructing the write operation is input to the queue register QR, the data DAT1 corresponding to the write operation is separately input as in the example of FIG.

For example, in the example of FIG. 17, the command set CmdOP1 is input from the timing t331 to the timing t332, and the writing operation (internal operation OP1) is started at the timing t333. Along with this, the signal of the terminal RY // BY has dropped from the "H" state to the "L" state.

Further, for example, in the example of FIG. 17, the command data C811 instructing the Q set operation is input at the timing t334, the command set CmdOP1'is input from the timing t335 to the timing t336, and the command instructing the Q end operation at the timing t337. Data C812 has been entered. Here, in the present embodiment, only the command data C111 and the command data C112 corresponding to the command data and the address data A111 to A115 corresponding to the address data are stored in the queue register QR in the command set CmdOP1'. The data DAT2 (data D111, D112, D113 ...) Is not stored in the queue register QR.

Further, for example, in the example of FIG. 17, the writing operation (internal operation OP1) ends at the timing t338, and the signal of the terminal RY // BY rises from the “L” state to the “H” state. Further, the command data C113 instructing the status read operation at the timing t339 is input.

Further, for example, in the example of FIG. 17, the command data C814 instructing the start of data input is input at the timing t340, and the data DAT2 (data D111, data D111,) included in the command set CmdOP1'from the timing t341 to the timing before the timing t343. D112 ...) Is input, and command data C815 instructing the end of data input is input at timing t343.

Further, for example, in the example of FIG. 17, the command data C813 instructing the Q execution operation is input at the timing t344. Along with this, the writing operation (internal operation OP1') is started at the timing t345. Along with this, the signal of the terminal RY // BY has dropped from the "H" state to the "L" state.

[effect]
According to the semiconductor storage device according to the present embodiment, it is possible to input a command set when the signal of the terminal RY // BY is in the “L” state. Therefore, it is possible to realize high-speed operation of the semiconductor storage device as compared with the case where the command set is input after waiting for the signal of the terminal RY // BY to rise to the “H” state.

[Fourth Embodiment]
Next, the semiconductor storage device according to the fourth embodiment will be described with reference to FIG. FIG. 18 is a timing chart for explaining the operation of the semiconductor storage device according to the present embodiment.

The semiconductor storage device according to the fourth embodiment is basically configured in the same manner as the semiconductor storage device according to the third embodiment. However, the semiconductor storage device according to the third embodiment is configured to execute the second internal operation by inputting the command data C813 during the ready period after the end of the first internal operation. On the other hand, the semiconductor storage device according to the fourth embodiment automatically enters the second internal operation after the end of the first internal operation by inputting the command data C842 during the execution of the first internal operation. It is configured to perform internal operations.

Hereinafter, the operation will be described with reference to the timing chart in FIG.

The operation illustrated in FIG. 18 is executed in the same manner as the operation illustrated in FIG. 13 up to the timing t316.

At the timing t401, the controller die CD inputs the command data C842 as the command data D _CMD to the memory die MD instead of the command data C812. The command data C842 is a command instructing that the internal operation corresponding to the command data currently being input is automatically executed according to the end of the internal operation currently being executed.

At the timing t402, the execution of the internal operation OP2 ends. Along with this, the Q execution operation is executed, and the execution of the internal operation OP2'is started.

In the example of FIG. 18, the Q execution operation is executed at the timing when the execution of the internal operation OP2 is completed, but the timing at which the Q execution operation is executed is the timing immediately before the execution of the internal operation OP2 is completed. May be. Such timing may be, for example, a predetermined timing in the recovery period or the like.

[effect]
According to the semiconductor storage device according to the present embodiment, after the end of the internal operation during execution, the operation corresponding to the command set stored in the queue register QR is performed without inputting the command data C813 corresponding to the Q execution operation. It is feasible. Therefore, it is possible to realize further speeding up of the operation of the semiconductor storage device as compared with the third embodiment.

Further, for example, it is possible to improve the operability of the semiconductor storage device by adopting an embodiment in which both the operation as illustrated in FIG. 16 and the operation as illustrated in FIG. 18 can be executed by distinguishing commands. Is.

[Fifth Embodiment]
Next, the semiconductor storage device according to the fifth embodiment will be described with reference to FIG. FIG. 19 is a schematic block diagram showing the configuration of the memory die MD ′ according to the present embodiment.

The semiconductor storage device according to the fifth embodiment is basically configured in the same manner as the semiconductor storage device according to the first embodiment. However, as shown in FIG. 19, in the input / output circuit I / O according to the fifth embodiment, in addition to the data signal input / output terminals DQ0 to DQ7 and the toggle signal input / output terminals DQS and / DQS, the data signal input terminal X1 It is equipped with. The data signal input terminal X1 is realized by, for example, the pad electrode P described with reference to FIGS. 2 and 3. In the fifth embodiment, this data signal input terminal X1 is used when inputting a command set to the queue register QR.

The data signal input terminal X1 is a terminal different from the data signal input / output terminals DQ0 to DQ7, which can accept input during both the ready period and the busy period. The 8-bit data input via the data signal input / output terminals DQ0 to DQ7 is input in parallel from the controller die CD to the memory die MD'. That is, when the signals of the external control terminal / WE or the toggle signal input / output terminals DQS and / DQS are switched once, 8-bit data is input at the same time. On the other hand, the 8-bit data input via the data signal input terminal X1 is serially input from the controller die CD to the memory die MD. That is, each time the signal of the external control terminal / WE or the toggle signal input / output terminals DQS and / DQS is switched once, one bit is sequentially input.

FIG. 20 is a timing chart for explaining the operation of the semiconductor storage device according to the present embodiment.

Hereinafter, the operation will be described with reference to the timing chart in FIG.

The operation illustrated in FIG. 20 is executed in the same manner as the operation illustrated in FIG. 15 up to the timing t217.

From timing t501 to timing t502, 8-bit data constituting the command data C811 is sequentially input bit by bit via the data signal input terminal X1.

From the timing t503 to the timing before the timing t504, the 5 × 8 bit data constituting the command set CmdOP2 ′ and the 1 × 8 bit data constituting the command data C812 are transmitted via the data signal input terminal X1. It is input one bit at a time. Further, in the example of FIG. 20, at the timing t503, the command data C113 instructing the status read operation is input.

At the timing t504, the execution of the internal operation OP2 ends. Further, with the end of the internal operation OP2, the signal of the terminal RY // BY rises from the “L” state to the “H” state.

At the timing t505, the controller die CD inputs the command data C813 instructing the Q execution operation as the command data D _CMD to the memory die MD.

At the timing t506, the execution of the internal operation OP2'is started. Further, with the start of execution of the internal operation OP2', the signal of the terminal RY // BY drops from the "H" state to the "L" state.

In the example of FIG. 20, it is assumed that the command data C811, the command set CmdOP2'and the command data C812 are input via the data signal input terminal X1. However, the command data C842 may be input instead of the command data C812. Further, in such a case, the timing at which the Q execution operation is executed may be the timing at which the execution of the internal operation OP2 is completed or the timing immediately before the execution of the internal operation OP2 is completed.

Further, in the example shown in FIG. 20, an example in which the command set CmdOP2'is input using the command data C811 or the like is shown. However, for example, it is also possible to automatically transfer the command data D _CMD and the address data D _ADD input via the data signal input terminal X1 to the queue register QR.

[effect]
According to the semiconductor storage device according to the present embodiment, the input of the command set stored in the queue register QR is executed via the data signal input terminal X1. Therefore, other operations such as the status read operation can be executed in parallel with the input of the command set stored in the queue register QR. Therefore, it is possible to realize further speeding up of the operation of the semiconductor storage device as compared with the first embodiment.

[Sixth Embodiment]
Next, the semiconductor storage device according to the sixth embodiment will be described with reference to FIG. 21. FIG. 21 is a schematic block diagram showing the configuration of the memory die MD ″ according to the present embodiment.

The semiconductor storage device according to the sixth embodiment is basically configured in the same manner as the semiconductor storage device according to the first embodiment. However, as shown in FIG. 21, the memory die MD ″ according to the sixth embodiment includes two memory cell arrays MCA1 and MCA2 corresponding to the memory cell array MCA described with reference to FIG. 4 and the like, and a sense amplifier module SAM. It includes two corresponding sense amplifier modules SAM1 and SAM2, and two cache memory CM1 and CM2 corresponding to the cache memory CM. The two memory cell arrays MCA1 and MCA2 have different plane addresses, for example, as described above. The sense amplifier modules SAM1 and SAM2 are connected to the memory cell array MCA1 and MCA2, respectively. The cache memories CM1 and CM2 are connected to the sense amplifier modules SAM1 and SAM2, respectively. Further, the input / output circuits I / O according to the present embodiment are connected to the cache memories CM1 and CM2, respectively.

FIG. 22 is a timing chart for explaining the operation of the semiconductor storage device according to the present embodiment, and is a schematic diagram showing data stored in the cache memories CM1 and CM2 when this operation is executed.

As described with reference to FIG. 17, in the semiconductor storage device according to the third embodiment, when the command set CmdOP1'instructing the write operation is input to the queue register QR, the command set CmdOP1'is included in the command set CmdOP1'. Only the command data C111 and the command data C112 corresponding to the command data, and the address data A111 to A115 corresponding to the address data are stored in the queue register QR, and the data DAT2 (data D111, D112, D113 ...) Is stored in the queue register QR. It was not stored.

On the other hand, in the semiconductor storage device according to the sixth embodiment, when the command set CmdOP1'instructing the write operation is input to the queue register QR, the plane address included in this command set CmdOP1'is currently being executed. It is determined whether or not it matches the plane address corresponding to the operation OP1. If the plane addresses match, the data DAT2 is separately input after the internal operation OP1 is executed, as described with reference to FIG. If the plane addresses do not match, the data DAT2 is stored in the cache memory CM1 or the cache memory CM2 corresponding to the command set CmdOP1'as illustrated in FIG.

Hereinafter, the operation will be described with reference to the timing chart in FIG.

The operation illustrated in FIG. 22 is executed in the same manner as the operation illustrated in FIG. 17 up to the timing t339. However, unlike the operation illustrated in FIG. 17, the data DAT2 input between the timing t335 and the timing t336 is stored in the cache memory CM2.

At the timing t601, after the internal operation OP1 is completed, the command data C813 instructing the Q execution operation is input as the command data D _CMD without inputting the data DAT2.

At the timing t602, the execution of the internal operation OP1'is started. Along with this, the signal of the terminal RY // BY drops from the "H" state to the "L" state.

In addition, in FIG. 22, an example of inputting a command set CmdOP1'instructing a write operation during execution of a write operation has been described. However, such an operation can also be executed, for example, when the command set CmdOP1'instructing the write operation is input during the execution of the read operation or the erase operation. Further, the cache memories CM1 and CM2 may not be used in the erasing operation. When the command set CmdOP1'instructing the write operation is input during the execution of such an erase operation, the same operation as that illustrated in FIG. 22 is performed even if the plane addresses match. It is feasible.

Further, in the example shown in FIG. 22, it is assumed that the command data C812 instructing the Q-end operation is input after the command set CmdOP1'is executed. However, the command data C842 may be input instead of the command data C812. Further, in such a case, the timing at which the Q execution operation is executed may be the timing at which the execution of the internal operation OP1 is completed or the timing immediately before the execution of the internal operation OP1 is completed.

Further, in the example shown in FIG. 22, an example in which the command set CmdOP1'is input using the command data C811 or the like is shown. However, for example, the operation as described with reference to FIG. 22 may be executed in the operation mode as described with reference to FIG. Further, even when the command set CmdOP1'is input using the data signal input terminal X1 as described with reference to FIG. 19, the operation as described with reference to FIG. 22 may be executed. ..

[7th Embodiment]
Next, the semiconductor storage device according to the seventh embodiment will be described with reference to FIG. 23. FIG. 23 is a schematic block diagram showing the configuration of the semiconductor storage device according to the present embodiment.

The semiconductor storage device according to the seventh embodiment is basically configured in the same manner as the semiconductor storage device according to the first embodiment. However, as shown in FIG. 23, in the semiconductor storage device according to the seventh embodiment, instead of the queue register QR and the queue register control circuit QRC with reference to FIG. 7, the queue register QR'and the queue register control circuit QRCa, It is equipped with QRCb.

The queue register QR'is connected to the address register ADR via the path S103'and the path S104', and to the command register CMR via the path S105'and the path S106', and data is bidirectionally connected to the address register ADR and the command register CMR. Input / output.

The paths S103', S104', S105', and S106'are basically configured in the same manner as the paths S103, S104, S105, and S106 (FIG. 7). However, the paths S103', S104', S105', and S106'may not include a switch circuit or the like.

The queue register QR'includes two register circuit sets RG104a and RG104b instead of one register circuit set RG104 as described with reference to FIG. 7. These two register circuit sets RG104a and RG104b are respectively configured in the same manner as the register circuit set RG104 described with reference to FIG. 7.

Further, the queue register QR'includes a switch circuit SWa provided between the register circuit set RG104a and the paths S103', S104', S105', S106'. Further, the queue register QR'includes a switch circuit SWb provided between the register circuit set RG104b and the paths S103', S104', S105', S106'. The switch circuits SWa and SWb may include, for example, a configuration corresponding to the switch circuit included in the paths S103, S104, S105, and S106 (FIG. 7).

The queue register control circuits QRCa and QRCb are configured in the same manner as the queue register control circuit QRC described with reference to FIG. 7, respectively. The queue register control circuits QRCa and QRCb are connected to the command register CMR via paths S107a and S107b, respectively. Further, the queue register control circuit QRCa is connected to the register circuit set RG104a and the switch circuit SWa via the path S204a. Further, the queue register control circuit QRCb is connected to the register circuit set RG104b and the switch circuit SWb via the path S204b. The paths S204a and S204b include configurations corresponding to the paths S201, S202, and S203 described with reference to FIG. 7, respectively.

24 and 25 are timing charts for explaining the operation of the semiconductor storage device according to the present embodiment.

The semiconductor storage device according to the seventh embodiment basically operates in the same manner as the semiconductor storage device according to the first embodiment. However, the semiconductor storage device according to the seventh embodiment has a Q set operation, a Q end operation, a Q execution operation, and a Q reset operation for the register circuit set RG104a, and a Q set operation, a Q end operation, and a Q execution for the register circuit set RG104b. The operation and the Q reset operation can be executed independently.

For example, as shown in FIG. 24, the semiconductor storage device according to the seventh embodiment can execute the Q set operation with respect to the register circuit set RG104a by the input of the command data C8a1, and the register circuit set RG104a by the input of the command data C8a2. The Q-end operation for the register circuit set RG104a can be executed by the input of the command data C8a3, the Q execution operation for the register circuit set RG104a can be executed by the input of the command data C8a3, and the Q reset operation for the register circuit set RG104a can be executed by the input of the command data C8a4.

In the example of FIG. 24, the command data C8a1 is input at the timing t7a1, the command set CmdOP0 is input from the timing t7a2 to the timing t7a6, and the command data C8a2 is input at the timing t7a7. As a result, the command set CmdOP0 is stored in the register circuit set RG104a. Further, in the example of FIG. 24, the command data C8a3 is input at the timing t7a8, whereby the read operation (internal operation OP0) is started. Further, in the example of FIG. 24, the command data C8a4 is input at the timing t7a9, whereby the command set CmdOP0 stored in the register circuit set RG104a is erased.

Further, for example, as shown in FIG. 25, the semiconductor storage device according to the seventh embodiment can execute the Q set operation for the register circuit set RG104b by inputting the command data C8b1, and the register circuit can be executed by inputting the command data C8b2. The Q-end operation for the set RG104b can be executed, the Q execution operation for the register circuit set RG104b can be executed by the input of the command data C8b3, and the Q reset operation for the register circuit set RG104b can be executed by the input of the command data C8b4. be.

In the example of FIG. 25, the command data C8b1 is input at the timing t7b1, the command set CmdOP0 is input from the timing t7b2 to the timing t7b6, and the command data C8b2 is input at the timing t7b7. As a result, the command set CmdOP0 is stored in the register circuit set RG104b. Further, in the example of FIG. 25, the command data C8b3 is input at the timing t7b8, whereby the read operation (internal operation OP0) is started. Further, in the example of FIG. 25, the command data C8b4 is input at the timing t7b9, whereby the command set CmdOP0 stored in the register circuit set RG104b is erased.

As described above, the operation as illustrated in FIG. 24 and the operation as illustrated in FIG. 25 can be executed independently. Therefore, for example, between the timing t7a7 and the timing t7a8 in FIG. 24, or between the timing t7a8 and the timing t7a9, the operation corresponding to the timing t7b1 to the timing t7b7, the operation corresponding to the timing t7b8, and the operation corresponding to the timing t7b8 in FIG. It is also possible to execute at least one of the operations corresponding to the timing t7b9.

In the examples shown in FIGS. 24 and 25, an example in which the command set CmdOP0 is input using the command data C8a1, C8b1, etc. is shown. However, for example, the operation as described with reference to FIGS. 24 and 25 may be performed in the operation mode as described with reference to FIG. Further, even when the command set CmdOP0 is input using the data signal input terminal X1 as described with reference to FIG. 19, the operations as shown in FIGS. 24 and 25 may be executed.

Further, in the examples shown in FIGS. 24 and 25, an example in which command data C8a3 and C8b3 are input when the Q execution operation is executed for the register circuit sets RG104a and RG104b is shown. However, for example, the Q execution operation for the register circuit sets RG104a and RG104b is automatically executed by the operation mode as described with reference to FIG. 15, the command corresponding to the command data C842 described with reference to FIG. May be done.

In such a case, for example, the first command set first input during the busy period may be input to the register circuit set RG104a. Further, if the second command set is input before the execution of the first internal operation corresponding to the first command set is started, the second command set is input to the register circuit set RG104b. May be. Further, the first internal operation corresponding to the first command set may be executed at the timing when the internal operation that was being executed at the time of inputting the first command set ends, or at the timing immediately before the end. Further, the second internal operation corresponding to the second command set may be executed at the timing when the first internal operation ends or the timing immediately before the end. Further, for example, when the third command set is further input after the timing when the first internal operation is started, the third command set may be input to the register circuit set RG104a. Further, the third internal operation corresponding to the third command set may be executed at the timing when the second internal operation ends or the timing immediately before the end.

Further, even when the writing operation is executed in the semiconductor storage device according to the present embodiment, the operation as described with reference to FIGS. 21 and 22 can be executed.

[Eighth Embodiment]
Next, the semiconductor storage device according to the eighth embodiment will be described with reference to FIG. 26. FIG. 26 is a schematic block diagram showing the configuration of the semiconductor storage device according to the present embodiment.

The semiconductor storage device according to the eighth embodiment is basically configured in the same manner as the semiconductor storage device according to the first embodiment. However, as shown in FIG. 26, the semiconductor storage device according to the eighth embodiment includes a queue register QR ″ instead of the queue register QR with reference to FIG. 7. Further, the semiconductor storage device according to the eighth embodiment includes a queue register selection circuit QRS.

The queue register QR ″ is connected to the address register ADR via the path S103 ′ and the path S104 ′ and to the command register CMR via the path S105 ′ and the path S106 ′, and is bidirectionally connected to the address register ADR and the command register CMR. Input / output data.

The queue register QR ″ includes m (m is a natural number of 2 or more) register circuit sets RG104 ₁ to RG104 _m , instead of one register circuit set RG104 as described with reference to FIG. 7. The m register circuit sets RG104 ₁ to RG104 _m are each configured in the same manner as the register circuit set RG104 described with reference to FIG. 7.

Further, the cue register QR ″ includes m switch circuits SW _1A to SW _mA provided between the register circuit sets RG104 ₁ to RG104 _m and the paths S103 ′, S104 ′, S105 ′, S106 ′. I have. The switch circuits SW _1A to SW _mA may include, for example, a configuration corresponding to the switch circuit included in the paths S103, S104, S105, and S106 (FIG. 7).

Further, the cue register QR ″ includes m switch circuits SW _1B to SW _mB provided between the register circuit sets RG104 ₁ to RG104 _m and the path S204. The switch circuits SW _1B to SW _mB may include, for example, a configuration corresponding to the switch circuit included in the paths S201, S202, and S203 described with reference to FIG. 7.

The queue register selection circuit QRS is connected to m switch circuits SW _1B to SW _mB via the path S205. The path S205 may include, for example, m wires. The queue register selection circuit QRS may include, for example, MOS transistors connected to these m wires.

FIG. 27 is a timing chart for explaining the operation of the semiconductor storage device according to the present embodiment.

The semiconductor storage device according to the eighth embodiment basically operates in the same manner as the semiconductor storage device according to the first embodiment. However, the semiconductor storage device according to the eighth embodiment can independently execute the Q set operation, the Q end operation, the Q execution operation, and the Q reset operation for m register circuit sets RG104 ₁ to RG104 _m .

For example, as shown in FIG. 27, the semiconductor storage device according to the eighth embodiment has the command data C811 and the command data C8k1 (k is an integer of 1 or more and m or less) with respect to the kth register circuit set RG104 _k . The Q-set operation can be executed, the Q-end operation for the k-th register circuit set RG104 _k can be executed by the input of the command data C812 and the command data C8k1, and the k-th can be executed by the input of the command data C813 and the command data C8k1. The Q execution operation for the register circuit set RG104 _k can be executed, and the Q reset operation for the kth register circuit set RG104 _k can be executed by inputting the command data C814 and the command data C8k1.

The command data C8k1 is a command for designating which of m register circuit sets RG104 ₁ to RG104 _m is to be accessed.

In the example of FIG. 27, the command data C811 is input at the timing t801, the command data C8k1 is input at the timing t802, the command set CmdOP0 is input from the timing t803 to the timing t807, and the command data C812 is input at the timing t808. , Command data C8k1 is input at timing t809. As a result, the command set CmdOP0 is stored in the register circuit set RG104 _k . Further, in the example of FIG. 27, the command data C813 is input at the timing t810, and the command data C8k1 is input at the timing t811, whereby the read operation (internal operation OP0) is started. Further, in the example of FIG. 27, the command data C814 is input at the timing t812 and the command data C8k1 is input at the timing t813, whereby the command set CmdOP0 stored in the register circuit set RG104 _k is erased.

In the example shown in FIG. 27, the command data C8k1 is input even when the Q-end operation is executed at the timing t809. However, for example, when executing the Q-end operation, the input of the command data C8k1 may be omitted. Further, in the example shown in FIG. 27, the command data C8k1 is input even when the Q reset operation is executed at the timing t813. However, for example, when executing the Q reset operation, the input of the command data C8 k1 may be omitted, and the Q reset operation may be executed for all the register circuit sets RG104 _k .

Further, in the semiconductor storage device according to the eighth embodiment, the number of operable register circuit sets RG104 may be specified by setting the operation mode or the like. In this case, for example, all m register circuit sets RG104 ₁ to RG104 _m may be operated, only one may be operated, or all may not be operated.

Further, in the example shown in FIG. 27, an example in which the command set CmdOP0 is input using the command data C811 or the like is shown. However, for example, the semiconductor storage device according to the present embodiment may be operated in the operation mode as described with reference to FIG. Further, in the semiconductor storage device according to the present embodiment, the command set CmdOP0'may be input using the data signal input terminal X1 as described with reference to FIG.

Further, in the example shown in FIG. 27, an example in which the command data C813 and the command data C8k1 are input when the Q execution operation is executed for the register circuit sets RG104 ₁ to RG104 _m is shown. However, for example, the Q execution operation for the register circuit sets RG104 ₁ to RG104 _m is automatically performed by the operation mode as described with reference to FIG. 15, the command corresponding to the command data C842 described with reference to FIG. May be executed in.

Further, even when the writing operation is executed in the semiconductor storage device according to the present embodiment, the operation as described with reference to FIGS. 21 and 22 can be executed.

[Other embodiments]
The above embodiments are merely examples, and specific embodiments and the like can be appropriately changed.

For example, in FIGS. An example is shown. However, the memory die MD may be laminated in a predetermined area on the mounting board MSB, and the controller die CD may be arranged in another area on the mounting board MSB. Further, instead of stacking all of the memory die MDs in one place, a plurality of stacked memory die MDs may be dispersed and stacked in a plurality of places. Further, all the memory die MDs may be provided directly on the mounting board MSB. Further, the mounting board MSB and the pad electrodes P of the plurality of memory die MDs may be connected by other electrodes, wiring, or the like instead of the bonding wire B. For example, it may be connected by an electrode penetrating the substrate of the memory die MD, a so-called TSV (Through Silicon Via) electrode, or the like.

Further, for example, in the above example, the memory cell array MCA is configured as a so-called flash memory including a memory transistor including a charge storage film in the gate insulating film. However, such a configuration is merely an example, and various configurations can be applied as a memory cell array. For example, the memory cell array may be a phase change memory containing a chalcogenide film such as GeSbTe and changing the crystal state of the chalcogenide film according to the writing operation. Further, the memory cell array includes a pair of ferromagnetic films arranged so as to face each other and a tunnel insulating film provided between the ferromagnetic films, and the magnetization direction of the ferromagnetic film changes according to the writing operation. It may be an MRAM (Magnetoresistive Random Access Memory). Further, the memory cell array includes a pair of electrodes and a metal oxide or the like provided between these electrodes, and the ReRAM in which the electrodes are electrically connected to each other via a filament or the like such as an oxygen defect according to a writing operation. (Resistive Random Access Memory) may be used. Further, the memory cell array may be a DRAM (Dynamic Random Access Memory) that includes a capacitor and a transistor and charges and discharges the capacitor during a write operation and a read operation. Further, the memory cell array may have other configurations.

Further, for example, in the above example, the number of bits of the register sequence included in the command register CMR and the register sequence included in the address register is 8 bits, and the number of bits of the plurality of register sequences included in the queue register QR is 9. It was a bit. That is, the number of bits of the register string included in the queue register QR was one bit more than the number of bits of the register sequence included in the command register CMR and the register sequence included in the address register. However, the number of bits of the register string included in the queue register QR may be 2 bits or more larger than the number of bits of the register sequence included in the command register CMR and the register sequence included in the address register.

Further, for example, in the above example, an example in which input / output of a command set, user data, etc. is executed via 8-bit data signal input / output terminals DQ0 to DQ7 has been described. However, the number of data signal input / output terminals can be changed as appropriate.

Similarly, in the fifth embodiment described with reference to FIGS. 19 and 20, a data signal input corresponding to 1-bit data is input to the input / output circuit I / O in addition to the data signal input / output terminals DQ0 to DQ7. The terminal X1 was provided. Further, the command set was input to the queue register QR via the data signal input terminal X1 corresponding to the 1-bit data. However, for example, the input / output circuit I / O may be provided with a data signal input terminal corresponding to data of 2 bits or more in addition to the data signal input / output terminals DQ0 to DQ7. Further, a command set may be input to the queue register QR via the data signal input terminal corresponding to the data of 2 bits or more.

[others]
Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other embodiments, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and variations thereof are included in the scope and gist of the invention, and are also included in the scope of the invention described in the claims and the equivalent scope thereof.

MC ... memory cell, MCA ... memory cell array, PC ... peripheral circuit, ADR ... address register, CMR ... command register, QR ... queue register.

Claims (14)

A memory cell array containing multiple memory cells and
It is connected to the memory cell array and includes a peripheral circuit that inputs and outputs user data in response to the input of a command set including command data and address data.
The peripheral circuit
A command register having an n-bit first register sequence capable of holding n (n is a natural number) bit data constituting the command data, and a command register.
An address register having an n-bit second register sequence capable of holding n-bit data constituting the address data, and an address register.
A plurality of third register rows capable of holding at least n + 1 bit data are provided, and the third register row can hold n-bit data constituting the command data and n-bit data constituting the address data. A semiconductor storage device with a cue register. The third register sequence is
A first register circuit connected to the first register row and the second register row and capable of holding n-bit data,
The semiconductor storage device according to claim 1, further comprising a second register circuit capable of holding at least one bit of data. A first switch circuit connected between the first register circuit and the first register row,
A second switch circuit connected between the first register circuit and the second register row is provided.
When the data held in the first register circuit is transferred to the first register row or the second register row,
When the first information is held in the second register circuit, the first switch circuit is turned on and the second switch circuit is turned off.
The semiconductor storage device according to claim 2, wherein when the second information is held in the second register circuit, the first switch circuit is in the OFF state and the second switch circuit is in the ON state. A third switch circuit connected between the first register circuit and the first register row,
A fourth switch circuit connected between the first register circuit and the second register row is provided.
When n-bit data is input to the first register circuit
When the third switch circuit is in the ON state and the fourth switch circuit is in the OFF state, the first information is input to the second register circuit.
The semiconductor storage device according to claim 3, wherein the second information is input to the second register circuit when the third switch circuit is in the OFF state and the fourth switch circuit is in the ON state. The third switch circuit also functions as the first switch circuit.
The semiconductor storage device according to claim 4, wherein the fourth switch circuit also functions as the second switch circuit. A claim configured to be able to execute an internal operation corresponding to the command set held in the queue register in response to the input of the first command data without erasing the command set held in the queue register. The semiconductor storage device according to any one of 1 to 5. The command set input during the execution of the first internal operation is configured to be held in the queue register.
The first item according to any one of claims 1 to 5, wherein the second internal operation corresponding to the command set held in the queue register can be automatically executed after the execution of the first internal operation. Semiconductor storage device. A memory cell array containing multiple memory cells and
It is connected to the memory cell array and includes a peripheral circuit that inputs and outputs user data in response to the input of a command set including command data and address data.
The peripheral circuit
It has a queue register that can hold the entered command set.
A semiconductor storage configured to be able to execute an internal operation corresponding to the command set held in the queue register without erasing the command set held in the queue register in response to the input of the first command data. Device. A memory cell array containing multiple memory cells and
It is connected to the memory cell array and includes a peripheral circuit that inputs and outputs user data in response to the input of a command set including command data and address data.
The peripheral circuit
It has a queue register that can hold the command set entered during the busy period during the execution of the first internal operation.
A semiconductor storage device configured to automatically execute a second internal operation corresponding to a command set held in the queue register after the execution of the first internal operation. The semiconductor storage according to any one of claims 1 to 9, wherein the command set input between the time when the second command data is input and the time when the third command data is input is input to the queue register. Device. The semiconductor storage device according to any one of claims 1 to 9, wherein a command set input during execution of the first internal operation is automatically input to the queue register. N first data input terminals that can be used to input the command set,
It has a second data input terminal that can be used to input the command set.
The semiconductor storage device according to any one of claims 1 to 11, wherein a command set can be input to the queue register via the second data input terminal. The semiconductor storage device according to any one of claims 1 to 12, wherein the command set held in the queue register is erased in response to the input of the fourth command data. The first memory cell array and the second memory cell array,
The first cache memory connected to the first memory cell array and
A second cache memory connected to the second memory cell array is provided.
When a command set containing address data corresponding to the second memory cell array is input during execution of the first internal operation with respect to the first memory cell array, and the input command set includes the user data. The semiconductor storage device according to any one of claims 1 to 13, wherein the user data included in the command set is input to the second cache memory.

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