TWI747704B - Semiconductor memory device - Google Patents

Abstract

The embodiment provides a semiconductor memory device capable of speeding up the writing sequence without reducing reliability. The semiconductor memory device of the embodiment includes a memory transistor and a character line connected to the gate electrode of the memory transistor. When the writing sequence is interrupted after the kth verification operation of the nth writing cycle of the writing sequence ends and before the k+1th verification operation ends, after restarting the writing sequence and starting the k+th Before the first verification operation, supply the verification voltage corresponding to the first verification operation or a larger voltage to the word line. The time from restarting the writing sequence to the beginning of the k+1 verification action is shorter than the time from the beginning of the first verification action of the nth writing cycle to the end of the kth verification action.

Description

Semiconductor memory device

This embodiment is related to a semiconductor memory device.

There is known a semiconductor memory device, which has a substrate, a plurality of gate electrodes laminated in a direction intersecting the surface of the substrate, a semiconductor layer facing the plurality of gate electrodes, and a gate electrode provided And the gate insulating film between the semiconductor layer. The gate insulating film has, for example, an _{insulating charge storage layer such as silicon nitride (Si 3} N ₄ ) or a conductive charge storage layer such as a floating gate, which can store data.

The embodiment provides a semiconductor memory device capable of speeding up the writing sequence without reducing reliability.

The semiconductor memory device of one embodiment includes a memory transistor and a character line connected to the gate electrode of the memory transistor. In addition, the semiconductor memory device is configured to perform a write sequence of performing multiple write cycles on the memory transistor. The write cycle includes a program operation of supplying a program voltage to the word line and at least one verification operation of supplying a verification voltage to the word line. During the period from the beginning to the end of the writing sequence, when the writing sequence is not interrupted, in the nth (n is a natural number) writing cycle, the program action is executed once, and m (m is 2 or more) Natural number) verification actions. When the writing sequence is interrupted after the kth (k is a natural number less than m) verification operation in the nth writing cycle of the writing sequence and before the k+1 verification operation ends, restart After the writing sequence and before starting the k+1 verification operation, the word line is supplied with a verification voltage corresponding to the first verification operation or a voltage greater than it. The time from restarting the writing sequence to the beginning of the k+1 verification action is shorter than the time from the beginning of the first verification action of the nth writing cycle to the end of the kth verification action.

Next, the semiconductor memory device of the embodiment will be described in detail with reference to the drawings. In addition, the following embodiment is only an example, and is not intended to limit the present invention. In addition, the following drawings are schematic diagrams, and for convenience of explanation, some of the components may be omitted. In addition, there are cases where the same reference numerals are given to the common parts in the plural embodiments, and the description is omitted.

In addition, in this manual, when referring to "semiconductor memory device", sometimes it also refers to memory die, and sometimes it also refers to memory chip, memory card, SSD (Solid State Drive), etc., including control The memory system of the device die. Furthermore, sometimes it also refers to the configuration of a smart phone, a tablet terminal, a personal computer, etc., which includes a host.

In addition, in this specification, when it is mentioned that the first configuration is "electrically connected" to the second configuration, the first configuration can be directly connected to the second configuration, and the first configuration can also be connected via wiring, semiconductor components, or transistors. Etc. connected to the second configuration. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor is "electrically connected" to the third transistor.

In addition, in this specification, when referring to the case where the first configuration is "connected" between the second configuration and the third configuration, it means that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected in series. When the configuration is connected to the third configuration via the first configuration.

In addition, in this specification, when referring to a case where a circuit or the like causes two wires to be "conducted", for example, it means that the circuit includes a transistor, etc., which is provided in the current path between the two wires. Wait for the situation in the ON state.

In this specification, the specific direction parallel to the upper surface of the substrate is referred to as the X direction, and the direction parallel to the upper surface of the substrate and perpendicular to the X direction is referred to as the Y direction, which is perpendicular to the upper surface of the substrate. The direction is called the Z direction.

In addition, in this specification, the direction along a specific surface is sometimes referred to as the first direction, the direction along the specific surface and the first direction is referred to as the second direction, and the direction intersecting the specific surface is sometimes referred to as The third direction. The first direction, the second direction, and the third direction may correspond to any one of the X direction, the Y direction, and the Z direction, or may not correspond.

In addition, in this manual, expressions such as "up" or "down" are based on the substrate. For example, the direction away from the substrate along the above-mentioned Z direction is referred to as up, and the direction approaching the substrate along the Z direction is referred to as down. In addition, when referring to the lower surface or the lower end of a structure, it means the surface or end of the substrate side of the structure, and when referring to the upper surface or the upper end, it means the surface or the surface of the structure opposite to the substrate. Ends. In addition, the surface intersecting the X direction or the Y direction is referred to as a side surface or the like.

[First Embodiment] [Memory System 10] FIG. 1 is a schematic block diagram showing the structure of the memory system 10 of the first embodiment.

The memory system 10 reads, writes, and deletes user data based on signals sent from the host 20. The memory system 10 is, for example, a memory chip, a memory card, an SSD, or other systems capable of storing user data. The memory system 10 includes a plurality of memory dies MD for storing user data, and a controller die CD connected to the plurality of memory dies MD and the host 20. The controller die CD has, for example, a processor, RAM (Random Access Memory), etc., and performs logical and physical address conversion, error detection/correction, garbage collection (compression), wear leveling, etc. deal with.

FIG. 2 is a schematic side view showing a configuration example of the memory system 10 of this embodiment. Fig. 3 is a schematic plan view showing the same configuration example. For ease of description, a part of the configuration is omitted in FIGS. 2 and 3.

As shown in FIG. 2, the memory system 10 of this embodiment includes a mounting substrate MSB, a plurality of memory die MD laminated on the mounting substrate MSB, and a controller die CD laminated on the memory die MD. In the Y-direction end region on the upper surface of the mounting substrate MSB, a pad electrode P is provided, and the other part of the region is connected to the lower surface of the memory die MD via an adhesive or the like. In the Y-direction end region on the upper surface of the memory die MD, there is provided a pad electrode P, and other regions are connected to the lower surface of other memory die MD or controller die CD via an adhesive or the like. In the Y-direction end region on the upper surface of the controller die CD, a pad electrode P is provided.

As shown in FIG. 3, the mounting substrate MSB, the plurality of memory die MD, and the controller die CD each have a plurality of pad electrodes P arranged in the X direction. The plurality of pad electrodes P provided on the mounting substrate MSB, the plurality of memory die MD, and the controller die CD are connected to each other via bonding wires B, respectively.

In addition, the structure shown in Fig. 2 and Fig. 3 is only an example, and the specific structure can be appropriately adjusted. For example, in the examples shown in FIGS. 2 and 3, the controller die CD is stacked on a plurality of memory die MD, and these components are connected by bonding wires B. In this configuration, a plurality of memory die MD and controller die CD are contained in one packet. However, the controller die CD can also be contained in a different package from the memory die MD. In addition, a plurality of memory die MD and controller die CD may be connected to each other via through electrodes or the like instead of bonding wires B.

[Circuit configuration of memory die MD] FIG. 4 is a schematic block diagram showing the structure of the memory die MD of the first embodiment. 5 and 6 are schematic circuit diagrams showing a part of the structure of the memory die MD.

In addition, a plurality of control terminals and the like are shown in FIG. 4. These plural control terminals are described as the control terminal corresponding to the high effective signal (positive logic signal), as the control terminal corresponding to the low effective signal (negative logic signal), and as the high effective signal and The situation described by the control terminals corresponding to both low effective signals. In Figure 4, the symbol of the control terminal corresponding to the low effective signal includes an overline. In this manual, the symbol of the control terminal corresponding to the low effective signal contains a slash ("/").

As shown in FIG. 4, the memory die MD includes a memory cell array MCA for storing data, and a peripheral circuit PC connected to the memory cell array MCA. The peripheral circuit PC includes a voltage generating circuit VG, a column decoder RD, a sense amplifier module SAM, and a sequence generator SQC. In addition, the peripheral circuit PC has a cache memory CM, an address register ADR, a command register CMR, and a status register STR. In addition, the peripheral circuit PC includes an input/output control circuit I/O and a logic circuit CTR.

[Circuit configuration of memory cell array MCA] The memory cell array MCA is shown in Fig. 5 and has a plurality of memory blocks BLK. Each of the plurality of memory blocks BLK has a plurality of string units SU. Each of the plurality of string units SU has a plurality of memory strings MS. One end of the plurality of memory strings MS is respectively connected to the peripheral circuit PC via the bit line BL. In addition, the other ends of the plurality of memory strings MS are respectively connected to the peripheral circuit PC via a common source line SL.

The memory string MS is provided with: a drain-side selection transistor STD, a plurality of memory cells MC (memory transistor), a source-side selection transistor STS, and a source connected in series between the bit line BL and the source line SL Side select transistor STSb. Hereinafter, the drain-side selection transistor STD, the source-side selection transistor STS, and the source-side selection transistor STSb are sometimes simply referred to as selection transistors (STD, STS, STSb).

The memory cell MC is a field effect transistor having a semiconductor layer functioning as a channel region, a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of the memory cell MC changes according to the amount of charge in the charge storage film. The memory cell MC stores 1-bit or multiple-bit data. In addition, word lines WL are respectively connected to the gate electrodes of the plurality of memory cells MC corresponding to one memory string MS. The word lines WL are respectively connected to all the memory strings MS in one memory block BLK.

The selected transistors (STD, STS, STSb) are field-effect transistors with semiconductor layers, gate insulating films, and gate electrodes that function as channel regions. The gate electrodes of the selective transistors (STD, STS, STSb) are respectively connected with selective gate lines (SGD, SGS, SGSb). The drain-side selection gate line SGD is arranged corresponding to the string unit SU, and is commonly connected to all memory strings MS in one string unit SU. The source-side selection gate line SGS is commonly connected to all the memory strings MS in the plurality of string units SU. The source-side selection gate line SGSb is commonly connected to all the memory strings MS in the plurality of string units SU.

[Circuit configuration of voltage generating circuit VG] The voltage generating circuit VG (FIG. 4) is connected to a plurality of voltage supply lines 31 as shown in FIG. 5, for example. The voltage generation circuit VG includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit 32. The step-down circuit and the step-up circuit are respectively connected to _{the voltage supply lines supplied with the power supply voltage V CC} and the ground voltage V _SS (Figure 4). These voltage supply lines are connected to the pad electrodes P described with reference to FIGS. 2 and 3, for example. The voltage generating circuit VG, for example, in accordance with the control signal from the sequence generator SQC, generates and applies to the bit line BL, the source line SL, and the word line WL in the read operation, write sequence, and delete sequence of the memory cell array MCA. And select the plural operating voltages of the gate lines (SGD, SGS, SGSb), and output them to the plural voltage supply lines 31 at the same time. The operating voltage output from the voltage supply line 31 is appropriately adjusted according to the control signal from the sequence generator SQC.

[Row decoder RD of the circuit configuration] column decoder RD (FIG. 4) for example, as shown in FIG. 5 includes: address decoder 22 which decodes the address data D _ADD; to block selection circuit 23 and the voltage selection circuit 24, They transmit the operating voltage to the memory cell array MCA according to the output signal of the address decoder 22.

The address decoder 22 includes a plurality of block selection lines BLKSEL and a plurality of voltage selection lines 33. The address decoder 22, for example, in accordance with the control signal from the sequence generator SQC, sequentially refers to the column address RA of the address register ADR (FIG. 4), decodes the column address RA, and will correspond to the column address RA The specific block selection transistor 35 and the voltage selection transistor 37 are set to the on state, and the other block selection transistors 35 and the voltage selection transistor 37 are set to the off state. For example, the voltages of the specific block selection line BLKSEL and the voltage selection line 33 are set to the "H" state, and the other voltages are set to the "L" state. In addition, when using P-channel transistors instead of N-channel transistors, opposite voltages are applied to the wires.

In addition, in the example shown in the figure, in the address decoder 22, a block selection line BLKSEL is set for one memory block BLK one by one. However, this configuration can be changed as appropriate. For example, for more than two memory blocks BLK, block selection lines BLKSEL may be provided one by one.

The block selection circuit 23 includes a plurality of block selection units 34 corresponding to the memory block BLK. Each of the plurality of block selection parts 34 includes a plurality of block selection transistors 35 corresponding to the word line WL and the selection gate line (SGD, SGS, SGSb). The block selection transistor 35 is, for example, a field-effect type piezoelectric crystal. The drain electrode of the block select transistor 35 is electrically connected to the corresponding word line WL or select gate line (SGD, SGS, SGSb), respectively. The source electrode is electrically connected to the voltage supply line 31 via the wiring CG and the voltage selection circuit 24, respectively. The gate electrodes are commonly connected to the corresponding block selection line BLKSEL.

In addition, the block selection circuit 23 further includes a plurality of transistors (not shown). The plurality of transistors are field effect transistors connected between the selection gate lines (SGD, SGS, SGSb) and the voltage supply line _{supplied with the ground voltage V SS.} The plurality of transistors _{supply the ground voltage V SS} to the selected gate lines (SGD, SGS, SGSb) included in the non-selected memory block BLK.

The voltage selection circuit 24 includes a plurality of voltage selection sections 36 corresponding to the word line WL and the selection gate line (SGD, SGS, SGSb). Each of the plurality of voltage selection units 36 includes a plurality of voltage selection transistors 37. The voltage selection transistor 37 is, for example, a field effect transistor. The drain terminal of the voltage selection transistor 37 is electrically connected to the corresponding word line WL or selection gate line (SGD, SGS, SGSb) through the wiring CG and the block selection circuit 23, respectively. The source terminals are electrically connected to the corresponding voltage supply lines 31 respectively. The gate electrodes are respectively connected to the corresponding voltage selection lines 33.

In addition, in the example shown in the figure, an example in which the wiring CG is connected to the voltage supply line 31 via a voltage selection transistor 37 has been shown. However, this configuration is only an example, and the specific configuration can be appropriately adjusted. For example, the wiring CG may also be connected to the voltage supply line 31 via two or more voltage selection transistors 37.

[Circuit configuration of sense amplifier module SAM] The sense amplifier module SAM includes, for example, a plurality of sense amplifier units SAU corresponding to a plurality of bit lines BL. The sense amplifier unit SAU is shown in Figure 6, each having a sense amplifier SA connected to the bit line BL, a wiring LBUS connected to the sense amplifier SA, a latch circuit SDL connected to the wiring LBUS, and a circuit connected to the wiring LBUS. A plurality of latch circuits DL, and a charging transistor 55 for precharging connected to the wiring LBUS. The wiring LBUS in the sense amplifier unit SAU is connected to the wiring DBUS via the switching transistor DSW.

The sense amplifier SA is provided with a sense transistor 41 as shown in FIG. 6, which discharges the charge of the wiring LBUS according to the current flowing in the bit line BL. The source electrode of the sensing transistor 41 is connected to the voltage supply line _{supplied with the ground voltage V SS.} The drain electrode is connected to the wiring LBUS via the switching transistor 42. The gate electrode is connected to the bit line BL via the sensing node SEN, the discharge transistor 43, the node COM, the clamping transistor 44, and the piezoelectric crystal 45. In addition, the sensing node SEN is connected to the internal control signal line CLKSA via the capacitor 48.

In addition, the sense amplifier SA is equipped with a voltage transmission circuit that, based on the data latched in the latch circuit SDL, connects the node COM and the sense node SEN to _{the voltage supply line of the supplied voltage V DD or} the voltage of the supplied voltage V _SRC The supply line is selectively turned on. The voltage transmission circuit includes: node N1; charging transistor 46, which is connected between node N1 and sensing node SEN; charging transistor 49, which is connected between node N1 and node COM; charging transistor 47, which is connected Between the node N1 and _{the voltage supply line supplied with the voltage V DD} ; and the discharge transistor 50, which is connected between the node N1 and the voltage supply line _{supplied with the voltage V SRC.} In addition, the gate electrodes of the charge transistor 47 and the discharge transistor 50 are commonly connected to the node INV_S of the latch circuit SDL.

In addition, the sensing transistor 41, the switching transistor 42, the discharging transistor 43, the clamping transistor 44, the charging transistor 46, the charging transistor 49, and the discharging transistor 50 are, for example, enhanced NMOS transistors. The piezoelectric crystal 45 is, for example, a depression type NMOS transistor. The charging transistor 47 is, for example, a PMOS transistor.

In addition, the gate electrode of the switching transistor 42 is connected to the signal line STB. The gate electrode of the discharge transistor 43 is connected to the signal line XXL. The gate electrode of the clamp transistor 44 is connected to the signal line BLC. The gate electrode of the piezoelectric crystal 45 is connected to the signal line BLS. The gate electrode of the charging transistor 46 is connected to the signal line HLL. The gate electrode of the charging transistor 49 is connected to the signal line BLX. The signal lines STB, XXL, BLC, BLS, HLL, BLX are connected to the sequence generator SQC.

The latch circuit SDL has: nodes LAT_S, INV_S, an inverter 51 with output terminals connected to the node LAT_S and input terminals connected to the node INV_S, one of the input terminals connected to the node LAT_S and the output terminals connected to the node INV_S Inverter 52, switching transistor 53 connected to node LAT_S and wiring LBUS, and switching transistor 54 connected to node INV_S and wiring LBUS. The switching transistors 53, 54 are, for example, NMOS transistors. The gate electrode of the switching transistor 53 is connected to the sequence generator SQC via the signal line STL. The gate electrode of the switching transistor 54 is connected to the sequence generator SQC via the signal line STI.

Each of the plurality of latch circuits DL has substantially the same configuration as the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL and the gate electrodes of the charging transistor 47 and the discharging transistor 50 in the sense amplifier SA are connected. The latch circuit DL is different from the latch circuit SDL in this point.

The switching transistor DSW is, for example, an NMOS transistor. The switching transistor DSW is connected between the wiring LBUS and the wiring DBUS. The gate electrode of the switching transistor DSW is connected to the sequence generator SQC via the signal line DBS.

In addition, the aforementioned signal lines STB, HLL, XXL, BLX, BLC, and BLS are respectively connected in common among all the sense amplifier units SAU included in the sense amplifier module SAM. In addition, the voltage supply line supplied with the voltage V _{DD and} the voltage supply line supplied with the voltage V _SRC are respectively connected in common among all the sense amplifier units SAU included in the sense amplifier module SAM. In addition, the signal line STI and the signal line STL of the latch circuit SDL are respectively connected in common among all the sense amplifier units SAU included in the sense amplifier module SAM. Similarly, the signal lines corresponding to the signal line STI and the signal line STL in the plurality of latch circuits DL are respectively connected in common among all the sense amplifier units SAU included in the sense amplifier module SAM.

[Circuit configuration of cache memory CM] The cache memory CM (Figure 4) has a plurality of latch circuits connected to the latch circuit in the sense amplifier module SAM via the wiring DBUS. The data DAT contained in the plurality of latch circuits are sequentially transmitted to the sense amplifier module SAM or the input/output control circuit I/O.

In addition, a decoding circuit and a switch circuit (not shown) are connected to the cache memory CM. The decoding circuit decodes the row address CA held in the address register ADR (Figure 4). The switch circuit turns on the latch circuit corresponding to the row address CA and the bus DB (Figure 4) according to the output signal of the decoding circuit.

[Circuit configuration of sequence generator SQC] The sequence generator SQC (Figure 4) outputs internal control signals to the column decoder RD, sense amplifier module SAM and voltage _{according to the command data D CMD held in the command register CMR} Generate circuit VG. In addition, the sequence generator SQC outputs state data D _ST appropriately representing its own state to the state register STR. In addition, the sequence generator SQC generates a ready/busy signal and outputs it to the terminal RY//BY. In addition, the terminal RY//BY is realized by the pad electrode P described with reference to FIGS. 2 and 3, for example.

[Circuit configuration of input and output control circuit I/O] The input and output control circuit I/O has data signal input and output terminals DQ0～DQ7, clock signal input and output terminals DQS, /DQS, and connected to data signal input and output terminals DQ0～DQ7 Input circuits such as comparators and output circuits such as OCD (Off Chip Driver) circuits. In addition, the input/output circuit I/O has a shift register and a buffer circuit connected to the input circuit and output circuit. The input circuit, the output circuit, the shift register and the buffer circuit are respectively connected to the terminals _{supplied with the power supply voltage V CCQ} and the ground voltage V _SS. The data signal input and output terminals DQ0 to DQ7, the clock signal input and output terminals DQS, /DQS, and _{the terminals supplied with the power supply voltage V CCQ are realized} by the pad electrodes P described with reference to FIGS. 2 and 3, for example. The data input through the data signal input and output terminals DQ0～DQ7 are output from the buffer circuit to the cache memory CM, the address register ADR or the command register CMR according to the internal control signal from the logic circuit CTR. In addition, the data output through the data signal input and output terminals DQ0 to DQ7 are input to the buffer circuit from the cache CM or the status register STR according to the internal control signal from the logic circuit CTR.

[Circuit configuration of logic circuit CTR] The logic circuit CTR (Figure 4) receives the external control signal from the controller die CD via the external control terminals /CEn, CLE, ALE, /WE, RE, /RE, and correspondingly outputs the internal control signal to the input and output control circuit I/O. In addition, the external control terminals /CEn, CLE, ALE, /WE, RE, and /RE are realized by the pad electrodes P described with reference to FIGS. 2 and 3, for example.

[The structure of memory die MD] FIG. 7 is a schematic three-dimensional view of the memory die MD. Fig. 8 is a schematic enlarged view of a part of the structure shown in Fig. 7. In addition, FIG. 7 and FIG. 8 are diagrams for explaining the schematic structure of the memory die MD, rather than showing the number, shape, arrangement, etc. of the specific structure.

The memory die MD, for example, as shown in FIG. 7 includes: a semiconductor substrate 100, a transistor layer L _TR provided on the semiconductor substrate 100, wiring layers D0, D1, D2 provided on the transistor layer L _{TR, and wiring layers} D0, the memory cell array layer D1, above the D2 L _MCA, a plurality of wiring layers and arranged in the memory cell array of the top layer L _MCA.

The semiconductor substrate 100 is, for example, a semiconductor substrate containing P-type silicon (Si), and the P-type silicon contains P-type impurities such as boron (B). On the surface of the semiconductor substrate 100, a semiconductor region and an insulating region STI are provided. The semiconductor regions respectively function as channel regions of a plurality of transistors Tr constituting the peripheral circuit PC.

The transistor layer L _{TR has} gate electrodes of a plurality of transistors Tr and a contact CS connected to the plurality of transistors Tr. The gate electrodes and the contacts CS may include, for example, a barrier conductive film such as titanium nitride (TiN) and a laminated film of a metal film such as tungsten (W).

The wiring layers D0, D1, and D2 include a plurality of wirings. The plurality of wirings are electrically connected to at least one of the configuration in the memory cell array MCA and the configuration in the peripheral circuit PC. The plurality of wirings may include, for example, a barrier conductive film such as titanium nitride (TiN) and a laminated film of a metal film such as tungsten (W).

The memory cell array layer L _{MCA is provided} with a plurality of conductive layers 110 arranged in the Z direction, a plurality of semiconductor pillars 120 extending in the Z direction, and a plurality of gates respectively arranged between the plurality of conductive layers 110 and the plurality of semiconductor pillars 120 Insulating film 130.

The conductive layer 110 is a substantially plate-shaped conductive layer extending in the X direction. One or a plurality of conductive layers 110 located in the lowermost layer of the plurality of conductive layers 110 serve as the source-side selection gate lines SGS, SGSb (FIG. 5) and the gates of the plurality of source-side selection transistors STS and STSb connected thereto The electrodes function. In addition, the plurality of conductive layers 110 located further above function as the gate electrodes of the word line WL (FIG. 5) and the plurality of memory cells MC (FIG. 5) connected to it. In addition, the one or more conductive layers 110 located further above function as the gate electrodes of the drain-side selection gate line SGD and the plurality of drain-side selection transistors STD (FIG. 5) connected thereto. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). In addition, the conductive layer 110 may include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). Between a plurality of conductive layers 110 arranged in the Z direction, an insulating layer 101 such as silicon oxide _{(SiO 2) is provided.}

Below the conductive layer 110, a conductive layer 140 is provided. The conductive layer 140 functions as a source line SL (FIG. 5 ). The conductive layer 140 includes a semiconductor layer 141 connected to the lower end of the semiconductor pillar 120 and a conductive layer 142 connected to the lower surface of the semiconductor layer 141. The semiconductor layer 141 may include, for example, polysilicon containing impurities such as phosphorus (P) or boron (B). The conductive layer 142 may include, for example, a metal such as tungsten (W), a conductive layer such as tungsten silicide, or other conductive layers. In addition, an insulating layer 101 such as silicon oxide _{(SiO 2} ) is provided between the conductive layer 140 and the conductive layer 110.

A contact CC extending in the Z direction is connected to the conductive layers 110 and 140. The contact CC may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

The semiconductor pillars 120 are arranged in a specific pattern in the X direction and the Y direction. The semiconductor pillar 120 functions as a channel area of a plurality of memory cells MC and selection transistors (STD, STS, STSb) included in one memory string MS (FIG. 5). The semiconductor pillar 120 is, for example, a semiconductor layer such as polysilicon (Si). The semiconductor pillar 120 has a substantially cylindrical shape with a bottom, and an insulating layer 125 such as silicon oxide is disposed at the center portion. In addition, the outer peripheral surfaces of the semiconductor pillars 120 are respectively surrounded by the conductive layer 110 and opposite to the conductive layer 110.

An impurity region 121 containing N-type impurities such as phosphorus (P) is provided on the upper end of the semiconductor pillar 120. The impurity region 121 is connected to the bit line BL via the contact Ch and the contact Cb.

An impurity region 122 containing N-type impurities such as phosphorus (P) is provided at the lower end of the semiconductor pillar 120. The impurity region 122 is connected to the semiconductor layer 141 of the aforementioned conductive layer 140. The portion of the semiconductor pillar 120 directly above the impurity region 122 functions as a channel region of the source-side selective transistor STSb.

The gate insulating film 130 has a substantially bottomed cylindrical shape covering the outer peripheral surface of the semiconductor pillar 120. The gate insulating film 130 includes, for example, as shown in FIG. 8, a tunnel insulating film 131, a charge storage film 132, and a blocking insulating film 133 laminated between the semiconductor pillar 120 and the conductive layer 110. The tunnel insulating film 131 and the barrier insulating film 133 are, for example, insulating films such as silicon oxide (SiO ₂ ). The charge storage film 132 is, for example, a film capable of storing charges _{such as silicon nitride (Si 3} N _{4 ).} The tunnel insulating film 131, the charge storage film 132, and the blocking insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer peripheral surface of the semiconductor pillar 120.

In addition, FIG. 8 shows an example in which the gate insulating film 130 includes a charge storage film 132 such as silicon nitride. However, the gate insulating film 130 may also be provided with a floating gate such as polysilicon containing N-type or P-type impurities, for example.

The plurality of wiring layers arranged above the memory cell array layer L _MCA include bit lines BL (FIG. 7 ), and pad electrodes P (FIG. 2, FIG. 3 ).

The bit line BL (FIG. 7) may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). The bit line BL extends in the X direction and the Y direction. In addition, the plurality of bit lines BL are respectively connected to one semiconductor pillar 120 included in each string unit SU (FIG. 5 ).

The pad electrode P (FIGS. 2 and 3) may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as aluminum (Al).

[Threshold voltage of memory cell MC] Next, referring to FIG. 9, the threshold voltage of the memory cell MC will be described.

As described above, the memory cell array MCA has a plurality of memory cells MC. When the write sequence is performed on the plurality of memory cells MC, the threshold voltage of the memory cells MC is controlled to a plurality of states.

FIG. 9 is a schematic histogram for explaining the threshold voltage of the memory cell MC for recording 4-bit data. The horizontal axis represents the voltage of the word line WL, and the vertical axis represents the number of memory cells MC in the memory cell array MCA.

In the example of FIG. 9, the threshold voltage of the memory cell MC is controlled to 16 states. For example, the Er state corresponds to the lowest threshold voltage (the threshold voltage of the memory cell MC in the deleted state). For example, the data "1111" can be allocated to the memory cell MC corresponding to the Er state. In addition, the S1 state corresponds to a threshold voltage higher than the threshold voltage corresponding to the above-mentioned Er state. For example, the data "1110" can be allocated to the memory cell MC corresponding to the S1 state. In the same way below, the states S2 to S15 in the figure correspond to threshold voltages that are higher than the threshold voltages corresponding to the states S1 to S14, respectively. The memory cells MC corresponding to these distributions are allocated with different 4-bit data.

For example, the threshold voltage of the memory cell MC controlled to the Er state is lower than the read voltage V _CGS1R and the verification voltage V _{VFYS1 in} FIG. 9. Also, for example, the threshold voltage of the memory cell MC controlled to the S1 state is greater than the readout voltage V _CGS1R and the verification voltage V _{VFYS1 in} FIG. 9, but less than the readout voltage V _CGS2R and the verification voltage V _VFYS2 . Also, for example, the threshold voltage of the memory cell MC controlled to the S2 state is greater than the read voltage V _CGS2R and the verification voltage V _{VFYS2 in} FIG. 9, but less than the read voltage V _CGS3R and the verification voltage V _VFYS3 . In the same way below, the threshold voltage of the memory cell MC controlled in the S3 state to the S15 state in the figure is controlled to be within a specific range. Moreover, the threshold voltages of all memory cells MC are less than the read path voltage V _{READ in} FIG. 9.

[Read action] Next, referring to FIGS. 10 and 11, the read operation of the semiconductor memory device of this embodiment will be described.

Fig. 10 is a schematic waveform diagram for explaining the readout operation. The signal waveform shown in Fig. 10 represents the signal of the terminal RY//BY (Fig. 4) of the memory die MD.

At time t101, the terminal RY//BY (FIG. 4) of the memory die MD is in the "H" state. The controller die CD inputs the command C01 to the memory die MD at time t101, then inputs the address A01, and then inputs the command C02. Command C01 is a command to execute the subject of the read operation. When inputting command C01, for example, set 8-bit data corresponding to command C01 for data signal input and output terminals DQ0～DQ7, and set "L, H, L" for external control terminals /CEn, CLE, and ALE, in this state , Raise the external control terminal /WE from the L state to the H state. In this way, the command C01 is latched into the command register CMR _{as the command data D CMD (Figure 4).} When the address A01 is input, for example, set the 8-bit data contained in the address A01 to the data signal input and output terminals DQ0～DQ7 in sequence, and set “L, L, H” to the external control terminals /CEn, CLE, and ALE. In this state, raise the external control terminal /WE from the L state to the H state multiple times. As a result, the address A01 is latched into the address register ADR _{as the address data D ADD (FIG. 4).} Command C02 is the command to start reading the subject of the action. The input of command C02 is performed in the same way as the input of command C01.

At time t102, the read operation of the memory die MD starts, and the terminal RY//BY (FIG. 4) of the memory die MD is in the "L" state.

At time t103, the read operation of the memory die MD ends, and the terminal RY//BY (FIG. 4) of the memory die MD is in the "H" state.

At time t104, the controller die CD inputs the command C03 to the memory die MD, then inputs the address A01, and then inputs the command C04. Command C03 is a command to output the subject of the data read by the read operation. Command C04 is the command to start the subject of output data. The input of commands C03 and C04 is the same as the input of command C01. Then, the controller die CD reads the data D01 from the memory die MD. When reading the data D01, for example, the 8-bit data output from the data signal input and output terminals DQ0 to DQ7 and the signal input to the external control terminals RE and /RE are switched alternately. The controller die CD performs error detection/correction on the data, and then transmits it to the host 20. In addition, although omitted in FIG. 10, when reading the data D01, the command and address can also be input again.

FIG. 11 is a schematic cross-sectional view for explaining the read operation. In addition, in the following description, the word line WL that is the target of operation is called the selected word line WL _S , and the other character lines WL are called the non-selected word line WL _U. In addition, in the following description, there is a case where a plurality of memory cells MC included in the string unit SU are connected to the selected word line WL _S as "selected memory cell MC".

During the read operation of the memory die MD, for example, the bit line BL is charged. For example, let the latch circuit SDL of FIG. 6 latch "H", and set the state of the signal lines STB, XXL, BLC, BLS, HLL, and BLX to "L, L, H, H, H, H". _{In this way, the voltage V DD is} supplied to the bit line BL and the sensing node SEN, and the charging of these is started. _{Also, for example, the voltage V SRC is} supplied to the source line SL (FIG. 5 ), and the charging is started. The voltage V _SRC has the same magnitude as the ground voltage V _{SS, for example.} The voltage V _{SRC is,} for example, greater than the ground voltage V _SS and less than the voltage V _DD .

In addition, as shown in FIG. 11, for example, a plurality of selected memory cells MC are connected to the bit line BL and the source line SL. _{For example, supply voltage V SG} to the selector gate line (SGD, SGS0, SGSb), and set the selector transistor (STD, STS, STSb) to the ON state. Further, the non-selected word line WL _U readout path supply voltage V _READ, be connected to all non-selected memory cell MC of the word line WL _U ON state.

Further, as shown in FIG. 11, the selection of the word line WL _S supplied with data corresponding to the readout of any one of the read voltage V _CGSR (FIG. 9 reads the voltage _V CGS1R ~ V CGS15R in any one of). Thereby, the memory cell MC corresponding to the arbitrary state of FIG. 9 becomes the on state, and the memory cell MC corresponding to the arbitrary state becomes the off state.

In addition, the on/off state of the selected memory cell MC is detected by the sense amplifier module SAM (Figure 5). For example, the wiring LBUS is charged via the charging transistor 55 of FIG. 6. In addition, the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, H, H, H, L, H", and the charge of the sensing node SEN is discharged to the bit line BL. Here, the voltage of the sensing node SEN connected to the bit line BL corresponding to the on-state memory cell MC is relatively greatly reduced. On the other hand, the voltage of the sensing node SEN connected to the bit line BL corresponding to the memory cell MC in the disconnected state does not decrease too much. Therefore, at a specific timing, the signal line STB is set to the "H" state, the charge of the wiring LBUS is released or maintained, and the signal line STL is set to the "H" state, thereby locking the data representing the state of the selected memory cell MC Stored in the latch circuit SDL. In addition, the data can also be latched to any latch circuit DL other than the latch circuit SDL.

When it is necessary to use a plurality of read voltages V _{CGSR to} perform a read operation, if necessary, repeat the supply of the read voltage V _{CGSR to the selected word line WL S} and detect the on/off state of the selected memory cell MC. Status, and latch the detected data. In addition, arithmetic processing is performed on the latched data, and the data D01 in FIG. 10 is calculated.

Thereafter, according to the command C04 described with reference to FIG. 10, the data D01 is output (FIG. 10). For example, the data D01 detected and calculated by the sense amplifier module SAM is sent to the controller die CD (Figure 1) via the cache memory CM (Figure 4), the bus DB and the input and output control circuit I/O.

[Write order] Next, referring to FIGS. 12-17, the writing sequence of the semiconductor memory device will be described.

Fig. 12 is a schematic waveform diagram for explaining the writing sequence. The signal waveform shown in Fig. 12 represents the signal of the terminal RY//BY (Fig. 4) of the memory die MD.

At time t111, the terminal RY//BY (FIG. 4) of the memory die MD is in the "H" state. The controller die CD inputs the command C11 to the memory die MD at the time t111, then inputs the address A11, then inputs the data D11, and then inputs the command C12. Commands C11 and C12 are commands to execute and start the subject of the writing sequence. The input of commands C11 and C12 is performed in the same way as the input of command C01. The input of address A11 is performed in the same way as the input of address A01. When inputting data D11, for example, set the 8-bit data contained in data D11 to the data signal input and output terminals DQ0～DQ7 in sequence, and set “L, L, L” to the external control terminals /CEn, CLE, and ALE, in this state Next, raise the external control terminal /WE from the L state to the H state multiple times. In this way, the data D11 is latched into the cache memory CM as the aforementioned data DAT (FIG. 4).

At time t112, the writing sequence of the memory die MD starts, and the terminal RY//BY (FIG. 4) of the memory die MD becomes the "L" state.

At time t113, the writing sequence of the memory die MD ends, and the terminal RY//BY (FIG. 4) of the memory die MD becomes the "H" state.

At time t114, the controller die CD inputs a command C13 to the memory die MD. Command C13 is a command to output the subject of status data. The input of command C13 is performed in the same way as the input of command C01. Then, the controller die CD reads the data D12 from the memory die MD. The data D12 is, for example, the status data D _ST (Figure 4). The reading of the data D12 is performed in the same manner as the reading of the data D01.

Fig. 13 is a schematic flow chart for explaining the writing sequence. FIG. 14 is a schematic cross-sectional view for explaining the program actions included in the writing sequence. FIG. 15 is a schematic cross-sectional view for explaining the verification operation included in the writing sequence. Fig. 16 is a schematic waveform diagram for explaining the verification operation. FIG. 17 is a schematic table for explaining the verification operation, showing which state of the state S1 to the state S11 corresponds to the verification operation performed in each write cycle. In addition, in the table illustrated in FIG. 17, only the part corresponding to the state S1 to the state S11 is displayed, and the part corresponding to the state S12 to the state S15 is omitted.

In step S101 (FIG. 13), the number of cycles n _{W is} set to 1. The number of cycles n _W is recorded in the register and so on. In addition, in step S101, the 4-bit data corresponding to the data written in each memory cell MC can be latched to a plurality of latch circuits DL in the sense amplifier unit SAU.

The program operation is performed in step S102.

During the program operation, for example, as shown in Figure 14, it is judged whether to adjust the threshold voltage of a plurality of selection memory cells MC (hereinafter, it is called "write memory cell MC") or not to perform plural selection memories Adjustment of the threshold voltage in the cell MC (hereinafter, there is a situation called "forbidden memory cell MC"). The judgment can be made based on the data of a plurality of latch circuits DL latched in the sense amplifier unit SAU (FIG. 6), for example. _{In addition, the voltage V SRC is} supplied to the bit line BL connected to the writing memory cell MC _{, and the voltage V DD is} supplied to the bit line BL connected to the inhibiting memory cell MC. For example, the latch circuit SDL (FIG. 6) corresponding to the write-in memory cell MC latches "L", and the latch circuit SDL (FIG. 6) corresponding to the inhibit memory cell MC latches "H". In addition, the states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are set to "L, L, H, H, L, H".

In addition, the write-in memory cell MC and the bit line BL are turned on, and the forbidden memory cell MC and the bit line BL are disconnected. _{For example, the voltage V SGD is} supplied to the drain-side selection gate line SGD. The voltage V _{SGD is smaller than the voltage V SG in} FIG. 11, for example. Thereby, the drain side selection transistor STD corresponding to the bit line BL supplied with the voltage V _SRC is turned on, and the drain side selection transistor STD corresponding to the bit line BL _{supplied with the voltage V DD is turned off} Open state. Further, the write voltage V _PASS path of the unselected word lines WL _U supply. The write path voltage V _{PASS is} greater than the read path voltage V _{READ in} FIG. 11, for example.

And, WL _S programming voltage V _PGM is supplied to the selected word line. The program voltage V _{PGM is} greater than the write path voltage V _PASS . Thereby, the electrons are accumulated in the charge accumulation film 132 (FIG. 8) of the desired memory cell MC, and the threshold voltage of the memory cell MC increases.

In step S103 (FIG. 13), a verification operation is performed. Furthermore, in step S104 (FIG. 13), it is determined whether the verification operation has ended. When the verification operation has not ended, proceed to step S103. When the verification operation ends, the process proceeds to step S105.

For example, in the example of FIG. 16, at time t121, the verification operation corresponding to the state S1 is started (step S103). Along with this, the selection of the word line WL _S verify voltage supply _V VFYS1. In addition, the states of the signal lines BLC, HLL, XXL, and STB (FIG. 6) are "H, H, L, L". _{Along with this, the voltage V DD is} supplied to the bit line BL connected to the memory cell MC corresponding to the state S1 _{, and the voltage V SRC is} supplied to the other bit lines BL. Also, for example, as shown in FIG. 15, the selected memory cell MC is connected to the bit line BL and the source line SL.

Also, at timing t122, the states of the signal lines BLC, HLL, XXL, and STB (FIG. 6) are "H, L, H, L".

Also, at timing t123, the states of the signal lines BLC, HLL, XXL, STB (Figure 6) are "H, L, L, H", and the on/off state of the selected memory cell MC is detected, which will indicate the selected memory The data of the state of the cell MC is latched to any latch circuit DL.

In addition, at time t124, the verification operation corresponding to the state S1 (step S103) ends, and in step S104, it is determined that the verification operation has not ended, and the verification operation corresponding to the state S2 is started (step S103). Along with this, the selection of the word line WL _S verify voltage supply _V VFYS2. In addition, the states of the signal lines BLC, HLL, XXL, and STB (Figure 6) are "H, L, L, L".

Also, at timing t125, the states of the signal lines BLC, HLL, XXL, and STB (FIG. 6) are "H, H, L, L". _{Along with this, the voltage V DD is} supplied to the bit line BL connected to the memory cell MC corresponding to the state S2 _{, and the voltage V SRC is} supplied to the other bit lines BL.

Also, at timing t126, the states of the signal lines BLC, HLL, XXL, and STB (FIG. 6) are "H, L, H, L".

Also, at timing t127, the states of the signal lines BLC, HLL, XXL, STB (Figure 6) are "H, L, L, H", and the on/off state of the selected memory cell MC is detected, which will indicate the selected memory The data of the state of the cell MC is latched to any latch circuit DL.

In addition, at timing t128, the states of the signal lines BLC, HLL, XXL, and STB (FIG. 6) are "H, L, L, L".

In addition, at time t129, the verification operation corresponding to the state S2 (step S103) ends, and in step S104, the purpose of ending the verification operation is determined. Along with this, the ground voltage V _SS is supplied to the selected word line WL _S. In addition, the states of the signal lines BLC, HLL, XXL, and STB (Figure 6) are "L, L, L, L".

In addition, in steps S103 and S104, it is determined whether each memory cell MC has reached the target threshold voltage based on the data representing the state of the memory cell MC obtained at time t123, t127, etc. For the memory cell MC determined to reach the target threshold voltage, the data in the plurality of latch circuits DL in the sense amplifier unit SAU corresponding to the memory cell MC is updated. For example, the data in the latch circuit DL is updated to a value indicating write prohibition. Thereby, in the subsequent writing sequence, the memory cell MC is treated as the forbidden memory cell MC. For the memory cell MC judged to have not reached the target threshold voltage, the data in the plurality of latch circuits DL in the sense amplifier unit SAU corresponding to the memory cell MC is maintained.

Further, the number of times of verification performed in each write cycle of operation or the like adjusted in accordance with the number of cycles n _W.

For example, in the example shown in FIG. 17, when the number of cycles n _W is 1, in steps S103 and S104, the verification operation corresponding to the above state S1 is performed. S1 corresponds to the state of the validation operation, for example, connected to the state S1 corresponding to the memory cell MC of the write bit line BL is charged, the selection of the word line WL _S verify voltage supply _V VFYS1.

Moreover, when the number of cycles n _W is 2, in steps S103 and S104, the verification operations corresponding to the above states S1 and S2 are sequentially executed. State S2 corresponds to the validation operation, for example, connected to the state S2 corresponds to the memory cell MC of the write bit line BL is charged, the selection of the word line WL _S verify voltage supply _V VFYS2.

In addition, when the number of cycles n _W is 3, in steps S103 and S104, the verification operations corresponding to the above states S1 to S3 are sequentially executed. To state S3 corresponding to the validation operation, for example, connected to the state S3 corresponding to the memory cell MC of the write bit line BL is charged, the selection of the word line WL _S verify voltage supply _V VFYS3.

In step S105 (Figure 13), the result of the verification action is determined. For example, when it is determined that the number of memory cells MC reaching the target threshold voltage is less than a certain number, it is determined that the verification has failed (FAIL), and the process proceeds to step S106. On the other hand, when it is determined that the number of memory cells MC reaching the target threshold voltage is greater than a certain number, it is determined that the verification is passed (PASS), and the process proceeds to step S108.

In step S106, it is determined _{whether the number of cycles n W} reaches a specific number of times N _W. If it is not reached, the process proceeds to step S107. When the situation is reached, the process proceeds to step S109.

In step S107, the number of cycles _{nW is} increased by 1, and the process proceeds to step S102. Furthermore, in step S107, for example, a specific voltage ΔV is added _{to the program voltage V PGM.}

_{In step S108, the status data D ST} of the subject of the normal end of the writing sequence is stored in the status register STR (FIG. 2) to end the writing sequence.

_{In step S109, the status data D ST} of the subject that the writing sequence has not normally ended is stored in the status register STR (FIG. 2 ), and the writing sequence is ended.

[Interruption and restart of writing sequence] Next, referring to FIGS. 18-20, the interruption and restart of the writing sequence of the semiconductor memory device will be described.

FIG. 18 is a schematic waveform diagram for explaining the interruption and restart of the write sequence. The signal waveform shown in FIG. 18 represents the signal of the terminal RY//BY (FIG. 4) of the memory die MD.

In the example of FIG. 18, at timing t115 during the execution of the write operation, the controller die CD inputs a command C21 to the memory die MD. Command C21 is a command that interrupts the writing operation. The input of command C21 is performed in the same way as the input of command C01.

Furthermore, in the example of FIG. 18, the write operation is interrupted at the subsequent timing t106, and the terminal RY//BY (FIG. 4) of the memory die MD becomes the "H" state.

Furthermore, in the example of FIG. 18, the read operation described with reference to FIG. 10 and FIG. 11 is subsequently performed.

Furthermore, in the example of FIG. 18, at the subsequent timing t117, the controller die CD inputs a command C22 to the memory die MD. Command C22 is a command to restart the writing operation. The input of command C22 is performed in the same way as the input of command C01.

Furthermore, in the example of FIG. 18, the writing operation is restarted at the subsequent timing t118.

Next, with reference to FIGS. 19 and 20, the supply of the interrupt and restart the writing order to the selected word line WL voltage and the like of _S will be described. In addition, FIG. 19 and FIG. 20 illustrate an example in which the number of loops n _W in FIG. 13 is 8, as shown in FIG. 17, where the verification operation is performed 6 times.

First, for comparison, referring to FIG. 19, an example in which the writing sequence is not interrupted will be described.

In the example shown in FIG. 19, the program operation starts at time t131. I.e., WL _S programming voltage V _PGM is supplied to the selected word line. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "L, L, L".

Also, at time t132, the program operation ends. That is, the ground voltage V _SS is supplied to the selected word line WL _S. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "L, L, L".

Furthermore, at time t133, the verification operation corresponding to the state S3 is started. That is, the voltage _V VFYS3 verify the selection word line WL _S supplied. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "H, L, L".

In addition, at timing t134, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, H, L".

Also, at timing t135, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, L, H".

Furthermore, at time t136, the verification operation corresponding to state S3 ends, and the verification operation corresponding to state S4 starts. That is, the voltage _V VFYS4 verify the selection word line WL _S supplied. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "H, L, L".

In addition, at timing t137, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, H, L".

In addition, at timing t138, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, L, H".

Furthermore, at time t139, the verification operation corresponding to state S4 ends, and the verification operation corresponding to state S5 starts. That is, the voltage _V VFYS5 verify the selection word line WL _S supplied. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "H, L, L".

In addition, at timing t140, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, H, L".

In addition, at timing t141, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, L, H".

Furthermore, at time t142, the verification operation corresponding to the state S5 ends, and the verification operation corresponding to the state S6 starts. That is, the voltage _V VFYS6 verify the selection word line WL _S supplied. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "H, L, L".

In addition, at timing t143, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, H, L".

In addition, at timing t144, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, L, H".

Furthermore, at time t145, the verification operation corresponding to state S6 ends, and the verification operation corresponding to state S7 starts. That is, the selection of the word line WL _S verify voltage supply _V VFYS7. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "H, L, L".

Also, at timing t146, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, H, L".

Also, at timing t147, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, L, H".

Furthermore, at time t148, the verification operation corresponding to the state S7 ends, and the verification operation corresponding to the state S8 starts. That is, the voltage _V VFYS8 verify the selection word line WL _S supplied. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "H, L, L".

Also, at timing t149, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, H, L".

Also, at timing t150, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, L, H".

Furthermore, at time t151, the verification operation corresponding to the state S8 ends. That is, the ground voltage V _SS is supplied to the selected word line WL _S. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "L, L, L".

Next, referring to FIG. 20, an example of interrupting and restarting the writing sequence will be described. In the semiconductor memory device of this embodiment, when the writing sequence is interrupted after the kth (k is a natural number less than m) verification operation in the writing sequence is completed and before the k+1 verification operation is completed , After the write sequence is restarted, the virtual verification action corresponding to the kth verification action is executed, and thereafter, the actions after the k+1th verification action are executed. In addition, an example of k=4 is shown in FIGS. 17 and 20. In FIG. 17, the verification action corresponding to the confirmation mark corresponds to the completed verification action, and the verification action corresponding to the circle corresponds to the verification action before execution. Also, in the example of FIG. 17, the number of cycles n _W is 8, and the state of k=4 corresponds to performing 4 verification operations corresponding to states S3 to S6, and not performing 2 times corresponding to states S7 and S8 Verify the status of the action.

In addition, the virtual verification operation can be performed in the same manner as the verification operation. However, in the virtual verification operation, the data indicating whether the selected memory cell MC is on or off may not be latched to the latch circuit. In addition, in the virtual verification operation, the voltage may be supplied to the bit line BL, or the voltage may not be supplied to the bit line BL. In addition, in the virtual verification operation, the sense amplifier module SAM can be operated in the same manner as the verification operation, and part or all of the sense amplifier module SAM may not be operated.

In the example shown in FIG. 20, at timing t131 to timing t144, the writing sequence is executed in the same manner as in the example shown in FIG. 19.

Also, at timing t245, the verification operation corresponding to the state S6 ends, and the writing sequence is interrupted. That is, the ground voltage V _SS is supplied to the selected word line WL _S. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "L, L, L".

Furthermore, at time t242, the writing sequence is restarted, and the virtual verification operation corresponding to the state S6 is started. That is, the voltage _V VFYS6 to verify the ground voltage V _SS is supplied to the selected word line WL _S supplied. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "H, L, L".

In addition, at timing t243, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, H, L".

In addition, at timing t244, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, L, H".

Thereafter, the virtual verification operation corresponding to the state S6 ends, and the operation corresponding to the timing t145 of the writing sequence and later is executed.

[First comparative example] Next, referring to FIG. 21, the interruption and restart of the writing sequence of the semiconductor memory device of the comparative example will be described.

In the semiconductor memory device of the first comparative example, when the writing sequence is interrupted after the kth verification operation of the writing sequence is completed and before the k+1 verification operation is completed, after the writing sequence is restarted, The virtual verification actions corresponding to the first to kth verification actions are sequentially executed, and thereafter, the actions after the k+1th verification action are executed. In addition, Figure 21 shows an example of k=4.

In the example shown in FIG. 21, at timing t131 to timing t144, the writing sequence is executed in the same manner as in the example shown in FIG. 19.

In addition, at timing t245, the verification operation corresponding to the state S6 ends, and the writing sequence is interrupted. That is, the ground voltage V _SS is supplied to the selected word line WL _S. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "L, L, L".

In addition, the writing sequence is restarted at timing t233. In addition, at timing t233 to timing t145, a virtual verification operation corresponding to state S3 to state S6 is performed.

Thereafter, operations corresponding to the timing t145 and later of the writing sequence are executed.

[Second Comparative Example] Next, referring to FIG. 22, the interruption and restart of the writing sequence of the semiconductor memory device of the comparative example will be described.

In the semiconductor memory device of the second comparative example, when the writing sequence is interrupted after the kth verification operation of the writing sequence ends and before the k+1th verification operation ends, after the writing sequence is restarted, The virtual verification action is not executed, and the actions after the k+1th verification action are executed immediately after the write sequence is restarted. In addition, Figure 22 shows an example of k=4.

In the example shown in FIG. 22, at timing t131 to timing t144, the writing sequence is executed in the same manner as in the example shown in FIG. 19.

In addition, at timing t245, the verification operation corresponding to the state S6 ends, and the writing sequence is interrupted. That is, the ground voltage V _SS is supplied to the selected word line WL _S. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "L, L, L".

In addition, the writing sequence is restarted at timing t145, and operations corresponding to the writing sequence after timing t145 are executed.

[Effects of the first embodiment] As described above, in the semiconductor memory device of the first comparative example, after the kth verification operation of the write sequence is completed and before the k+1 verification operation is completed, when the write sequence is interrupted, the write is restarted After entering the sequence, perform virtual verification actions corresponding to the first to kth verification actions, and then perform actions after the k+1th verification action.

In this method, the time from restarting the writing sequence to reaching the k+1th verification operation (the time from timing t233 to timing t145 in FIG. 21) is extended, which may hinder the speeding up of the writing sequence.

Therefore, as described above, in the semiconductor memory device of the second comparative example, when the writing sequence is interrupted after the kth verification operation of the writing sequence is completed and before the k+1 verification operation is completed, After restarting the writing sequence, the virtual verification action is not performed, and the actions after the k+1th verification action are executed immediately after the writing sequence is restarted.

In this method, since the k+1th verification operation is started immediately after the write sequence is restarted, the write sequence can be speeded up.

However, in this method, compared with the method of the first comparative example, there is a case where the reliability of the verification operation performed immediately after the write sequence is restarted is reduced. This is considered to be due to the following phenomenon.

That is, as the semiconductor memory device becomes more integrated, the thickness of the conductive layer 110 that functions as the word line WL becomes smaller and smaller, and the conductive layer 110 becomes higher and higher in resistance. Furthermore, the distance between the conductive layers 110 in the Z direction becomes shorter and shorter, and the electrostatic capacitance in the conductive layer 110 becomes larger. As a result, the time constant in the conductive layer 110 becomes larger and larger, and the time required for the voltage of the entire word line WL to reach the voltage supplied to the word line WL becomes longer and longer.

In the case of performing a verification operation in this state, for example, it is also possible to consider supplying voltage to the word line WL until the voltage of the entire word line WL is saturated, and obtaining information indicating whether the memory cell MC is in an on state or an off state is obtained in this state. material. However, in this method, the time required for the verification operation is prolonged, which may hinder the speeding up of the writing sequence. Therefore, in order to increase the speed of the writing sequence, for example, it may be considered to obtain the above-mentioned data before the voltage of the entire word line WL is saturated.

Herein before, in the first comparative example, the case where the write sequence is interrupted, the interruption is not the case when, in all upcoming time k + 1-verify operation, the selection of the word line WL _S verify voltage supply V _VFYS6, k + 1 times in the first verify operation, the selection of the word line WL _S verify voltage supply _V VFYS7. Thus, the voltage that selects the first k + 1 times to verify operation of the word line WL _S whether write sequence is interrupted, the degree of size are all the same.

Before the other hand, in the second comparative example, the case when the write sequence is interrupted, the forthcoming at times k + 1-verify operation, the ground voltage V _SS is supplied to the selected word line WL _S, in the k + 1 verify operation, the selection of the word line WL _S verify voltage supply _V VFYS7. Therefore, when that the k-th write sequence of interrupt + 1 times to verify voltage selection operation of the word line WL _S, is less than the voltage selecting the k + 1 is not interrupted when the write verify operation sequence of the word line WL _S .

Here, as described above, in the semiconductor memory device of the first embodiment, when the writing sequence is interrupted after the kth verification operation of the writing sequence ends and before the k+1th verification operation ends, After restarting the writing sequence, execute the virtual verification action corresponding to the kth verification action, and then execute the actions after the k+1th verification action.

In this method, the time from restarting the writing sequence to reaching the k+1th verification operation (the time from timing t242 to timing t145 in FIG. 20) is shorter than that of the first comparative example.

Further, in this method, in the upcoming the k + 1 times before the verify operation, the selection of the word line WL _S verify voltage supply _V VFYS6, k + 1 in the first verify operation, the word line selection verification is supplied WL _S The voltage is V _VFYS7 . Thus, the voltage that selects the first k + 1 times to verify operation of the word line WL _S, whether the writing sequence is interrupted, the degree of size are all the same.

Therefore, according to the semiconductor memory device of the first embodiment, it is possible to increase the speed of the writing sequence without reducing the reliability of the writing sequence.

[Second Embodiment] Next, referring to FIG. 23, the semiconductor memory device of the second embodiment will be described. The semiconductor memory device of the second embodiment has basically the same structure as the semiconductor memory device of the first embodiment. However, in the semiconductor memory device of the second embodiment, the operations performed after interrupting the writing sequence and restarting the writing sequence are different from those of the semiconductor memory device of the first embodiment.

In the semiconductor memory device of the second embodiment, when the writing sequence is interrupted after the kth verification operation of the writing sequence ends and before the k+1 verification operation ends, after the writing sequence is restarted, The virtual verification actions corresponding to the k-1th and kth verification actions are sequentially executed, and thereafter, the actions after the k+1th verification action are executed. In addition, an example of k=4 is shown in FIG. 23.

In the example shown in FIG. 23, the writing sequence and the reading operation are basically performed in the same manner as the operation described with reference to FIG. 20.

However, in the example shown in FIG. 23, the writing sequence is not restarted at the timing t242 but at the timing t239.

In addition, from the timing t239 of restarting the writing sequence to the timing t145 of starting the verification operation corresponding to the state S7, the virtual verification operations corresponding to the state S5 and the state S6 are sequentially executed.

[Third Embodiment] Next, referring to FIG. 24, the semiconductor memory device of the third embodiment will be described. The semiconductor memory device of the third embodiment basically has the same structure as the semiconductor memory device of the first embodiment. However, in the semiconductor memory device of the third embodiment, the operations performed after interrupting the writing sequence and restarting the writing sequence are different from those of the semiconductor memory device of the first embodiment.

In the semiconductor memory device of the third embodiment, when the writing sequence is interrupted after the kth verification operation of the writing sequence ends and before the k+1 verification operation ends, after the writing sequence is restarted, Perform the virtual verification action corresponding to the kth verification action twice, and then execute the actions after the k+1 verification action. In addition, Fig. 24 shows an example of k=4.

In the example shown in FIG. 24, the writing sequence and the reading operation are basically performed in the same manner as the operation described with reference to FIG. 20.

However, in the example shown in FIG. 24, the writing sequence is not restarted at the timing t242 but at the timing t239.

In addition, from the timing t239 of restarting the writing sequence to the timing t145 of starting the verification operation corresponding to the state S7, the virtual verification operation corresponding to the state S6 is executed twice.

[Fourth Embodiment] Next, referring to FIG. 25, the semiconductor memory device of the fourth embodiment will be described. The semiconductor memory device of the fourth embodiment has basically the same structure as the semiconductor memory device of the first embodiment. However, in the semiconductor memory device of the fourth embodiment, the operations performed after interrupting the writing sequence and restarting the writing sequence are different from those of the semiconductor memory device of the first embodiment.

In the semiconductor memory device of the fourth embodiment, when the writing sequence is interrupted after the kth verification operation of the writing sequence ends and before the k+1 verification operation ends, after the writing sequence is restarted, The virtual verification actions corresponding to the k+1th and kth verification actions are sequentially executed, and thereafter, the actions after the k+1th verification action are executed. In addition, Figure 25 shows an example of k=4.

In the example shown in FIG. 25, the writing sequence and the reading operation are basically executed in the same manner as the operation described with reference to FIG. 20.

However, in the example shown in FIG. 25, the writing sequence is not restarted at the timing t242 but at the timing t239.

In addition, from the timing t239 of restarting the writing sequence to the timing t145 of starting the verification operation corresponding to the state S7, the virtual verification operations corresponding to the state S7 and the state S6 are sequentially executed.

[Fifth Embodiment] Next, referring to FIG. 26, the semiconductor memory device of the fifth embodiment will be described. The semiconductor memory device of the fifth embodiment has basically the same structure as the semiconductor memory device of the first embodiment. However, in the semiconductor memory device of the fifth embodiment, the operations performed after interrupting the writing sequence and restarting the writing sequence are different from those of the semiconductor memory device of the first embodiment.

In the semiconductor memory device of the fifth embodiment, when the writing sequence is interrupted after the kth verification operation of the writing sequence ends and before the k+1 verification operation ends, after the writing sequence is restarted, Perform the virtual verification action corresponding to the k+1th verification action, and then execute the actions after the k+1th verification action. In addition, Figure 26 shows an example of k=4.

In the example shown in FIG. 26, the writing sequence and the reading operation are basically performed in the same manner as the operation described with reference to FIG. 20.

However, in the example shown in FIG. 26, from the timing t242 of restarting the writing sequence to the timing t145 of starting the verification operation corresponding to the state S7, the virtual verification operation corresponding to the state S7 is executed.

[Sixth Embodiment] Next, referring to FIG. 27, the semiconductor memory device of the sixth embodiment will be described. The semiconductor memory device of the sixth embodiment has basically the same structure as the semiconductor memory device of the first embodiment. However, in the semiconductor memory device of the sixth embodiment, the operation performed after interrupting the writing sequence and restarting the writing sequence is different from that of the semiconductor memory device of the first embodiment.

In the semiconductor memory device of the sixth embodiment, when the writing sequence is interrupted after the kth verification operation of the writing sequence ends and before the k+1 verification operation ends, after the writing sequence is restarted, Perform a virtual verification operation to supply the selected word line WL _{S with a voltage greater} than the verification voltage V VFYS7 corresponding to the k+1th verification operation, and then perform a virtual verification operation corresponding to the k+1th verification operation, which After that, perform actions after the k+1th verification action. In addition, Figure 27 shows an example of k=4.

In the example shown in FIG. 27, the writing sequence and the reading operation are basically executed in the same manner as the operation described with reference to FIG. 20.

However, in the example shown in FIG. 27, the writing sequence is not restarted at the timing t242 but at the timing t239.

In addition, from the timing t239 of restarting the writing sequence to the timing t145 of starting the verification operation corresponding to the state S7, the above-mentioned two virtual verification operations are sequentially performed. Also, in the embodiment of FIG. 27, from the timing t239 to timing T242, the selection word line WL _S supplied corresponds to the state of the verification voltage _V VFYS8 S8.

[The seventh embodiment] Next, referring to FIG. 28, the semiconductor memory device of the seventh embodiment will be described. The semiconductor memory device of the seventh embodiment has basically the same structure as the semiconductor memory device of the first embodiment. However, in the semiconductor memory device of the seventh embodiment, the operations performed after interrupting the writing sequence and restarting the writing sequence are different from those of the semiconductor memory device of the first embodiment.

In the semiconductor memory device of the seventh embodiment, when the writing sequence is interrupted after the kth verification operation of the writing sequence ends and before the k+1 verification operation ends, after the writing sequence is restarted, performing the selection word line WL _S supplied than corresponds to the first authentication verification k + 1 times of operation of the voltage _V VFYS7 large virtual verify operation voltage, thereafter, after performing the first authentication operation time k + 1 operation. In addition, Figure 28 shows an example of k=4.

In the example shown in FIG. 28, the writing sequence and the reading operation are basically executed in the same manner as the operation described with reference to FIG. 20.

However, in the example shown in FIG. 28, from the timing t242 when the writing sequence is restarted to the timing t145 when the verification operation corresponding to the state S7 is started, the above-mentioned virtual verification operation is executed. Also, in the embodiment of FIG. 28, from the timing t242 to timing T145, the selection word line WL _S supplied S8 corresponds to the state of the verification voltage _V VFYS8.

[Eighth Embodiment] Next, referring to FIGS. 29 to 31, the semiconductor memory device of the eighth embodiment will be described. The semiconductor memory device of the eighth embodiment has basically the same structure as the semiconductor memory device of the first embodiment. However, in the semiconductor memory device of the eighth embodiment, the execution sequence of the verification operation is different from that of the semiconductor memory device of the first embodiment.

For example, in the first embodiment, as explained with reference to FIG. 17, FIG. 19, etc., when the number of cycles n _W is 8, at time t133 to time t136, the verification operation corresponding to state S3 is performed, and at time t136 ～Sequence t139, execute the verification action corresponding to state S4, the same below, at time sequence t139~time t151, execute the verification action corresponding to states S5, S6, S7, S8 in sequence. That is, when multiple verification operations are performed in each write cycle, the verification operations are performed in the order from the verification operation corresponding to the low threshold voltage state to the verification operation corresponding to the high threshold voltage state.

On the other hand, in the eighth embodiment, as illustrated in Figs. 29 and 30, when the number of cycles n _W is 8, the verification operation corresponding to the state S8 is executed from time t333 to time t336, and at time t336 ～Sequence t339, execute the verification action corresponding to the state S7, the same below, from the time sequence t339 to the time sequence t351, sequentially execute the verification actions corresponding to the states S6, S5, S4, S3. That is, when a plurality of verification operations are performed in each write cycle, the verification operations are performed in the order from the verification operation corresponding to the high threshold voltage state to the verification operation corresponding to the low threshold voltage state.

In addition, in the eighth embodiment, when the writing sequence is interrupted after the kth verification operation of the writing sequence ends and before the k+1th verification operation ends, the same as in the first embodiment, After the writing sequence is restarted, the virtual verification action corresponding to the kth verification action is executed, and thereafter, the actions after the k+1th verification action are executed.

In the example shown in FIG. 31, from timing t131 to timing t344, the writing sequence is executed in the same manner as in the example shown in FIG. 30.

Furthermore, at timing t445, the verification operation corresponding to the state S5 ends, and the writing sequence is interrupted. That is, the ground voltage V _SS is supplied to the selected word line WL _S. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "L, L, L".

Furthermore, at time t442, the writing sequence is restarted, and the virtual verification operation corresponding to the state S5 is started. That is, the voltage _V VFYS5 to verify the ground voltage V _SS is supplied to the selected word line WL _S supplied. In addition, the states of the signal lines HLL, XXL, and STB (FIG. 6) are "H, L, L".

Also, at timing t443, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, H, L".

In addition, at timing t444, the states of the signal lines HLL, XXL, and STB (FIG. 6) become "L, L, H".

After that, the virtual verification operation corresponding to the state S5 ends, and the operation corresponding to the writing sequence after timing t345 is executed.

In addition, in the above example, similar to the first embodiment, when the writing sequence is interrupted after the kth verification operation of the writing sequence ends and before the k+1th verification operation ends, the writing sequence is restarted After that, the virtual verification action corresponding to the kth verification action is executed, and thereafter, the actions after the k+1th verification action are executed. However, this method is only an example, and the specific aspect can be adjusted appropriately.

For example, as in the second embodiment (FIG. 23), after the kth verification operation of the writing sequence ends and before the k+1th verification operation ends, when the writing sequence is interrupted, restart writing After entering the sequence, perform virtual verification actions corresponding to the k-1th and kth verification actions in sequence.

Also, for example, as in the third embodiment (FIG. 24), when the writing sequence is interrupted after the kth verification operation of the writing sequence is completed and before the k+1 verification operation is completed, the After restarting the writing sequence, execute the virtual verification action corresponding to the kth verification action twice.

Also, for example, as in the fourth embodiment (FIG. 25), when the writing sequence is interrupted after the kth verification operation of the writing sequence is completed and before the k+1 verification operation is completed, the After restarting the writing sequence, the virtual verification actions corresponding to the k+1th and kth verification actions are sequentially executed.

Also, for example, as in the fifth embodiment (FIG. 26), when the writing sequence is interrupted after the kth verification operation of the writing sequence is completed and before the k+1 verification operation is completed, the After restarting the writing sequence, a virtual verification action corresponding to the k+1th verification action is executed.

[Other embodiments] In the foregoing, the semiconductor memory devices of the first embodiment to the eighth embodiment have been described. However, the semiconductor memory devices of these embodiments are only examples, and the specific configuration, operation, etc. can be adjusted appropriately.

For example, in the first embodiment to the eighth embodiment, after the kth verification operation of the writing sequence ends and before the k+1th verification operation ends, when the writing sequence is interrupted, the writing is restarted before the start of the sequence and the first verify operation time k + 1, the selection of the word line WL _S supplied state corresponds to state S1 ~ S15 of the voltage _V VFYS1 ~ verify any verification of the voltage _V VFYS15 one. However, this method is only an example, and the specific method can be adjusted appropriately. For example, contemplated at this time is supplied to a voltage of the selected word line WL _S corresponding to the above operation of the authentication verification voltage 1st. Furthermore, for example, can be considered a voltage supplied to the selected word line WL _S at this time is set to correspond to the above of the authentication verification operation voltage of the k-th, whereby the adjustment can be more suitably selecting the word line WL _S Voltage. Further, at this time can be considered the supply voltage to the selected word line WL _S is at least voltage is less than the programming voltage V _PGM.

Also, for example, in the first embodiment to the eighth embodiment, it has been shown that the execution time of the verification action is the same as the execution time of the virtual verification action, and the number of virtual verification actions executed after restarting the writing sequence is less than that of the first comparative example (Figure 21) example. However, this aspect is only an example, and the specific aspect can be adjusted appropriately. For example, the execution time of the virtual verification action can be made shorter than the execution time of the verification action. In this way, it is possible to further increase the speed of the writing sequence.

Also, for example, as described above, in the virtual verification operation, the voltage may be supplied to the bit line BL, or may not be supplied. In addition, when a voltage is supplied to the bit line BL, which bit line BL is supplied with the voltage can be appropriately adjusted. For example, in the above example, for the memory cell MC determined to reach the target threshold voltage during the verification operation, the data in the plurality of latch circuits DL in the sense amplifier unit SAU corresponding to the memory cell MC is updated to indicate the write Prohibited value. In this case, it is considered that in the virtual verification operation, the number of bit lines BL supplied with voltage is less than the number of bit lines BL supplied with voltage in the verification operation.

However, this aspect is only an example, and the specific method can be adjusted appropriately. For example, for the memory cell MC determined to reach the target threshold voltage during the verification operation, the verification path flag can be individually latched in the sense amplifier unit SAU corresponding to the memory cell MC to maintain the corresponding memory cell MC. 4-bit data. In addition, the number of bit lines BL to which voltage is supplied in the virtual verification operation may be the same as the number of bit lines BL to which voltage is supplied in the verification operation.

[other] Several embodiments of the present invention have been described, but these embodiments are presented as examples only, and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments or their changes are all included in the scope or spirit of the invention, and are included in the invention described in the scope of the patent application and its equivalent scope.

[Related Application Case] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2020-87180 (application date: May 19, 2020). This application includes all the contents of the basic application by referring to the basic application.

10: Memory system 20: Host 22: Address decoder 23: Block selection circuit 24: Voltage selection circuit 31: Voltage supply line 32: Charge pump circuit 33: Voltage selection line 34: Block selection section 35: Block selection transistor 36: Voltage Selection Section 37: Voltage Selection Transistor 41: Sensing Transistor 42: Switching Transistor 43: Discharging Transistor 44: Clamping Transistor 45: Piezoelectric Resistance Crystal 46: Charging Transistor 47: Charging Transistor 48 : Capacitor 49: charging transistor 50: discharging transistor 51: inverter 52: inverter 53: switching transistor 54: switching transistor 55: charging transistor 100: semiconductor substrate 101: insulating layer 110: conductive layer 120 : Semiconductor pillar 121: impurity region 122: impurity region 125: insulating layer 130: gate insulating film 131: tunnel insulating film 132: charge storage film 133: blocking insulating film 140: conductive layer 141: semiconductor layer 142: conductive layer ADR : Address register ALE: External control terminal A01: Address A11: Address B: Bonding line BL: Bit line BLC: Signal line BLK: Memory block BLKSEL: Block selection line BLS: Signal line BLX: Signal line CA : Row address Cb: Contact CC: Contact CD: Controller die CEn: External control terminal/CEn: External control terminal CG: Wiring Ch: Contact CLE: External control terminal CLKSA: Internal control signal line CM: Fast Fetch memory CMR: Command register COM: Node CS: Contact CTR: Logic circuit C01~C04: Command C11~C13: Command C21: Command C22: Command D _ADD : Address data D _AT : Data DB: Bus DBUS: wiring DBS: signal line D _CMD : command data DL: latch circuit DQ0~DQ7: data signal input and output terminals DQS: clock signal input and output terminals / DQS: clock signal input and output terminals DST: status data DSW: switch Transistor D0: Wiring layer D01: Reading data D1: Wiring layer D2: Wiring layer D11: Reading data D12: Reading data Er: Status HLL: Signal line INV_S: Node I/O: Input and output circuit LAT_S: Node LBUS : Wiring LL _MCA : Memory cell array layer L _TR : Transistor layer MC: Memory cell MCA: Memory cell array MD: Memory die MS: Memory string MSB: Mounting substrate N1: Node P: Pad electrode PC: Peripheral circuit RA: column address RD: column decoder RE: external control terminal /RE: external control terminal RY//BY: terminal SA: sense amplifier SAM: sense amplifier module SAU: sense amplifier unit SDL: latch circuit SEN: Sensing node SGD: Drain side selection gate line SGS: Source side selection gate line SGSb: Source side selection gate line SL: Source line SQC: Sequencer STB: Signal line STI: Signal line STL: Signal Line STS: Source-side select transistor STSb: Source-side select transistor SU: String unit S1~S15: State S101~S109: Step Tr: Transistor t101~t104: Timing t106: Timing t111~t115: Timing t117: Timing t118: Timing t121~t129: Timing t131~t151: Timing t234~t245: Timing t333~t351: Timing V _CC : Power supply voltage V _CCQ : Power supply voltage V _CGSR : Reading voltage V _CGS1R ~V _CGS15R : Reading voltage V _DD : Voltage V _PASS : Write path voltage V _PGM : Program voltage V _READ : Read path voltage V _SG : Voltage V _SGD : Voltage V _SRC : Voltage V _SS : Ground voltage VG: Voltage generation circuit V _VFYS : Verification voltage V _VFYS1 ~V _VFYS15 : verification voltage WL: character line WL _S : selected character line WL _U : non-selected character line/WE: external control terminal XXL: signal line

FIG. 1 is a schematic block diagram showing the structure of the memory system 10 of the first embodiment. FIG. 2 is a schematic side view showing a configuration example of the same memory system 10. Fig. 3 is a schematic plan view showing the same configuration example. FIG. 4 is a schematic block diagram showing the structure of the memory die MD of the first embodiment. Figure 5 shows a schematic circuit diagram of a part of the same memory die MD. Fig. 6 shows a schematic circuit diagram of a part of the same memory die MD. Fig. 7 is a schematic three-dimensional view of the same memory die MD. Fig. 8 is a schematic enlarged view of a part of the structure shown in Fig. 7. FIG. 9 is a schematic histogram for explaining the threshold voltage of the memory cell MC. Fig. 10 is a schematic waveform diagram for explaining the readout operation. FIG. 11 is a schematic cross-sectional view for explaining the read operation. Fig. 12 is a schematic waveform diagram for explaining the writing sequence. Fig. 13 is a schematic flow chart for explaining the writing sequence. Fig. 14 is a schematic cross-sectional view for explaining the operation of the program. FIG. 15 is a schematic cross-sectional view for explaining the verification operation. Fig. 16 is a schematic waveform diagram for explaining the verification operation. Fig. 17 is a schematic table for explaining the verification operation. FIG. 18 is a schematic waveform diagram for explaining the interruption and restart of the write sequence. FIG. 19 is a schematic waveform diagram for explaining the interruption and restart of the writing sequence. FIG. 20 is a schematic waveform diagram for explaining the interruption and restart of the writing sequence. FIG. 21 is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the first comparative example. Fig. 22 is a schematic waveform diagram for explaining the interruption and restart of the writing sequence of the second comparative example. Fig. 23 is a schematic waveform diagram for explaining interruption and restart of the writing sequence of the second embodiment. Fig. 24 is a schematic waveform diagram for explaining interruption and restart of the writing sequence of the third embodiment. Fig. 25 is a schematic waveform diagram for explaining interruption and restart of the writing sequence of the fourth embodiment. Fig. 26 is a schematic waveform diagram for explaining interruption and restart of the writing sequence of the fifth embodiment. Fig. 27 is a schematic waveform diagram for explaining interruption and restart of the writing sequence of the sixth embodiment. Fig. 28 is a schematic waveform diagram for explaining interruption and restart of the writing sequence of the seventh embodiment. Fig. 29 is a schematic table for explaining interruption and restart of the writing sequence of the eighth embodiment. Fig. 30 is a schematic waveform diagram for explaining interruption and restart of the writing sequence of the eighth embodiment. Fig. 31 is a schematic waveform diagram for explaining interruption and restart of the writing sequence of the eighth embodiment.

CG: Wiring

HLL: signal line

STB: signal line

t131~t151: Timing

t242~t245: timing

V _PGM : Program voltage

V _SS : Ground voltage

V _VFYS3 ~V _VFYS8 : verification voltage

WL _S : select character line

XXL: signal line

Claims (5)

A semiconductor memory device including: A memory transistor, and a character line connected to the gate electrode of the memory transistor, and are configured to perform a writing sequence of performing a plurality of write cycles on the memory transistor; The write cycle includes a program operation of supplying a program voltage to the word line, and at least one verification operation of supplying a verification voltage to the word line; During the period from the beginning to the end of the above-mentioned writing sequence, when the above-mentioned writing sequence is not interrupted, in the nth (n is a natural number) writing cycle, the above program action is executed once, and m (m is 2 or more natural numbers) above verification actions; The situation where the above writing sequence is interrupted after the kth (k is a natural number less than m) verification operation in the nth writing cycle of the above writing sequence and before the k+1 verification operation ends hour, After restarting the writing sequence and before starting the k+1 verification operation, supply the word line with the verification voltage corresponding to the first verification operation or a larger voltage; The time from restarting the writing sequence to the beginning of the k+1 verification operation is shorter than the time from the beginning of the first verification operation of the nth writing cycle to the end of the kth verification operation. Such as the semiconductor memory device of claim 1, wherein The above m is a natural number above 3; The above k is a natural number above 2; After restarting the writing sequence and before starting the k+1 verification operation, supply the first verification voltage to the word line; The first verification voltage is the verification voltage corresponding to any one of the k-th verification operation to the m-th verification operation of the n-th writing cycle in the writing sequence. Such as the semiconductor memory device of claim 2, wherein The above m is a natural number above 4; The above k is a natural number above 3; After restarting the writing sequence and before supplying the first verification voltage to the word line, supply a second verification voltage to the word line; The second verification voltage is the verification voltage corresponding to any one of the verification operation from the k-1th verification operation of the nth writing cycle to the mth verification operation in the writing sequence. Such as the semiconductor memory device of any one of claims 1 to 3, wherein The above m is a natural number above 3; The above k is a natural number above 2; After restarting the writing sequence and before starting the k+1 verification operation, supply the word line with the verification voltage corresponding to the k verification operation of the nth writing cycle of the writing sequence Or a higher voltage. Such as the semiconductor memory device of any one of claims 1 to 3, which has: The bit line is electrically connected to the aforementioned memory transistor; A sensing transistor, which has a gate electrode electrically connected to the above-mentioned bit line; and The first transistor is electrically connected to the aforementioned sensing transistor; and In the first sequence of the verification operation, the voltage supplied to the gate electrode of the first transistor rises, and in the second sequence later, the voltage supplied to the gate electrode of the first transistor falls; After restarting the writing sequence and before starting the k+1 verification operation, at the third timing, the voltage supplied to the gate electrode of the first transistor rises, and at the fourth timing later than The voltage to the gate electrode of the above-mentioned first transistor drops.

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