SG10202006754WA - Interface circuit, memory device, storage device, and method of operating the memory device - Google Patents

Interface circuit, memory device, storage device, and method of operating the memory device

Info

Publication number
SG10202006754WA
SG10202006754WA SG10202006754WA SG10202006754WA SG10202006754WA SG 10202006754W A SG10202006754W A SG 10202006754WA SG 10202006754W A SG10202006754W A SG 10202006754WA SG 10202006754W A SG10202006754W A SG 10202006754WA SG 10202006754W A SG10202006754W A SG 10202006754WA
Authority
SG
Singapore
Prior art keywords
memory device
operating
interface circuit
storage device
storage
Prior art date
Application number
SG10202006754WA
Inventor
Na Daehoon
Lee Jangwoo
Ihm Jeongdon
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10202006754WA publication Critical patent/SG10202006754WA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
SG10202006754WA 2019-09-11 2020-07-15 Interface circuit, memory device, storage device, and method of operating the memory device SG10202006754WA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190113012A KR20210031266A (en) 2019-09-11 2019-09-11 Interface circuit, memory device, storage device and operation method of the memory device

Publications (1)

Publication Number Publication Date
SG10202006754WA true SG10202006754WA (en) 2021-04-29

Family

ID=71620347

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10202006754WA SG10202006754WA (en) 2019-09-11 2020-07-15 Interface circuit, memory device, storage device, and method of operating the memory device

Country Status (6)

Country Link
US (2) US11199975B2 (en)
EP (1) EP3792775A1 (en)
JP (1) JP2021043975A (en)
KR (1) KR20210031266A (en)
CN (1) CN112486866A (en)
SG (1) SG10202006754WA (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220001370A (en) * 2020-06-29 2022-01-05 에스케이하이닉스 주식회사 Electronic device for executing active operation
CN114550775A (en) * 2020-11-24 2022-05-27 瑞昱半导体股份有限公司 Memory controller and control method thereof
US20230052489A1 (en) * 2021-08-13 2023-02-16 Micron Technology, Inc. Die location detection for grouped memory dies

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4716545A (en) * 1985-03-19 1987-12-29 Wang Laboratories, Inc. Memory means with multiple word read and single word write
US5136582A (en) * 1990-05-29 1992-08-04 Advanced Micro Devices, Inc. Memory management system and method for network controller
JP2003036681A (en) 2001-07-23 2003-02-07 Hitachi Ltd Non-volatile memory device
US6778436B2 (en) 2001-10-10 2004-08-17 Fong Piau Apparatus and architecture for a compact flash memory controller
WO2007116486A1 (en) 2006-03-31 2007-10-18 Fujitsu Limited Memory apparatus, control method thereof, control program thereof, memory card, circuit board and electronic device
KR100851545B1 (en) 2006-12-29 2008-08-11 삼성전자주식회사 Nand flash memory having c/a pin and flash memory system including that
KR101893176B1 (en) 2010-12-03 2018-08-29 삼성전자주식회사 Multi- chip memory device and control method thereof
WO2012109677A2 (en) * 2011-02-11 2012-08-16 Fusion-Io, Inc. Apparatus, system, and method for managing operations for data storage media
US20120239874A1 (en) * 2011-03-02 2012-09-20 Netlist, Inc. Method and system for resolving interoperability of multiple types of dual in-line memory modules
US9645758B2 (en) * 2011-07-22 2017-05-09 Sandisk Technologies Llc Apparatus, system, and method for indexing data of an append-only, log-based structure
US9335952B2 (en) 2013-03-01 2016-05-10 Ocz Storage Solutions, Inc. System and method for polling the status of memory devices
US9684622B2 (en) * 2014-06-09 2017-06-20 Micron Technology, Inc. Method and apparatus for controlling access to a common bus by multiple components
US9933950B2 (en) * 2015-01-16 2018-04-03 Sandisk Technologies Llc Storage operation interrupt
US9921763B1 (en) 2015-06-25 2018-03-20 Crossbar, Inc. Multi-bank non-volatile memory apparatus with high-speed bus
US10025536B2 (en) * 2016-02-10 2018-07-17 Sandisk Technologies Llc Memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment
US11403241B2 (en) * 2017-10-02 2022-08-02 Micron Technology, Inc. Communicating data with stacked memory dies
TWI684860B (en) * 2018-10-15 2020-02-11 慧榮科技股份有限公司 Method for performing read acceleration, and associated data storage device and controller thereof

Also Published As

Publication number Publication date
CN112486866A (en) 2021-03-12
KR20210031266A (en) 2021-03-19
US11199975B2 (en) 2021-12-14
US20220083237A1 (en) 2022-03-17
EP3792775A1 (en) 2021-03-17
US11960728B2 (en) 2024-04-16
JP2021043975A (en) 2021-03-18
US20210072902A1 (en) 2021-03-11

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