SG10201909446PA - Semiconductor memory device and method for forming the same - Google Patents

Semiconductor memory device and method for forming the same

Info

Publication number
SG10201909446PA
SG10201909446PA SG10201909446PA SG10201909446PA SG10201909446PA SG 10201909446P A SG10201909446P A SG 10201909446PA SG 10201909446P A SG10201909446P A SG 10201909446PA SG 10201909446P A SG10201909446P A SG 10201909446PA SG 10201909446P A SG10201909446P A SG 10201909446PA
Authority
SG
Singapore
Prior art keywords
forming
same
memory device
semiconductor memory
semiconductor
Prior art date
Application number
SG10201909446PA
Inventor
Oh Sung-Lae
Kim Dong-Hyuk
Park Tae-Sung
Jung Soo-Nam
Choi Chang-Woon
Original Assignee
Sk Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sk Hynix Inc filed Critical Sk Hynix Inc
Publication of SG10201909446PA publication Critical patent/SG10201909446PA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Geometry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
SG10201909446PA 2018-11-19 2019-10-09 Semiconductor memory device and method for forming the same SG10201909446PA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020180142264A KR102635678B1 (en) 2018-11-19 2018-11-19 Semiconductor memory device and method for forming the same

Publications (1)

Publication Number Publication Date
SG10201909446PA true SG10201909446PA (en) 2020-06-29

Family

ID=70728383

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201909446PA SG10201909446PA (en) 2018-11-19 2019-10-09 Semiconductor memory device and method for forming the same

Country Status (4)

Country Link
US (2) US11063061B2 (en)
KR (1) KR102635678B1 (en)
CN (1) CN111199980B (en)
SG (1) SG10201909446PA (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020155492A (en) * 2019-03-18 2020-09-24 キオクシア株式会社 Semiconductor storage and manufacturing method of semiconductor storage
KR102688510B1 (en) * 2019-03-28 2024-07-26 에스케이하이닉스 주식회사 Semiconductor memory device
CN111540747B (en) * 2020-04-27 2021-07-16 长江存储科技有限责任公司 Method for manufacturing 3D memory device
US11917817B2 (en) * 2020-12-17 2024-02-27 Micron Technology, Inc. Microelectronic devices, memory devices, and electronic systems
JP2022126323A (en) * 2021-02-18 2022-08-30 キオクシア株式会社 Semiconductor memory device
US11665894B2 (en) * 2021-03-04 2023-05-30 Micron Technology, Inc. Microelectronic devices, memory devices, and electronic systems
US20230010799A1 (en) * 2021-07-12 2023-01-12 Micron Technology, Inc. Microelectronic devices with active source/drain contacts in trench in symmetrical dual-block structure, and related systems and methods
US11792988B2 (en) 2021-08-09 2023-10-17 Sandisk Technologies Llc Three-dimensional memory device with separated contact regions and methods for forming the same
US11889694B2 (en) 2021-08-09 2024-01-30 Sandisk Technologies Llc Three-dimensional memory device with separated contact regions and methods for forming the same
US11996153B2 (en) 2021-08-09 2024-05-28 Sandisk Technologies Llc Three-dimensional memory device with separated contact regions and methods for forming the same
KR20240022584A (en) * 2021-08-09 2024-02-20 샌디스크 테크놀로지스 엘엘씨 Three-dimensional memory device with separated contact zones and method of forming the same
US20230063178A1 (en) * 2021-08-30 2023-03-02 Micron Technology, Inc. Microelectronic devices including stair step structures, and related electronic systems and methods

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120121177A (en) * 2011-04-26 2012-11-05 에스케이하이닉스 주식회사 Semiconductor memory device and method of manufacturing the same
JP2015026674A (en) * 2013-07-25 2015-02-05 株式会社東芝 Non-volatile memory device and method of manufacturing the same
KR102238951B1 (en) * 2014-07-25 2021-04-12 에스케이하이닉스 주식회사 Semiconductor device with air gap and method for fabricating the same
US9530781B2 (en) * 2014-12-22 2016-12-27 Sandisk Technologies Llc Three dimensional NAND memory having improved connection between source line and in-hole channel material as well as reduced damage to in-hole layers
KR20170014757A (en) * 2015-07-31 2017-02-08 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of the same
KR102487526B1 (en) * 2015-11-06 2023-01-12 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of the same
KR102568886B1 (en) 2015-11-16 2023-08-22 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of the same
KR102649372B1 (en) * 2016-01-08 2024-03-21 삼성전자주식회사 Three dimensional semiconductor memory device
KR102550571B1 (en) * 2016-05-02 2023-07-04 에스케이하이닉스 주식회사 Semiconductor device and method of manufacturing the same
CN107731834B (en) * 2017-08-30 2019-01-01 长江存储科技有限责任公司 A kind of core space layer insulation oxide layer CMP method for 3D NAND

Also Published As

Publication number Publication date
US11063061B2 (en) 2021-07-13
KR102635678B1 (en) 2024-02-14
KR20200057936A (en) 2020-05-27
US20210296362A1 (en) 2021-09-23
CN111199980B (en) 2023-12-26
US11563030B2 (en) 2023-01-24
CN111199980A (en) 2020-05-26
US20200161326A1 (en) 2020-05-21

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