SG10202002136TA - Nonvolatile memory device and method for fabricating the same - Google Patents
Nonvolatile memory device and method for fabricating the sameInfo
- Publication number
- SG10202002136TA SG10202002136TA SG10202002136TA SG10202002136TA SG10202002136TA SG 10202002136T A SG10202002136T A SG 10202002136TA SG 10202002136T A SG10202002136T A SG 10202002136TA SG 10202002136T A SG10202002136T A SG 10202002136TA SG 10202002136T A SG10202002136T A SG 10202002136TA
- Authority
- SG
- Singapore
- Prior art keywords
- fabricating
- same
- memory device
- nonvolatile memory
- nonvolatile
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020190067910A KR20200141213A (en) | 2019-06-10 | 2019-06-10 | Nonvolatile memory device and method for fabricating the same |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10202002136TA true SG10202002136TA (en) | 2021-01-28 |
Family
ID=73651613
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10202002136TA SG10202002136TA (en) | 2019-06-10 | 2020-03-09 | Nonvolatile memory device and method for fabricating the same |
Country Status (4)
Country | Link |
---|---|
US (1) | US11296110B2 (en) |
KR (1) | KR20200141213A (en) |
CN (1) | CN112071854A (en) |
SG (1) | SG10202002136TA (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20210117522A (en) * | 2020-03-19 | 2021-09-29 | 삼성전자주식회사 | Nonvolatile memory device and method for fabricating the same |
KR102556380B1 (en) * | 2021-02-02 | 2023-07-17 | 한양대학교 산학협력단 | 3d flash memory with wider memory cell area |
JP2023046164A (en) * | 2021-09-22 | 2023-04-03 | キオクシア株式会社 | Semiconductor device |
TWI789295B (en) * | 2022-04-27 | 2023-01-01 | 旺宏電子股份有限公司 | Memory device |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010010596A (en) * | 2008-06-30 | 2010-01-14 | Toshiba Corp | Nonvolatile semiconductor storage device and manufacturing method |
JP5086933B2 (en) * | 2008-08-06 | 2012-11-28 | 株式会社東芝 | Driving method of nonvolatile semiconductor memory device |
JP2011023586A (en) | 2009-07-16 | 2011-02-03 | Toshiba Corp | Semiconductor memory device and method of manufacturing the same |
KR101110355B1 (en) | 2010-04-05 | 2012-02-14 | 서울대학교산학협력단 | 3d stacked array having cut-off gate line and fabrication method thereof |
US8437192B2 (en) | 2010-05-21 | 2013-05-07 | Macronix International Co., Ltd. | 3D two bit-per-cell NAND flash memory |
US9349745B2 (en) | 2014-08-25 | 2016-05-24 | Macronix International Co., Ltd. | 3D NAND nonvolatile memory with staggered vertical gates |
US9620514B2 (en) | 2014-09-05 | 2017-04-11 | Sandisk Technologies Llc | 3D semicircular vertical NAND string with self aligned floating gate or charge trap cell memory cells and methods of fabricating and operating the same |
TWI582964B (en) | 2015-12-30 | 2017-05-11 | 旺宏電子股份有限公司 | A memory device and method for fabricating the same |
US9812462B1 (en) | 2016-06-07 | 2017-11-07 | Sandisk Technologies Llc | Memory hole size variation in a 3D stacked memory |
KR20180012640A (en) | 2016-07-27 | 2018-02-06 | 삼성전자주식회사 | Vertical memory device and method of manufacturing the same |
-
2019
- 2019-06-10 KR KR1020190067910A patent/KR20200141213A/en not_active Application Discontinuation
-
2020
- 2020-02-21 US US16/797,884 patent/US11296110B2/en active Active
- 2020-03-09 SG SG10202002136TA patent/SG10202002136TA/en unknown
- 2020-06-09 CN CN202010516756.7A patent/CN112071854A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US11296110B2 (en) | 2022-04-05 |
KR20200141213A (en) | 2020-12-18 |
US20200388633A1 (en) | 2020-12-10 |
CN112071854A (en) | 2020-12-11 |
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