SG10202003517XA - Memory device - Google Patents

Memory device

Info

Publication number
SG10202003517XA
SG10202003517XA SG10202003517XA SG10202003517XA SG10202003517XA SG 10202003517X A SG10202003517X A SG 10202003517XA SG 10202003517X A SG10202003517X A SG 10202003517XA SG 10202003517X A SG10202003517X A SG 10202003517XA SG 10202003517X A SG10202003517X A SG 10202003517XA
Authority
SG
Singapore
Prior art keywords
memory device
memory
Prior art date
Application number
SG10202003517XA
Inventor
Yun Kyunghwa
Kwak Pansuk
Kim Chanho
Kang Dongku
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10202003517XA publication Critical patent/SG10202003517XA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
SG10202003517XA 2019-08-06 2020-04-17 Memory device SG10202003517XA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190095526A KR20210018608A (en) 2019-08-06 2019-08-06 Memory device

Publications (1)

Publication Number Publication Date
SG10202003517XA true SG10202003517XA (en) 2021-03-30

Family

ID=74188452

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10202003517XA SG10202003517XA (en) 2019-08-06 2020-04-17 Memory device

Country Status (6)

Country Link
US (1) US11211391B2 (en)
JP (1) JP2021027329A (en)
KR (1) KR20210018608A (en)
CN (1) CN112349724A (en)
DE (1) DE102020107244A1 (en)
SG (1) SG10202003517XA (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11289500B2 (en) 2019-08-06 2022-03-29 Samsung Electronics Co., Ltd. Memory device
KR20210083545A (en) * 2019-12-27 2021-07-07 삼성전자주식회사 Memory device having cop structure and memory package including the same
KR20220019901A (en) * 2020-08-10 2022-02-18 삼성전자주식회사 Semiconductor device and electronic system including the same
KR20240039855A (en) * 2022-09-20 2024-03-27 삼성전자주식회사 Semiconductor device and electronic system

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3447939B2 (en) 1997-12-10 2003-09-16 株式会社東芝 Nonvolatile semiconductor memory and data reading method
KR100304710B1 (en) * 1999-08-30 2001-11-01 윤종용 Nonovolatile Memory Device Having Bulk Bias Contact Structure in Cell Array Region
KR100849715B1 (en) 2006-11-07 2008-08-01 주식회사 하이닉스반도체 NAND type flash memory device having global page buffer and method for reading data thereof
KR101784999B1 (en) 2011-04-08 2017-11-06 삼성전자주식회사 Nonvolatile memory device and driving method thereof
US9111591B2 (en) 2013-02-22 2015-08-18 Micron Technology, Inc. Interconnections for 3D memory
KR102128469B1 (en) 2013-11-08 2020-06-30 삼성전자주식회사 Semiconductor devices
KR20150139255A (en) 2014-06-03 2015-12-11 에스케이하이닉스 주식회사 Semiconductor device and method of manufacturing the same
US9412749B1 (en) 2014-09-19 2016-08-09 Sandisk Technologies Llc Three dimensional memory device having well contact pillar and method of making thereof
US9202581B1 (en) 2014-09-25 2015-12-01 Macronix International Co., Ltd. Sensing method for a flash memory and memory device therewith
US9818759B2 (en) 2015-12-22 2017-11-14 Sandisk Technologies Llc Through-memory-level via structures for a three-dimensional memory device
US9589978B1 (en) 2016-02-25 2017-03-07 Micron Technology, Inc. Memory devices with stairs in a staircase coupled to tiers of memory cells and to pass transistors directly under the staircase
US9941209B2 (en) 2016-03-11 2018-04-10 Micron Technology, Inc. Conductive structures, systems and devices including conductive structures and related methods
JP2017163114A (en) 2016-03-11 2017-09-14 東芝メモリ株式会社 Semiconductor storage device
KR102618562B1 (en) 2016-05-16 2023-12-27 삼성전자주식회사 semiconductor chip and method of manufacturing the same
KR102607833B1 (en) 2016-05-23 2023-11-30 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of the same
US10396090B2 (en) 2016-05-23 2019-08-27 SK Hynix Inc. Semiconductor device and manufacturing method thereof
US10256248B2 (en) 2016-06-07 2019-04-09 Sandisk Technologies Llc Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof
US10276585B2 (en) 2016-08-12 2019-04-30 Toshiba Memory Corporation Semiconductor memory device
KR102667878B1 (en) * 2016-09-06 2024-05-23 삼성전자주식회사 Semiconductor memory device and method of fabricating the same
KR102671937B1 (en) 2017-01-10 2024-06-05 에스케이하이닉스 주식회사 Nonvolatile memory device including multi plane
US10115440B2 (en) 2017-01-10 2018-10-30 Sandisk Technologies Llc Word line contact regions for three-dimensional non-volatile memory
US9953992B1 (en) 2017-06-01 2018-04-24 Sandisk Technologies Llc Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof
KR102253836B1 (en) 2017-07-11 2021-05-20 삼성전자주식회사 Page buffer and nonvolatile memory device including the same
KR102633483B1 (en) * 2018-02-23 2024-02-05 삼성전자주식회사 Semiconductor Memory Device

Also Published As

Publication number Publication date
US20210043639A1 (en) 2021-02-11
JP2021027329A (en) 2021-02-22
KR20210018608A (en) 2021-02-18
CN112349724A (en) 2021-02-09
US11211391B2 (en) 2021-12-28
DE102020107244A1 (en) 2021-02-11

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