SG10202003945RA - Vertical memory devices - Google Patents

Vertical memory devices

Info

Publication number
SG10202003945RA
SG10202003945RA SG10202003945RA SG10202003945RA SG10202003945RA SG 10202003945R A SG10202003945R A SG 10202003945RA SG 10202003945R A SG10202003945R A SG 10202003945RA SG 10202003945R A SG10202003945R A SG 10202003945RA SG 10202003945R A SG10202003945R A SG 10202003945RA
Authority
SG
Singapore
Prior art keywords
memory devices
vertical memory
vertical
devices
memory
Prior art date
Application number
SG10202003945RA
Inventor
Baek Seokcheon
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10202003945RA publication Critical patent/SG10202003945RA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
SG10202003945RA 2019-06-04 2020-04-29 Vertical memory devices SG10202003945RA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190066135A KR20200139526A (en) 2019-06-04 2019-06-04 Vertical memory devices

Publications (1)

Publication Number Publication Date
SG10202003945RA true SG10202003945RA (en) 2021-01-28

Family

ID=73579704

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10202003945RA SG10202003945RA (en) 2019-06-04 2020-04-29 Vertical memory devices

Country Status (4)

Country Link
US (1) US11610908B2 (en)
KR (1) KR20200139526A (en)
CN (1) CN112038352A (en)
SG (1) SG10202003945RA (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102640175B1 (en) * 2019-11-18 2024-02-23 삼성전자주식회사 Semiconductor devices
US11637125B2 (en) * 2020-10-20 2023-04-25 Macronix International Co., Ltd. Memory device
KR20220059600A (en) * 2020-11-03 2022-05-10 삼성전자주식회사 Semiconductor device, method of manufacturing the same, and massive data storage system including the same

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013055136A (en) 2011-09-01 2013-03-21 Toshiba Corp Nonvolatile semiconductor memory device and method of manufacturing the same
KR20150073251A (en) 2013-12-20 2015-07-01 에스케이하이닉스 주식회사 Semiconductor device and method of manufacturing the same
KR102168189B1 (en) 2014-03-07 2020-10-21 삼성전자주식회사 Three-dimensional semiconductor device and fabricating method thereof
US10008510B2 (en) * 2015-03-31 2018-06-26 Toshiba Memory Corporation Semiconductor memory device
US9698066B2 (en) * 2015-10-08 2017-07-04 Samsung Electronics Co., Ltd. Semiconductor chips having defect detecting circuits
US9698151B2 (en) * 2015-10-08 2017-07-04 Samsung Electronics Co., Ltd. Vertical memory devices
KR102424720B1 (en) 2015-10-22 2022-07-25 삼성전자주식회사 Vertical memory devices and methods of manufacturing the same
KR102497116B1 (en) 2015-12-30 2023-02-07 에스케이하이닉스 주식회사 Electronic device and method for fabricating the same
KR102581038B1 (en) 2016-03-15 2023-09-22 에스케이하이닉스 주식회사 Semiconductor device
KR20180019807A (en) 2016-08-16 2018-02-27 삼성전자주식회사 Semiconductor devices
US10134757B2 (en) 2016-11-07 2018-11-20 Asm Ip Holding B.V. Method of processing a substrate and a device manufactured by using the method
KR20180068587A (en) 2016-12-14 2018-06-22 삼성전자주식회사 vertical type semiconductor device
US20180269226A1 (en) 2017-03-16 2018-09-20 Toshiba Memory Corporation Semiconductor memory device and method for manufacturing same
US10847529B2 (en) 2017-04-13 2020-11-24 Asm Ip Holding B.V. Substrate processing method and device manufactured by the same
KR20180122847A (en) * 2017-05-04 2018-11-14 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method thereof
WO2019028136A1 (en) 2017-08-04 2019-02-07 Lam Research Corporation Selective deposition of sin on horizontal surfaces

Also Published As

Publication number Publication date
CN112038352A (en) 2020-12-04
KR20200139526A (en) 2020-12-14
US11610908B2 (en) 2023-03-21
US20200388624A1 (en) 2020-12-10

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