SG10201909445RA - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
SG10201909445RA
SG10201909445RA SG10201909445RA SG10201909445RA SG10201909445RA SG 10201909445R A SG10201909445R A SG 10201909445RA SG 10201909445R A SG10201909445R A SG 10201909445RA SG 10201909445R A SG10201909445R A SG 10201909445RA SG 10201909445R A SG10201909445R A SG 10201909445RA
Authority
SG
Singapore
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Application number
SG10201909445RA
Inventor
Oh Sung-Lae
Original Assignee
Sk Hynix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sk Hynix Inc filed Critical Sk Hynix Inc
Publication of SG10201909445RA publication Critical patent/SG10201909445RA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
SG10201909445RA 2019-01-16 2019-10-09 Semiconductor memory device SG10201909445RA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190005521A KR102648581B1 (en) 2019-01-16 2019-01-16 Semiconductor memory device

Publications (1)

Publication Number Publication Date
SG10201909445RA true SG10201909445RA (en) 2020-08-28

Family

ID=71516857

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201909445RA SG10201909445RA (en) 2019-01-16 2019-10-09 Semiconductor memory device

Country Status (4)

Country Link
US (1) US10930587B2 (en)
KR (1) KR102648581B1 (en)
CN (1) CN111446257B (en)
SG (1) SG10201909445RA (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3951873A4 (en) 2019-03-29 2023-07-05 Industry-University Cooperation Foundation Hanyang University Ferroelectric material-based three-dimensional flash memory, and manufacture therefor
KR20220010874A (en) * 2020-07-20 2022-01-27 에스케이하이닉스 주식회사 Three dimensional memory device and method for fabricating threrof
KR102424408B1 (en) * 2020-07-24 2022-07-22 한양대학교 산학협력단 Three dimension flash memory with efficient word line connection structure
WO2022019522A1 (en) * 2020-07-24 2022-01-27 한양대학교 산학협력단 Three-dimensional flash memory having improved integration density
KR20220083115A (en) 2020-12-11 2022-06-20 에스케이하이닉스 주식회사 Three dimensional memory device and fabricating method thereof

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100689831B1 (en) * 2005-06-20 2007-03-08 삼성전자주식회사 Phase change memory cells having a cell diode and a bottom electrode self-aligned with each other and methods of fabricating the same
JP2011054886A (en) * 2009-09-04 2011-03-17 Toshiba Corp Nonvolatile semiconductor memory and method of manufacturing the same
KR101738533B1 (en) * 2010-05-24 2017-05-23 삼성전자 주식회사 Stacked memory devices and method of manufacturing the same
KR101738103B1 (en) * 2010-09-10 2017-05-22 삼성전자주식회사 Therr dimensional semiconductor memory devices
KR101721117B1 (en) 2011-03-15 2017-03-29 삼성전자 주식회사 Method for fabricating of semiconductor device
JP2013131580A (en) * 2011-12-20 2013-07-04 Toshiba Corp Semiconductor device and manufacturing method therefor
US9070447B2 (en) * 2013-09-26 2015-06-30 Macronix International Co., Ltd. Contact structure and forming method
KR102094470B1 (en) 2014-04-08 2020-03-27 삼성전자주식회사 Semiconductor Device and Method of Fabricating the Same
KR20160128127A (en) 2015-04-28 2016-11-07 에스케이하이닉스 주식회사 Semiconductor device and manufaturing method thereof
KR102568886B1 (en) * 2015-11-16 2023-08-22 에스케이하이닉스 주식회사 Semiconductor device and manufacturing method of the same
KR102650535B1 (en) * 2016-01-18 2024-03-25 삼성전자주식회사 Three dimensional semiconductor memory device
JP2018037513A (en) * 2016-08-31 2018-03-08 東芝メモリ株式会社 Semiconductor device
KR20180066745A (en) * 2016-12-09 2018-06-19 삼성전자주식회사 Semiconductor memory device
KR20180096878A (en) * 2017-02-21 2018-08-30 삼성전자주식회사 Three dimensional semiconductor memory device and method for manufacturing the same

Also Published As

Publication number Publication date
KR102648581B1 (en) 2024-03-18
CN111446257B (en) 2023-06-09
CN111446257A (en) 2020-07-24
KR20200088988A (en) 2020-07-24
US10930587B2 (en) 2021-02-23
US20200227347A1 (en) 2020-07-16

Similar Documents

Publication Publication Date Title
EP3673484A4 (en) Semiconductor memory device
SG11201802573UA (en) Semiconductor memory device
SG10202007886XA (en) Three-Dimensional Semiconductor Memory Device
SG10202004453RA (en) Three-Dimensional Semiconductor Memory Device
SG10201905158TA (en) Semiconductor package
SG10202008178YA (en) Semiconductor Memory Devices
SG10202001607VA (en) Semiconductor device
SG10202004477SA (en) Three-dimensional semiconductor memory device
SG10201905122TA (en) Semiconductor memory device
SG10201909445RA (en) Semiconductor memory device
SG10201905607UA (en) Semiconductor device
SG10201905606YA (en) Semiconductor device
SG11202011551QA (en) Memory device
SG10201911466SA (en) Semiconductor memory devices
SG11202102625VA (en) Semiconductor memory device
SG10202003517XA (en) Memory device
SG10201902032WA (en) Semiconductor Package
GB201814693D0 (en) Semiconductor devices
SG10202006115RA (en) Vertical memory device
SG11202008495TA (en) Semiconductor memory device
SG10201906732VA (en) Three dimensional semiconductor memory devices
SG11202013103YA (en) Semiconductor memory device
SG10201906019QA (en) Semiconductor Device
IL269012A (en) Nonvolatile semiconductor storage device
EP4084064A4 (en) Semiconductor device