SG11201802573UA - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- SG11201802573UA SG11201802573UA SG11201802573UA SG11201802573UA SG11201802573UA SG 11201802573U A SG11201802573U A SG 11201802573UA SG 11201802573U A SG11201802573U A SG 11201802573UA SG 11201802573U A SG11201802573U A SG 11201802573UA SG 11201802573U A SG11201802573U A SG 11201802573UA
- Authority
- SG
- Singapore
- Prior art keywords
- memory device
- semiconductor memory
- semiconductor
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2016/050888 WO2017122302A1 (en) | 2016-01-13 | 2016-01-13 | Semiconductor storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201802573UA true SG11201802573UA (en) | 2018-04-27 |
Family
ID=59311761
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201802573UA SG11201802573UA (en) | 2016-01-13 | 2016-01-13 | Semiconductor memory device |
Country Status (7)
Country | Link |
---|---|
US (3) | US10431273B2 (en) |
EP (1) | EP3404697A4 (en) |
JP (1) | JP6571208B2 (en) |
CN (2) | CN108055873B (en) |
SG (1) | SG11201802573UA (en) |
TW (3) | TWI642112B (en) |
WO (1) | WO2017122302A1 (en) |
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JP5814867B2 (en) * | 2012-06-27 | 2015-11-17 | 株式会社東芝 | Semiconductor memory device |
WO2017122302A1 (en) * | 2016-01-13 | 2017-07-20 | 東芝メモリ株式会社 | Semiconductor storage device |
KR102462503B1 (en) * | 2017-11-27 | 2022-11-02 | 삼성전자주식회사 | Nonvolatile memory device having vertical structure and memory system including the same |
JP2019161094A (en) * | 2018-03-15 | 2019-09-19 | 東芝メモリ株式会社 | Semi-conductor memory |
JP2020013889A (en) * | 2018-07-18 | 2020-01-23 | キオクシア株式会社 | Semiconductor storage device |
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JP2020047642A (en) * | 2018-09-14 | 2020-03-26 | キオクシア株式会社 | Semiconductor storage device |
JP2020047348A (en) * | 2018-09-19 | 2020-03-26 | キオクシア株式会社 | Semiconductor storage device and control method thereof |
JP2020047806A (en) * | 2018-09-20 | 2020-03-26 | キオクシア株式会社 | Semiconductor storage |
JP2020065022A (en) | 2018-10-19 | 2020-04-23 | キオクシア株式会社 | Semiconductor device and semiconductor storage device |
JP2020092141A (en) * | 2018-12-04 | 2020-06-11 | キオクシア株式会社 | Semiconductor memory |
JP2020092168A (en) * | 2018-12-05 | 2020-06-11 | キオクシア株式会社 | Semiconductor memory |
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KR20200072883A (en) * | 2018-12-13 | 2020-06-23 | 에스케이하이닉스 주식회사 | Semiconductor apparatus |
CN111354739A (en) * | 2018-12-21 | 2020-06-30 | 芯恩(青岛)集成电路有限公司 | Three-dimensional junction semiconductor memory device and manufacturing method thereof |
JP2020102290A (en) * | 2018-12-21 | 2020-07-02 | キオクシア株式会社 | Semiconductor storage device |
JP2020126943A (en) * | 2019-02-05 | 2020-08-20 | キオクシア株式会社 | Semiconductor storage device |
JP2020136426A (en) | 2019-02-18 | 2020-08-31 | キオクシア株式会社 | Semiconductor chip |
JP2020145218A (en) * | 2019-03-04 | 2020-09-10 | キオクシア株式会社 | Semiconductor storage device and method for manufacturing semiconductor storage device |
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JP2020155664A (en) * | 2019-03-22 | 2020-09-24 | キオクシア株式会社 | Semiconductor storage device |
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JP7414411B2 (en) * | 2019-06-14 | 2024-01-16 | キオクシア株式会社 | semiconductor storage device |
JP2021048353A (en) | 2019-09-20 | 2021-03-25 | キオクシア株式会社 | Semiconductor memory device |
JP2021052084A (en) * | 2019-09-25 | 2021-04-01 | キオクシア株式会社 | Semiconductor storage device |
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CN112634966B (en) | 2019-10-23 | 2022-08-12 | 长江存储科技有限责任公司 | Method of programming a memory device and related memory device |
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-
2016
- 2016-01-13 WO PCT/JP2016/050888 patent/WO2017122302A1/en active Application Filing
- 2016-01-13 EP EP16884905.7A patent/EP3404697A4/en active Pending
- 2016-01-13 SG SG11201802573UA patent/SG11201802573UA/en unknown
- 2016-01-13 CN CN201680052188.1A patent/CN108055873B/en active Active
- 2016-01-13 CN CN202110395832.8A patent/CN113113055A/en active Pending
- 2016-01-13 JP JP2017561446A patent/JP6571208B2/en active Active
- 2016-03-04 TW TW105106806A patent/TWI642112B/en active
- 2016-03-04 TW TW107128961A patent/TWI692037B/en active
- 2016-03-04 TW TW109108815A patent/TWI776132B/en active
-
2018
- 2018-04-12 US US15/951,314 patent/US10431273B2/en active Active
-
2019
- 2019-08-20 US US16/546,064 patent/US10957368B2/en active Active
-
2021
- 2021-02-12 US US17/175,045 patent/US11443787B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
TWI776132B (en) | 2022-09-01 |
US20210166744A1 (en) | 2021-06-03 |
EP3404697A1 (en) | 2018-11-21 |
WO2017122302A1 (en) | 2017-07-20 |
TW201841264A (en) | 2018-11-16 |
US10957368B2 (en) | 2021-03-23 |
US20180233185A1 (en) | 2018-08-16 |
TWI642112B (en) | 2018-11-21 |
TWI692037B (en) | 2020-04-21 |
US10431273B2 (en) | 2019-10-01 |
CN108055873B (en) | 2021-04-30 |
US20190371382A1 (en) | 2019-12-05 |
CN108055873A (en) | 2018-05-18 |
TW201738965A (en) | 2017-11-01 |
TW202042309A (en) | 2020-11-16 |
EP3404697A4 (en) | 2019-12-25 |
US11443787B2 (en) | 2022-09-13 |
JP6571208B2 (en) | 2019-09-04 |
CN113113055A (en) | 2021-07-13 |
JPWO2017122302A1 (en) | 2018-07-12 |
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