WO2022077318A1

WO2022077318A1 - Array and contact architecture for four stack three dimensional cross point memory

Info

Publication number: WO2022077318A1
Application number: PCT/CN2020/121071
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2020-10-15
Filing date: 2020-10-15
Publication date: 2022-04-21
Also published as: CN112385040B; CN112385040A; CN114005829A

Abstract

An architecture for a three dimensional cross point memory cell includes a plurality of layers of planar and mutually parallel bit tiles, each of the bit tiles including bit lines extending in a bit line direction. The architecture further includes decoders to which the bit tiles are electrically connected by contacts. Each layer of bit tiles has a tile per decoder ratio defined as a ratio of bit tiles in the layer to a number of decoders to which at least one tile in the layer is electrically connected. At least one layer of bit tiles has a different tile per decoder ratio greater than 1: 1.

Description

AN ARRAY AND CONTACT ARCHITECTURE FOR FOUR STACK THREE DIMENSIONAL CROSS POINT MEMORY

TECHNICAL FIELD

The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to increasing the density of memory cells in three-dimensional cross-point memories.

BACKGROUND OF THE INVENTION

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells by layering multiple planes of memory cells in a single device.

BRIEF SUMMARY OF THE INVENTION

In accordance with an aspect, an architecture for a three dimensional cross point memory cell includes a plurality of layers of planar and mutually parallel bit tiles, each of the bit tiles including bit lines extending in a bit line direction. The architecture further includes decoders to which the bit tiles are electrically connected by contacts. Each layer of bit tiles has a tile per decoder ratio defined as a ratio of bit tiles in the layer to a number of decoders to which at least one tile in the layer is electrically connected. At least one layer of bit tiles has a different tile per decoder ratio greater than 1: 1.

In some arrangements, at least one layer of bit tiles has a different tile per decoder ratio than another layer of bit tiles.

In some arrangements, at least one layer of bit tiles has a tile per decoder ratio of 2: 1.

In some arrangements, the at least one layer of bit tiles having a tile per decoder ratio of 2: 1 includes bit tiles electrically connected to a same decoder as one other bit tile in the same layer.

In some arrangements, at least one layer of bit tiles has a tile per decoder ratio of 4: 1.

In some arrangements, the at least one layer of bite tiles having a tile per decoder ratio of 4: 1 includes bit tiles electrically connected to a same decoder as three other bit tiles in the same layer.

In some arrangements, the plurality of layers of bit tiles includes a first layer, an intermediate layer nearer to the decoders than the first layer and having a greater tile per decoder ratio than the first layer, and an outer layer nearer to the decoders than the intermediate layer and having a greater tile per decoder ratio than the intermediate layer.

In some arrangements, the plurality of layers of bit tiles further includes a second layer further from the decoders than the intermediate layer and the outer layer and having a same tile per decoder ratio as the first layer.

In some arrangements, the bit tiles in the intermediate layer are shorter in the bit line direction than the tiles in the first layer and the bit tiles in the outer layer are shorter in the bit line direction than the tiles in the intermediate layer.

In accordance with another aspect, an array and contact architecture for three dimensional cross point memory cell includes a plurality of layers of planar and mutually parallel bit tiles, each of the bit tiles including bit lines extending in a bit line direction. Bit tiles in at least one layer of bit tiles are shorter in the bit line direction than bit tiles in another layer of bit tiles.

In some arrangements, the architecture includes decoders and the plurality of bit tiles includes a first layer, an intermediate layer nearer to the decoders and including bit tiles that are shorter in the bit line direction than bit tiles in the first layer, and an outer layer nearer to the decoders than the intermediate layer and including bit tiles that are shorter in the bit line direction than the bit tiles in the intermediate layer.

In some arrangements, each layer of bit tiles has a tile per decoder ratio defined as a ratio of bit tiles in the layer to a number of decoders to which at least one tile in the layer is electrically connected, and the intermediate layer has a greater tile per decoder ratio than the first layer.

In some arrangements, the outer layer has a greater tile per decoder ratio than the intermediate layer.

In some arrangements, the plurality of layers of bit tiles further includes a second layer further from the decoders than the intermediate layer and the outer layer and having bit tiles of a same length in the bit line direction as the bit tiles in the first layer.

In some arrangements, each layer of bit tiles has a tile per decoder ratio defined as a ratio of bit tiles in the layer to a number of decoders to which at least one tile in the layer is electrically connected. The second layer has a same tile per decoder ratio as the first layer, the intermediate layer has a greater tile per decoder ratio than the first layer, and the outer layer has a greater tile per decoder ratio than the intermediate layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity. However, the aspects of the present disclosure are not intended to be limited to the specific terms used.

FIG. 1 is an isometric view of a section of a prior three-dimensional cross-point memory.

FIG. 2 is a plan view of a section of the prior three-dimensional cross-point memory shown in FIG. 1.

FIG. 3 is a cross-sectional side view of a section of the prior three-dimensional cross-point memory shown in FIGS. 1 and 2.

FIG. 4 is a cross-sectional side view of a section of three-dimensional cross-point memory according to an embodiment.

DETAILED DESCRIPTION

The present technology is applied in the field of three-dimensional crosspoint memory. A generalized example of a three-dimensional (3D) memory is shown in Fig. 1. In particular, Fig. 1 is an isometric view of a section of three-dimensional crosspoint memory 10. The section includes a first bit tile 14 and a second bit tile 18 extending below first bit tile 18. The first bit tile 14 and second bit tile 18 are both planar and mutually parallel, and each includes multiple bit lines 22 therethrough. The lines 22 are also mutually parallel and extend in a bit line direction 18.

Interleaved with the

bit tiles

14, 18, are a first word tile 26 extending between the first bit tile 14 and second bit tile 18 and a second word tile 30 extending below the second bit tile 18. The illustrated interleaving is merely exemplary, and in other examples the first word tile 26 may extend above the first bit tile 14 while the second word tile 30 extends between the first bit tile 14 and second bit tile 18. The

word tiles

26, 30 are also planar and parallel to the

bit tiles

14, 18. The

word tiles

26, 30 each include multiple word lines 34 extending therethrough in a word direction Z that is perpendicular to the bit direction Y.

The illustrated section of memory 10 includes three layers of memory cells 40. A memory cell 40 may exist between a

bit tile

14, 18 and a

word tile

26, 30 wherever a bit line 22 and word line 34 intersect from the perspective of a height direction Y. Memory density per unit area on the X-Y plane is therefore a function of a number of bit tiles and word tiles that can be alternatingly interleaved at a given location.

In order to selectively activate the word lines 34 and bit lines 22, the memory includes bit line decoders 42 and word line decoders 46 at a bottom layer of the memory architecture. The bit line decoders 42 and word line decoders 46 are respectively coupled to the bit lines 22 and word lines 34 by contacts 38 and are used to decode bit line and word line addresses such that a particular bit line 22 or word line 34 is activated when it is addressed.

Bit tiles

14, 18 and

word tiles

26, 30 are each illustrated with broken lines to indicate that contacts 38 are located at or near midpoints of the

bit tiles

14, 18 in the bit direction X and are located at or near midpoints of the word tiles 34 in the word direction Z. It should further be understood that the illustrated numbers of bit lines 22 per

bit tile

14, 18 and word lines 34 per

word tile

26, 30 are exemplary, and more or fewer lines per tile may be used. The positioning of the

decoders

42, 46 and contacts 38 are discussed further in connection with FIG. 2.

FIG. 2 schematically illustrates the section of memory 10 from the perspective of the height direction Y, showing only bit lines 22 and word lines 34 corresponding to the first and

second bit tiles

14, 18 and the first word tile 26. As contacts 38 extend vertically to the bottom layer of the memory architecture, the contacts 38 associate with each tile define regions, indicated by dashed lines that other tiles cannot pass beneath. This is also illustrated in FIG. 3, which schematically illustrates a cross-section of first bit tiles 14 and second bit tiles 18 on the X-Y plane. Such contact regions therefore hinder interleaving of tiles. When present in a repeating pattern, the contact regions limit the number of layers of memory cells achievable across a memory device. For example, where bit tiles 14, 18 of approximately equal length in the bit direction X and centered contacts 38 are used, only two layers of bit tiles may be used at a given location along the bit direction X on a given X-Y plane.

FIG. 4 schematically illustrates a cross-section of memory according to an embodiment along the X-Y plane. As shown, the memory includes third bit tiles 50 extending below the second bit tiles 18 and fourth bit tiles 54 extending below the third bit tiles 50. Third bit tiles 50 are shorter in the bit direction X than the first and

second bit tiles

14, 18, enabling the third bit tiles 50 to fit between contacts 38 associated with the first and

second bit tiles

14, 18. Similarly, fourth bit tiles 54 are shorter in the bit direction X than third bit tiles 50, enabling fourth bit tiles 54 to fit between contacts 38 associated with the first, second, and

third bit tiles

14, 18, 50. The architecture of FIG. 4 thereby enables up to four layers of bit tiles to be used at a given location along the bit direction X on the illustrated X-Y plane. The greater number of layers of bit tiles enables a corresponding increase in the number of layers of memory cells 40, thereby increasing a possible memory density per unit area on the X-Z plane. Despite the differing dimensions of the third bit tiles 50 and fourth bit tiles 54, in the illustrated example the contactors 38 connect to respective third bit tiles 50 and fourth bit tiles 54 at the center of the tiles along the X direction.

Bridges 56 join the contacts 38 associated with the third bit tiles 50 and fourth bit tiles 54 at a bottom layer of the memory architecture such that multiple third bit tiles 50 are contacted to a single bit line decoder 42, and multiple fourth bit tiles 54 are contacted to a single bit line decoder 42. In the illustrated example, bridges 56 join contactors 38 associated with two adjacent third bit tiles 50, such that each third bit tile 50 shares a bit line decoder 42 with another third bit tile 50. Similarly, bridges 56 join contactors 38 associated with four adjacent fourth bit tiles 54, such that each fourth bit tile 50 shares a decoder with three other fourth bit tile 54. As such, each layer of tiles has a tile per decoder ratio defined as a ratio of a total number of bit tiles in a layer to a total number of decoders electrically connected to bit tiles in that layer. Thus, in a layer with a tile per decoder ratio of 1: 1, and assuming no bit tile is electrically connected to more than one decoder, each bit tile electrically connects to a different decoder. Similarly, in a layer with a tile per decoder ratio of 2: 1, and assuming no bit tile is electrically connected to more than one decoder and the size of decoder sharing groups of tiles in the layer is uniform across the layer, the bit tiles are grouped in pairs of bit tiles that share the same decoder by electrical connection, and each pair of bit tiles electrically connects to a different decoder. Here, a decoder sharing group refers to group of bit tiles that are all electrically connected to the same decoder.

Layers may be assigned layer wide group sizes. In examples where tile arrangements are uniform across a layer, the layer wide group size refers to the number of tiles in each decoder sharing group of tiles in the layer. In examples where decoder sharing group sizes vary within a layer, such as due to variances at the edge of an architecture or manufacturing defects, the layer wide group size instead refers to a statistical mode number of bit tiles in the layer to which any one decoder is electrically connected among a group of all decoders that are electrically connected to bit tiles in the layer. Stated another way, in a layer where decoder sharing group sizes are not uniform, the layer wide group size refers to the statistical mode size of decoder sharing groups of bit tiles in the layer, with each decoder sharing group of bit tiles being one or more bit tiles that share a decoder.

In the illustrated example, a layer including the third bit tiles 50 has a tile per decoder ratio that is greater than tile per decoder ratios of layers including the first bit tiles 14 and second bit tiles 18, and a layer including the fourth bit tiles 54 has a greater tile per decoder ratio than the tile per decoder ratio of the layer including the third bit tiles 50, while the layer including the first bit tiles 14 has an equal tile per decoder ratio to that of the layer including the second bit tiles 18. Particularly, the tile per decoder ratio of the layer including the third bit tiles 50 is twice the tile per decoder ratio of the layers including the first bit tiles 14 and the second bit tiles 18, and the tile per decoder ratio of the layer including the fourth bit tiles 54 is twice the tile per decoder ratio of the layer including the third bit tiles 50. Thus, the layer including the first bit tiles 14 and the layer including the second bit tiles 18 both have a tile per decoder ratio of 1: 1. The layer including the third bit tiles 50 has a tile per decoder ratio of 2: 1, and the layer including the fourth bit tiles 54 has a tile per decoder ratio of 4: 1. Similarly, the layers that include the first bit tiles 14 and the second bit tiles 18 both have layer wide group sizes of 1. The layer including the third bit tiles 50 has a layer wide group size of 2, and the layer including the fourth bit tiles 54 has a layer wide group size of 4. However, it should be understood that the illustrated tile per decoder ratios and layer wide group sizes are merely exemplary, and other tile per decoder ratios are possible according to various applications and embodiments. Moreover, though some examples are arranged such that tile per decoder ratio of a layer will generally be greater for layers of bit tiles nearer to the bit line decoders 42, other tile per decoder ratio gradients are possible. Further, it should be understood that the same or similar approaches of varying tile per decoder ratios as described above with regard to

bit tiles

14, 18, 50, 54 may be applied to

word tiles

26, 30 and word line decoders 46 to enable construction of memory architectures with more layers of word tiles.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

An architecture for a three dimensional memory cell, comprising:

a plurality of layers of planar and mutually parallel bit tiles, each of the bit tiles including bit lines extending in a bit line direction;

decoders to which the bit tiles are electrically connected by contacts; wherein:

each layer of bit tiles has a tile per decoder ratio defined as a ratio of a total number of bit tiles in the layer to a total number of decoders that electrically connect to bit tiles in the layer; and

at least one layer of bit tiles has a tile per decoder ratio greater than 1: 1.
The architecture of claim 1, wherein at least one layer of bit tiles has a different tile per decoder ratio than another layer of bit tiles.
The architecture of claim 1, wherein at least one layer of bit tiles has a tile per decoder ratio of 2: 1.
The architecture of claim 3, wherein the at least one layer of bit tiles having a tile per decoder ratio of 2: 1 includes bit tiles electrically connected to a same decoder as one other bit tile in the same layer.
The architecture of claim 1, wherein at least one layer of bit tiles has a tile per decoder ratio of 4: 1.
The architecture of claim 1, wherein the at least one layer of bite tiles having a tile per decoder ratio of 4: 1 includes bit tiles electrically connected to a same decoder as three other bit tiles in the same layer.
The architecture of claim 1, wherein the plurality of layers of bit tiles includes:

a first layer;

an intermediate layer nearer to the decoders than the first layer and having a greater tile per decoder ratio than the first layer; and

an outer layer nearer to the decoders than the intermediate layer and having a greater tile per decoder ratio than the intermediate layer.
The architecture of claim 7, wherein the plurality of layers of bit tiles further includes a second layer further from the decoders than the intermediate layer and the outer layer and having a same tile per decoder ratio as the first layer.
The architecture of claim 7, wherein the bit tiles in the intermediate layer are shorter in the bit line direction than the tiles in the first layer and the bit tiles in the outer layer are shorter in the bit line direction than the tiles in the intermediate layer.
An array and contact architecture for three dimensional memory cell, comprising:

a plurality of layers of planar and mutually parallel bit tiles, each of the bit tiles including bit lines extending in a bit line direction;

wherein bit tiles in at least one layer of bit tiles are shorter in the bit line direction than bit tiles in another layer of bit tiles.
The architecture of claim 10, comprising decoders and wherein the plurality of bit tiles includes:

a first layer;

an intermediate layer nearer to the decoders and including bit tiles that are shorter in the bit line direction than bit tiles in the first layer; and

an outer layer nearer to the decoders than the intermediate layer and including bit tiles that are shorter in the bit line direction than the bit tiles in the intermediate layer.
The architecture of claim 11, wherein each layer of bit tiles has a tile per decoder ratio defined as a ratio of a total number of bit tiles in the layer to a total number of decoders that electrically connect to bit tiles in the layer, and the intermediate layer has a greater tile per decoder ratio than the first layer.
The architecture of claim 12, wherein the outer layer has a greater tile per decoder ratio than the intermediate layer.
The architecture of claim 11, wherein the plurality of layers of bit tiles further includes a second layer further from the decoders than the intermediate layer and the outer layer and having bit tiles of a same length in the bit line direction as the bit tiles in the first layer.
The architecture of claim 14, wherein:

each layer of bit tiles has a tile per decoder ratio defined as a ratio of a total number bit tiles in the layer to a total number of decoders that electrically connect to bit tiles in the layer;

the second layer has a same tile per decoder ratio as the first layer;

the intermediate layer has a greater tile per decoder ratio than the first layer; and

the outer layer has a greater tile per decoder ratio than the intermediate layer.