CN108417560B

CN108417560B - Semiconductor device and method for manufacturing the same

Info

Publication number: CN108417560B
Application number: CN201810154260.2A
Authority: CN
Inventors: 薛光洙; 曹盛纯
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2012-10-05
Filing date: 2013-10-08
Publication date: 2021-11-09
Anticipated expiration: 2033-10-08
Also published as: CN103715176B; CN108417560A; CN103715176A

Abstract

The present disclosure relates to a semiconductor device and a method of manufacturing the same. A semiconductor device includes: a plurality of memory cell strings; a bit line; and an interconnect connecting at least two memory cells in series to the bit line. The memory cell strings can be coupled to corresponding bit lines through corresponding interconnects. Alternate strings of memory cells can be coupled to different bit lines by corresponding different interconnects.

Description

Semiconductor device and method for manufacturing the same

The present application is a divisional application of invention patent application No. 201310464865.9 having application date of 2013, 10, 8 and entitled "semiconductor device".

Technical Field

The present general inventive concept relates to a semiconductor device, and more particularly, to a vertical type memory device.

Background

There is a continuing need to increase the density of semiconductor devices in order to achieve higher performance and lower cost. In particular, the density of semiconductor devices is an important determinant of product pricing. Since the density of the conventional two-dimensional semiconductor memory device is mainly determined by the area occupied by the unit memory cell, the density is significantly affected by the level of fine patterning technology. However, an ultra-high cost apparatus is required to realize such a fine pattern. Therefore, there is still a limit in increasing the density of two-dimensional semiconductor memory devices.

Disclosure of Invention

In one embodiment, a semiconductor device includes: a plurality of vertically stacked memory cell strings, a bit line, and an interconnect serially connecting at least two vertically stacked memory cells to the bit line.

In another embodiment, a portion of the interconnect extends in a first direction and the bit line extends in a second direction.

In some embodiments, the bit lines extend substantially parallel to the interconnects.

In one embodiment, the at least two memory cell strings are arranged in the second direction and offset from the bit line in the first direction, and the portion of the interconnect protrudes in the first direction.

In another embodiment, the bit line, the interconnect, and the at least two memory cell strings are referred to as a first bit line, a first interconnect, and a first group of at least two memory cell strings, and the semiconductor device further includes: a second bit line, and a second interconnect serially connecting a second set of at least two memory cells to the second bit line.

In one embodiment, a portion of the first interconnect protrudes in a first direction, and the second interconnect protrudes in a direction opposite to the first direction.

According to one aspect of the inventive concept, a method comprises: forming a plurality of memory cell strings; coupling an interconnect to at least two of the strings of storage cells; and coupling a bit line to the interconnect.

According to another aspect of the inventive concept, a method of manufacturing a semiconductor device includes: forming a buffer dielectric layer over a semiconductor substrate; repeatedly forming a stack of a sacrificial layer and an insulating layer over the buffer dielectric layer; forming a vertical pillar extending through the stack of sacrificial layers and insulating layers to connect to the semiconductor substrate; forming a separation region by patterning the buffer dielectric layer, the sacrificial layer and the insulating layer to expose a portion of the substrate; removing the patterned sacrificial layer to form a recessed region exposing a portion of the sidewalls of the vertical pillars; forming an information storage element in the recessed area; forming a conductive layer on the information storage element within the recessed area, thereby forming a memory cell string including first and second string selection lines, the first and second string selection lines being spaced apart from each other; forming a first contact on the vertical pillar; forming a sub-interconnect on the first contact to interconnect the vertical pillar with the first and second string selection lines; forming a second contact on the first and second sub-interconnects; and forming a bit line on the second contact, wherein the first sub-interconnect and the second sub-interconnect are connected to different adjacent bit lines through the second contact.

Drawings

The inventive concept will become more apparent in light of the attached drawings and detailed description thereof. The embodiments depicted therein are provided by way of example, and not by way of limitation, in which like reference numerals refer to the same or similar elements. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the various aspects of the inventive concepts.

FIG. 1 is a block diagram of a memory device according to various embodiments of the present inventive concept;

FIG. 2 is a block diagram illustrating an example of the memory cell array of FIG. 1;

fig. 3 is a perspective view of a memory block of a vertical type memory device according to a first embodiment of the inventive concept;

fig. 4A to 4I are enlarged views of "a" in fig. 3;

fig. 5A, 5C and 5D are top plan views of the vertical type memory device in fig. 3, and fig. 5B is a sectional view taken along line a-a' in fig. 5A;

fig. 6A to 12A are top plan views corresponding to fig. 5A, and fig. 6B to 12B are sectional views corresponding to fig. 5B;

fig. 13 is a perspective view of a memory block of a vertical type memory device according to a second embodiment of the inventive concept;

fig. 14A is a top plan view of the vertical type memory device in fig. 13, and fig. 14B is a cross-sectional view taken along line a-a' of fig. 14A;

fig. 15A to 18A are top plan views corresponding to fig. 14A, and fig. 15B to 18B are sectional views corresponding to fig. 14B;

fig. 19 is a perspective view of a memory block of a vertical type memory device according to a third embodiment of the inventive concept;

fig. 20A and 20C are top plan views of the vertical type memory device in fig. 19, and fig. 20B is a cross-sectional view taken along line a-a' in fig. 20A;

fig. 21 is a perspective view of a memory block of a vertical type memory device according to a fourth embodiment of the inventive concept;

fig. 22A is a top plan view of the vertical type memory device in fig. 21, and fig. 22B is a cross-sectional view taken along line a-a' in fig. 22A;

fig. 23A to 25A are top plan views corresponding to fig. 22A, and fig. 23B to 25B are sectional views corresponding to fig. 22B;

fig. 26 is a perspective view of a memory block of a vertical type memory device according to a fifth embodiment of the inventive concept;

fig. 27A is a top plan view of the vertical type memory device in fig. 26, and fig. 27B is a cross-sectional view taken along line a-a' in fig. 27A;

fig. 28 is a schematic block diagram illustrating an example of a memory system including semiconductor devices manufactured according to various embodiments of the inventive concept;

fig. 29 is a schematic block diagram illustrating an example of a memory card including semiconductor devices manufactured according to embodiments of the inventive concept; and

fig. 30 is a schematic block diagram showing an example of an information processing system on which semiconductor devices according to various embodiments of the present inventive concept are mounted.

Detailed Description

The advantages and features of the inventive concepts, and methods of accomplishing the same, will become apparent from the following exemplary embodiments, which are described in greater detail with reference to the accompanying drawings. However, it should be noted that the present inventive concept is not limited to the following exemplary embodiments, and may be implemented in various forms. Accordingly, the exemplary embodiments are provided only to disclose examples of the inventive concept and to let those skilled in the art understand the essence of the inventive concept.

It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept. The terminology used in the description presented herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Like reference numerals refer to like elements throughout the specification.

The present inventive concept will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the inventive concept are shown.

FIG. 1 is a block diagram of a memory device according to some embodiments of the inventive concept. Referring to fig. 1, a memory device 100 according to some embodiments of the inventive concept may include a memory cell array 10, an address decoder 20, a read/write circuit 30, a data input/output (I/O) circuit 40, and a control logic 50.

The memory cell array 10 may be connected to the address decoder 20 through a plurality of word lines WL, and connected to the read/write circuit 30 through bit lines BL. The memory cell array 10 includes a plurality of memory cells. For example, the memory cell array 10 is configured to store one or more bits in a single cell.

Address decoder 20 may be configured to operate in response to control by control logic 50. The address decoder 20 may receive the address ADDR from the outside. The address decoder 20 decodes a row address in the received address ADDR to select a corresponding one of the word lines WL. In addition, the address decoder 20 may include well-known components such as, for example, a row decoder, a column decoder, an address buffer, and the like.

The read/write circuit 30 may be connected to the memory cell array 10 through bit lines BL, and to the data I/O circuit 40 through data lines D/L. The read/write circuits 30 may be configured to operate in response to control by the control logic 50. Read/write circuit 30 may be configured to receive the decoded column address from address decoder 20. The read/write circuit 30 may be configured to select the bit line BL using the decoded column address. For example, the read/write circuit 30 may be configured to receive data from the data I/O circuit 40 and write the received data to the memory cell array 10. The read/write circuit 30 may be configured to read data from the memory cell array 10 and transfer the read data to the data I/O circuit 40. The read/write circuit 30 may be configured to read data from a first storage area of the memory cell array 10 and write the read data to a second storage area of the memory cell array 10. For example, the read/write circuit 30 may be configured to perform a copy-back operation.

The read/write circuit 30 may include components including a page buffer (or page register), a column selector, and the like. As another example, the read/write circuits 30 may include components including read amplifiers, write drivers, column selectors, and the like.

The data I/O circuit 40 may be connected to the read/write circuit 30 through a data line DL. The data I/O circuit 40 may be configured to operate in response to control by the control logic 50. The DATA I/O circuit 40 may be configured to exchange DATA with an external device. The DATA I/O circuit 40 is configured to transfer DATA received from the outside to the read/write circuit 30 through the DATA line DL. The DATA I/O circuit 40 is configured to output DATA transferred through the DATA line DL to an external device. For example, the data IO circuit 40 may include components such as a data buffer and the like.

Control logic 50 may be coupled to address decoder 20, read/write circuits 30, and data I/O circuits 40. Control logic 50 may be configured to control the operation of memory device 100. The control logic 50 may operate in response to a control signal CTRL transmitted from the outside.

Fig. 2 is a block diagram illustrating an example of the memory cell array 10 in fig. 1. Referring to fig. 2, the memory cell array 10 may include a plurality of memory blocks BLK1 through BLKh. Each of the memory blocks BLK1 through BLKh may have a three-dimensional structure (or a vertical structure). For example, each of memory blocks BLK 1-BLKh may include structures that extend along corresponding orthogonal coordinate axes in first, second, and third directions. For example, each of the memory blocks BLK1 through BLKh includes a plurality of cell strings extending in the third direction, and the memory blocks BLK1 through BLKh extend in the second direction. The additional memory blocks may extend in the first direction. Thus, the memory blocks and associated structures may extend in three directions.

Fig. 3 is a perspective view of a vertical type memory device according to a first embodiment of the inventive concept, and fig. 4A to 4I are enlarged views of "a" in fig. 3.

Referring to fig. 3, a substrate 110 is provided. The substrate 110 may have a first conductivity type, such as P-type. The gate structure GL may be disposed on the substrate 110. The buffer dielectric layer 121 may be disposed between the substrate 110 and the gate structure GL. The buffer dielectric layer 121 may include silicon oxide or other suitable dielectric material such as a high-k dielectric material.

The gate structure GL may extend in a first direction on the substrate 110. The plurality of sets of gate structures GL may face each other and may extend in a second direction on the substrate 110, wherein the second direction is different from the first direction. For example, the second direction may be substantially orthogonal to the first direction. The gate structure GL may include the insulation patterns 125, and the gate electrodes G1 to G6 spaced apart from each other with the insulation patterns 125 therebetween. The gate electrodes G1 through G6 may include first through sixth gate electrodes G1 through G6 sequentially stacked on the substrate 110. The insulation pattern 125 may include silicon oxide. The buffer dielectric layer 121 may be thinner than the insulating pattern 125. Gate electrodes G1-G6 may include doped silicon, metal (e.g., tungsten), metal nitride, metal silicide, combinations thereof, and the like. Although six gate electrodes are shown, there may be any number of gate electrodes greater than six in the gate structure GL. In a specific example, the number of gate electrodes may be selected based on the number of memory cells and control transistors in the memory cell string.

The first partition 131 extending in the first direction may be disposed between the gate structures GL. The first separation region 131 may be filled with a first separation insulating layer (not shown here, see 141 in fig. 5B). The common source line CSL is disposed in the substrate 110 adjacent to the first partition 131. The common source line CSL may be formed in the substrate 110. The common source lines CSL may be spaced apart from each other and extend in the first direction. The common source line CSL may have a second conductivity type (e.g., N-type) different from the first conductivity type. Unlike in the drawing, the common source line CSL may have a line-shaped conductive pattern disposed between the substrate 110 and the first gate electrode G1 and extending in the first direction.

The vertical pillars PL are arranged in a matrix extending in the first and second directions. A plurality of vertical pillars PL may be coupled with the gate structure GL. A plurality of vertical pillars PL are connected to the substrate 110 and extend through the gate electrodes G1-G6. The vertical pillars PL may have a major axis extending upward (i.e., in a third direction) from the substrate 110. One end of the vertical pillar PL may be coupled with the substrate 110, and the opposite end may be coupled with the bit lines BL1 and BL2 extending in the second direction.

Sub-interconnects SBL1 and SBL2 are disposed between the vertical pillars PL and bit lines BL1 and BL 2. Alternatively, the vertical pillar PL and the sub-interconnects SBL1 and SBL2 may be connected through the first contact 152. Alternatively, the bit lines BL1 and BL2 and the sub-interconnects SBL1 and SBL2 may be connected through the second contact 154. The sub-interconnects SBL1 and SBL2 may interconnect adjacent vertical pillars PL, which may be coupled with the immediately adjacent gate structure GL, through the first contact 152.

A plurality of cell strings of a nonvolatile memory device such as a flash memory device are disposed between the bit lines BL1 and BL2 and the common source line CSL. An individual cell string may include a string selection transistor connected to the bit lines BL1 and BL2, a ground selection transistor (ground selection transistor) connected to the common source line CSL, and a plurality of memory cells disposed between the string selection transistor and the ground selection transistor. The selection transistor and the plurality of memory cells may be disposed corresponding to a single semiconductor pillar PL. The first gate electrode G1 may be a ground selection gate line GSL of a ground selection transistor. The second to fifth gate electrodes G2 to G5 may be cell gates WL of a plurality of memory cells. The sixth gate electrode G6 may be a string selection gate line SSL of the string selection transistor.

The information storage element 135 may be disposed between the second to fifth gate electrodes G2 to G5 and the vertical pillar PL. Although it is illustrated in fig. 3 that the information storage elements 135 extend between the gate electrodes G1 through G6 and the insulating patterns 125 and between the gate electrodes G1 through G6 and the vertical pillars PL, the positions and shapes of the information storage elements 135 are not limited thereto. In the embodiments described later, the information storage element 135 may be changed in various ways (see fig. 4A to 4I).

In one aspect, the vertical pillar PL may comprise a semiconductor material. Therefore, the vertical pillar PL may serve as a channel of the transistor. The vertical column PL may be a solid cylindrical column or a hollow cylindrical (e.g. macaroni type) column. The filling insulation layer 127 may be filled in the hollow vertical pillar. The filling insulating layer 127 may include silicon oxide. The filling insulation layer 127 may directly contact the inner wall of the vertical pillar PL. The vertical pillar PL and the substrate 110 may be a substantially continuous semiconductor structure. In this case, the vertical pillar PL may be a single crystal semiconductor. Thus, the vertical pillars PL may be formed using a growth technique such as Selective Epitaxial Growth (SEG). Alternatively, the interface of the vertical pillar PL and the substrate 110 may include a boundary surface and/or other discontinuities. In this case, the vertical pillars PL may be polycrystalline or amorphous-structured vertical pillars formed by, for example, chemical vapor deposition. The conductive pattern 128 may be disposed at one end of the vertical pillar PL. The end of the vertical pillar PL contacting the conductive pattern 128 may form a drain region of a transistor such as a string selection transistor.

As an example, referring to fig. 4A, similar to fig. 3, the information storage element 135 may include a blocking insulating layer 135c adjacent to the gate electrodes G1 to G6, a tunnel insulating layer 135a adjacent to the vertical pillar PL, and a charge storage layer 135b between the blocking insulating layer 135c and the tunnel insulating layer 135 a. The information storage element 135 may extend between the gate electrodes G1 through G6 and both the insulating pattern 125 and the vertical pillars PL. The blocking insulating layer 135c may include a high-k dielectric (e.g., aluminum oxide or hafnium oxide). The barrier insulating layer 135c may be a multilayer film including a plurality of thin films. For example, the blocking insulating layer 135c may include aluminum oxide and/or hafnium oxide, and there may be various stacked orders of aluminum oxide and hafnium oxide. The charge storage layer 135b may be an insulating layer including a charge trapping layer, conductive nanoparticles, and the like. The charge trapping layer may comprise, for example, silicon nitride. The tunnel insulating layer 135a may include silicon oxide or other suitable dielectric material.

As another example, referring to fig. 4B to 4D, unlike that shown in fig. 3, some portions of the information storage element 135 may not extend between the insulation pattern 125 and the gate electrodes G1 to G6, but some other portions of the information storage element 135 may still extend between the gate electrodes G1 to G6 and the vertical pillars PL. Referring to fig. 4B, a tunnel insulating layer 135a may extend between the insulating patterns 125 and the vertical pillars PL, and a charge storage layer 135B and a blocking insulating layer 135c may extend between the insulating patterns 125 and the gate electrodes G1 to G6.

Referring to fig. 4C, portions of the tunnel insulating layer 135a and the charge storage layer 135b may extend between the insulating patterns 125 and the vertical pillars PL, and portions of the blocking insulating layer 135C may extend between the insulating patterns 125 and the gate electrodes G1 to G6. Referring to fig. 4D, the tunnel insulating layer 135a, the charge storage layer 135b, and the blocking insulating layer 135c may extend between the insulating patterns 125 and the vertical pillars PL, however, the insulating patterns 125 directly contact the gate electrodes G1 to G6.

Unlike the above example, referring to fig. 4E, the charge storage layer 135b may include polysilicon. At this time, the tunnel insulating layer 135a, the charge storage layer 135b, and the blocking insulating layer 135c may be disposed between the gate electrodes G1 to G6, the vertical pillars PL, and the insulating patterns 125.

On the other hand, the vertical pillars PL may be conductive pillars. The vertical pillars PL may include at least one of a conductive material such as a doped semiconductor, a metal, a conductive metal nitride, a silicide, or a nanostructure such as a carbon nanotube or graphene.

Referring to fig. 4F, the information storage element 135 may be disposed only between the gate electrodes G1 through G6, the vertical pillars PL, and the insulation pattern 125.

Referring to fig. 4G and 4H, the information storage element 135 may extend between the insulation pattern 125 and the vertical pillar PL or between the insulation pattern 125 and the gate electrodes G1 to G6. At this time, the information storage element 135 may be a variable resistance pattern. The variable resistance pattern may include at least one of materials having a variable resistance characteristic (i.e., whose resistance is variable). Hereinafter, examples of the variable resistance pattern used as the information storage element 135 will be explained below.

As an example, the information storage element 135 may include a material whose resistance may be changed depending on heat generated by a current flowing through its adjacent electrode. The material may be, for example, a phase change material. The phase change material may include at least one of antimony (Sb), tellurium (Te), and selenium (Se). For example, the phase change material may include a chalcogenide compound in which tellurium (Te) has a concentration of about 20 to about 80 atomic percent, antimony (Sb) has a concentration of about 5 to about 50 atomic percent, and the balance is germanium (Ge). In addition, the phase change material may include at least one of N, O, C, Bi, In, B, Sn, Si, Ti, Al, Ni, Fe, Dy, and La as an impurity. Alternatively, the variable resistance pattern may be made of only one of GeBiTe, InSb, GeSb, and GaSb.

As an example, the information storage element 135 may be formed to have a thin film structure whose resistance may be changed by a spin transfer process (spin transfer process) caused by a current flowing through the information storage element 135. The information storage element 135 may have a thin film structure to exhibit a magnetoresistance characteristic, and include at least one of ferromagnetic materials and/or at least one of antiferromagnetic materials. The information storage element 135 may then include a free layer and a reference layer.

As yet another example, the information storage element 135 may include at least one of perovskite compounds or at least one of transition metals. For example, the information storage element 135 may include at least one of niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO ((Pr, Ca) MnO3), strontium titanium oxide, barium strontium titanium oxide, strontium zirconium oxide, barium zirconium oxide, and barium strontium zirconium oxide.

According to some examples of the inventive concept, referring to fig. 4I, at least one of the materials SW having a self-rectifying property (e.g., a PN junction diode) may be disposed between the information storage element 135 and the gate electrodes G1 to G6.

Fig. 5A is a top plan view of the vertical type memory device in fig. 3, and fig. 5B is a cross-sectional view taken along line a-a' in fig. 5A. Referring to fig. 5A and 5B, a vertical type memory device according to some embodiments of the inventive concept will now be described in detail.

Referring to fig. 5A and 5B, the gate structure GL may include first and second gate structures GL1 and GL 2. The sixth gate electrode G6 of the first gate structure GL1 may be referred to as a first string selection line SSL1, and the sixth gate electrode G6 of the second gate structure GL2 may be referred to as a second string selection line SSL 2. The first and second string selection lines SSL1 and SSL2 may be alternately arranged in the second direction.

The vertical pillars may include first and second vertical pillars PL1 and PL2 sequentially arranged in the second direction. The first and second vertical pillars PL1 and PL2 may be arranged in a matrix of first and second directions. The first vertical pillar PL1 is coupled to one side of the string select line SSL1 or SSL2, and the second vertical pillar PL2 may be coupled to the other side thereof. The vertical pillars immediately adjacent in the first direction may be spaced apart from each other by, for example, two pitches of the bit lines BL1 and BL 2.

The sub-interconnects may interconnect vertical pillars PL1 and PL2 coupled to different string select lines SSL. The sub-interconnects may include a first sub-interconnect SBL1 and a second sub-interconnect SBL 2. For example, the first sub-interconnect SBL1 may connect the second vertical pillar PL2 of one first string selection line SSL1 to the first vertical pillar PL1 of the second string selection line SSL2, and the second sub-interconnect SBL2 may connect the second vertical pillar PL2 of the second string selection line SSL2 to the first vertical pillar PL1 of the other first string selection line SSL 1.

Each first sub-interconnect SBL1 and each second sub-interconnect SBL2 may be arranged in the first direction. The first and second sub-interconnections SBL1 and SBL2 may be alternately arranged in the second direction. The first sub-interconnect SBL1 and the second sub-interconnect SBL2 may be connected to different bit lines adjacent to each other. For example, the first sub-interconnect SBL1 may be connected to a first bit line BL1, and the second sub-interconnect SBL2 may be connected to a second bit line BL 2.

The first sub-interconnect SBL1 may include a first protrusion P1 protruding in a first direction, and the second sub-interconnect SBL2 may include a second protrusion P2 protruding in a direction opposite to the first direction.

In some embodiments, depending on the application, first and second protrusions P1 and P2 may be arranged to extend in the same direction.

The protrusions P1 and P2 may extend over the first separation insulating layer 141 between the gate structures GL1 and GL 2.

The first contact 152 may connect the vertical pillars PL1 and PL2 to the sub-interconnects SBL1 and SBL 2. The second contact 154 may connect the sub-interconnects SBL1 and SBL2 to the bit lines BL1 and BL 2. The first contact 152 may be disposed on the vertical pillars PL1 and PL 2. The second contact 154 may be disposed on the sub-interconnects SBL1 and SBL2 over the first separation insulating layer 141 between the gate structures GL1 and GL 2. For example, the second contact 154 may be directly over the first isolation insulating layer 141.

As shown in fig. 5A, the second contact 154 on the first sub-interconnect SBL1 is shifted in a first direction away from the first contact 152, e.g., by half the pitch of the bit lines BL1 and BL 2; the second contact 154 on the second sub-interconnect SBL2 is shifted from the first contact 152 in a direction opposite to the first direction, for example, by half the pitch of the bit lines BL1 and BL 2. The second contacts 154 may be disposed on the protrusions P1 and P2.

Fig. 5C and 5D show a modified example of fig. 5A. Referring to fig. 5C and 5D, modified examples of the vertical type memory device according to some embodiments of the inventive concept will be described in detail below. Technical features similar to those illustrated in fig. 5A and 5B will not be described, but differences therebetween will be described in detail.

Referring to fig. 5C, the first sub-interconnect SBL1 may extend in the second direction and include a protrusion P1 protruding in the first direction. The second sub-interconnect SBL2 may have a rectangular or substantially rectangular shape extending in the second direction without the protrusion P1 or P2. Second contact 154 on first sub-interconnect SBL1 may be displaced from first contact 152 and second contact 154 on second sub-interconnect SBL2 may be aligned with first contact 152. The second contact 154 on the first sub-interconnect SBL1 may be displaced from the first contact 152 by one pitch of the bit lines BL1 and BL2 in the first direction.

Referring to fig. 5D, the first and second sub-interconnects SBL1 and SBL2 may have a rectangular or rectangular shape extending in the second direction. For example, the sub-interconnects SBL1 and SBL2 may have a width greater than the bit lines BL1 and BL2 and a width smaller than the diameter of the vertical pillars. The second contact 154 on the first sub-interconnect may be shifted in the first direction by half a pitch of the first contact 152, e.g., bit lines BL1 and BL2, and the second contact 154 on the second sub-interconnect SBL2 may be shifted in the opposite direction to the first direction by half a pitch of the first contact 152, e.g., bit lines BL1 and BL 2. Sub-interconnects SBL1 and SBL2 have widths that extend from first contact 152 to second contact 154.

As shown in fig. 5C and 5D, sub-interconnects SBL1 and SBL2 may be modified into various shapes. Although a specific shape and size have been used as an example, in other embodiments, the sub-interconnect SBL may take other shapes, sizes, and the like.

In the above-described embodiments of the inventive concept, constructing the vertical pillars to be connected to the bit lines by sub-interconnects according to the techniques described herein allows adjacent bit lines (e.g., immediately adjacent bit lines) to be more closely disposed, thereby increasing integration density. For example, if the diameter of a vertical pillar when viewed from the top is referred to as F, the effective area may be defined as the average area occupied by a single channel on the top surface. In the layout of a conventional VNAND arrangement, the effective area for a single channel is 6F²(2F × 3F/1 channel); however the effective area for a single channel in the first embodiment of the inventive concept is reduced to 5F²(2F 5F/2 channel). Therefore, the unit cell area can be reduced, thereby increasing the integration density. Furthermore, the number of bit lines (i.e., page size) selected by one string select gate may be doubled when compared to a conventional VNAND. Then, weaveThe stroke and read speed can be improved.

A method of forming the vertical type memory device in fig. 3 will now be described. Fig. 6A to 12A are top plan views corresponding to fig. 5A, and fig. 6B to 12B are cross-sectional views corresponding to fig. 5B.

Referring to fig. 6A and 6B, a substrate 110 is provided. The substrate 110 may have a first conductivity type, such as P-type. A buffer dielectric layer 121 may be formed on the substrate 110. The buffer dielectric layer 121 may include, for example, silicon oxide. The buffer dielectric layer 121 may be formed by, for example, a thermal oxidation process. The sacrificial layers 123 and the insulating layers 124 are alternately stacked on the buffer dielectric layer 121. The thickness of the uppermost insulating layer 124U may be greater than the thickness of the other insulating layers 124. The insulating layers 124, 124U may include, for example, silicon oxide. The sacrificial layer 123 may include a material having different wet etchability (etch selectivity) with respect to the buffer dielectric layer 121 and the insulating layers 124, 124U. Sacrificial layer 123 may comprise, for example, silicon nitride, silicon oxynitride, polysilicon, or polycrystalline silicon germanium. The sacrificial layer 123 and the insulating layer 124 may be formed by, for example, Chemical Vapor Deposition (CVD).

Referring to fig. 7A and 7B, a vertical hole 126 is formed to expose the substrate 110, which passes through the buffer dielectric layer 121, the sacrificial layer 123, and the insulating layers 124, 124U. The vertical holes 126 may be provided in the same manner as the vertical pillars PL1 and PL2 explained with reference to fig. 5A.

Referring to fig. 8A and 8B, vertical pillars PL1 and PL2 are formed within vertical holes 126. In one aspect, the vertical pillars PL1 and PL2 may be a semiconductor layer of the first conductivity type. The semiconductor layer may be formed to not fill (i.e., partially fill) the vertical hole 126, and an insulating material may be formed on the semiconductor layer to fill the vertical hole 126. The semiconductor layer and insulating material may be planarized to expose the uppermost insulating layer 124U. Thus, cylindrical vertical pillars PL1 and PL2 may be formed, which have an interior filled with a filling insulation layer 127.

Alternatively, the semiconductor layer may be formed to fill the vertical hole 126. At this time, the filling of the insulating layer may not be required. The upper portions of the vertical pillars PL1 and PL2 may be recessed below the uppermost insulating layer. The conductive pattern 128 may be formed within a vertical hole 126 with vertical pillars PL1 and PL2 recessed within the vertical hole 126. The conductive pattern 128 may be formed of a conductive material such as doped polysilicon or metal. The drain region may be formed by introducing impurities of the second conductive type into the conductive pattern 128 and upper portions of the vertical pillars PL1 and PL 2. The second conductivity type may be N-type.

On the other hand, the vertical pillars PL1 and PL2 may include at least one of a conductive material such as a doped semiconductor, a metal, a conductive metal nitride, a silicide, or a nanostructure (such as a carbon nanotube or graphene).

Referring to fig. 9A and 9B, the buffer dielectric layer 121, the sacrificial layer 123, and the insulating layer 124 are sequentially patterned to form separation regions 131, the separation regions 131 being spaced apart from each other, extending in the first direction, and exposing portions of the substrate 110. The patterned insulating layers 124, 124U may become insulating patterns 125.

Referring to fig. 10A and 10B, the patterned sacrificial layer 123 exposed to the separation region 131 is selectively removed to form a recessed region 133. The recessed region 133 corresponds to a region in which the sacrificial layer 123 is removed, and is defined by the vertical pillars PL1 and PL2 and the insulating pattern 125. If the sacrificial layer 123 includes silicon nitride or silicon oxynitride, the process of removing the sacrificial layer 123 may be performed with an etchant containing phosphoric acid. Portions of the sidewalls of vertical pillars PL1 and PL2 are exposed with respect to recessed region 133.

Referring to fig. 11A and 11B, the information storage element 135 is formed in the recessed area 133. In an embodiment, the information storage element 135 may include a tunnel insulating layer contacting the vertical pillars PL1 and PL2, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer (see, e.g., fig. 4A). At this time, the vertical pillars PL1 and PL2 may be semiconductor pillars. The tunnel insulating layer may include silicon oxide. The tunnel insulating layer may be formed by thermally oxidizing the vertical pillars PL1 and PL2 exposed with respect to the recessed region 133. Alternatively, the tunnel insulating layer may be formed by an Atomic Layer Deposition (ALD) process. The charge storage layer may be a charge trapping layer or an insulating layer comprising conductive nanoparticles. The charge trapping layer may comprise, for example, silicon nitride. The blocking insulating layer may comprise a high-k dielectric (e.g., aluminum oxide or hafnium oxide). The barrier insulating layer may be a multilayer film including a plurality of thin films. For example, the blocking insulating layer may include aluminum oxide and silicon oxide, and there may be various stacking orders of the aluminum oxide and the silicon oxide. The charge storage layer and the blocking insulating layer may be formed by an ALD process and/or a Chemical Vapor Deposition (CVD) process having excellent step coverage. Alternatively, when the information storage element 135 has the structure illustrated in fig. 4B to 4E, at least one of a tunnel insulating layer, a charge storage layer, and/or a blocking insulating layer constituting the information storage element 135 may be formed within the vertical hole 126 before the formation of the vertical pillars PL1 and PL 2.

In some other embodiments, the information storage element 135 may be a variable resistance pattern (see fig. 4F to 4H). The variable resistance pattern may include at least one of materials having a variable resistance characteristic (i.e., its resistance is variable depending on a current flowing therethrough). In this case, vertical pillars PL1 and PL2 may be conductive pillars comprising conductive materials, such as doped semiconductors, metals, conductive metal nitrides, silicides, or nanostructures, such as carbon nanotubes or graphene. When the information storage element 135 has the structure shown in fig. 4G, the information storage element 135 may be formed within the vertical hole 126 before the formation of the vertical pillars PL1 and PL 2.

A conductive layer is formed on the information storage element 135 within the recessed region 133. The conductive layer may be formed of at least one of doped silicon, a metal (e.g., tungsten), a metal nitride, and a metal silicide. The metal conductive layer may be formed by an ALD process. When the conductive layer is a metal silicide layer, the conductive layer may be formed by forming a polysilicon layer, removing a portion of the polysilicon layer adjacent to the first partition region 131 to recess the polysilicon layer, forming a metal layer on the recessed polysilicon layer, heat-treating the metal layer, and removing an unreacted metal layer. The metal layer for the metal silicide layer may include tungsten, titanium, cobalt, or nickel.

The conductive layer formed outside the recessed region 133 (i.e., within the first partition region 131) is removed. Thus, the gate electrodes G1 to G6 are formed in the recessed region 133. The gate electrodes G1 to G6 extend in the first direction. The gate structure GL may include gate electrodes G1 to G6. The gate structure GL may include first and second gate structures GL1 and GL2 alternately arranged along the second direction. The first and second vertical pillars PL1 and PL2 arranged in a matrix in the first and second directions may be coupled with one gate structure.

The conductive layer formed within the separation region 131 may be removed to expose the substrate 110. The impurities of the second conductive type may be introduced into the exposed substrate 110 at a high concentration to form the common source line CSL.

Referring to fig. 12A and 12B, a first separation insulating layer 141 is formed to fill the separation region 131. The first contact 152 may be formed on the vertical pillars PL1 and PL 2. Sub-interconnects SBL1 and SBL2 may be formed on the first contact 152. Sub-interconnects SBL1 and SBL2 may connect vertical pillars PL1 and PL2 coupled to adjacent string select lines SSL1 and SSL2, respectively, through first contacts 152. That is, the sub-interconnects SBL1 and SBL2 may cross the first separation insulating layer 141.

The first sub-interconnect SBL1 and the second sub-interconnect SBL2 may extend in the second direction. The first sub-interconnect SBL1 may include a first protrusion P1 protruding in a first direction, and the second sub-interconnect may include a second protrusion P2 protruding in a direction opposite to the first direction. The protrusions P1 and P2 may extend over the first separation insulating layer 143 between the gate structures GL1 and GL 2.

Returning to fig. 5A and 5B, the first sub-interconnect SBL1 and the second sub-interconnect SBL2 are connected to different adjacent bit lines through the second contact 154. The first sub-interconnect SBL1 may be connected to a first bit line BL1, and the second sub-interconnect SBL2 may be connected to a second bit line BL 2.

Fig. 13 is a perspective view of a memory block of a vertical type memory device according to some embodiments of the inventive concept. Fig. 14A is a top plan view of the vertical type memory device in fig. 13, and fig. 14B is a cross-sectional view taken along line a-a' of fig. 14A. Technical features similar to those of the embodiment described with reference to fig. 3 will not be described, but differences therebetween will be described in detail.

Referring to fig. 13, 14A and 14B, four vertical pillars PL1, PL2, PL1 and PL2 are sequentially arranged in a single gate structure GL along the second direction. Four vertical pillars PL1, PL2, PL1 and PL2 are arranged in a matrix and also extend in the first direction in the gate structure GL.

The sixth gate electrode G6 of one gate structure GL may include first and second string selection lines SSL1 and SSL 2. The first string selection lines SSL1 and the second string selection lines SSL2 may be adjacent to each other and alternately arranged in the second direction. The second separation insulating layer 142 is formed between the first string selection line SSL1 and the second string selection line SSL 2. The second separation insulating layer 142 may have a smaller width than the first separation insulating layer 141.

The first protrusion P1 may extend over the first partition insulating layer 141, and the second protrusion P2 may extend over the second partition insulating layer 142. The second contact 154 on the first sub-interconnect SBL1 may be disposed on the first partition insulating layer 141, and the second contact 154 on the second sub-interconnect SBL2 may be disposed on the second partition insulating layer 142.

As shown in fig. 5C and 5D, the sub-interconnects SBL1 and SBL2 may be modified into various shapes.

Referring to fig. 14A, in this embodiment of the inventive concept, the effective area for a single channel is reduced to 4F²(2F 4F/2 channel). Also, the unit cell area can be reduced to increase the integration density. Further, the number of bit lines (i.e., page size) selected by one string select gate may be doubled when compared to a conventional VNAND. Thus, programming and reading speeds can be increased.

A method of manufacturing the vertical type memory device in fig. 13 will now be described. Fig. 15A to 17A are top plan views corresponding to fig. 14A, and fig. 15B to 17B are sectional views corresponding to fig. 14B. Technical features similar to those of the embodiment described with reference to fig. 6A to 12B will not be described, but differences therebetween will be described in detail.

Referring to fig. 15A and 15B, similar to the embodiment described with reference to fig. 6A to 8B, vertical pillars PL1 and PL2 are formed within vertical holes that penetrate the buffer dielectric layer 121, the sacrificial layer 123, and the insulating layer 124 to expose the substrate 110. The vertical pillars PL1 and PL2 may be recessed, and the conductive pattern 128 may be formed within the recessed vertical hole.

Referring to fig. 16A and 16B, the buffer dielectric layer 121, the sacrificial layer 123, and the insulating layer 124 may be patterned to form separation regions 131 spaced apart from each other. The separation region 131 extends in the first direction, and exposes a portion of the substrate 110. The patterned insulating layer 124 becomes an insulating pattern 125. The sacrificial layer 123 exposed to the separation region 131 is selectively removed to form a recessed region 133.

Referring to fig. 17A and 17B, an information storage element 135 and a conductive layer are formed in the recessed region 133. The conductive layer formed outside the recessed region 133 (i.e., inside the separation region 131) is removed. Then, the gate electrodes G1 to G6 are formed in the recessed region 133 described above. The gate electrodes G1 to G6 extend in the first direction.

The conductive layer formed within the separation region 131 may be removed to expose a portion of the substrate 110. The impurities of the second conductive type may be introduced into the exposed substrate 110 at a high concentration to form the common source line CSL.

The first separation insulating layer 141 is formed to fill the separation region 131. The sixth gate electrode G6 is patterned to form first and second string selection lines SSL1 and SSL2 in the single gate structure GL. The second partition 132 is formed between the first and second string selection lines SSL1 and SSL 2. The first and second string selection lines SSL1 and SSL2 are adjacent to each other and alternately arranged in the second direction. The first and second vertical pillars PL1 and PL2 arranged in a matrix may be coupled with one string selection line. For example, in this embodiment, within a single gate structure GL, the first and second vertical pillars PL1 and PL2 may be coupled with one of the first and second string selection lines SSL1 and SSL 2.

Referring to fig. 18A and 18B, a second partition insulating layer 142 is formed to fill the second partition region 132. The first contact 152 may be formed on the vertical pillars PL1 and PL 2. Sub-interconnects SBL1 and SBL2 may be formed on the first contact 152. The first sub-interconnect SBL1 and the second sub-interconnect SBL2 may extend in the second direction. The sub-interconnects SBL1 and SBL2 may connect the vertical pillars PL1 and PL2 through the first contacts 152 in a one-to-one correspondence, the vertical pillars PL1 and PL2 being coupled with the immediately adjacent string select lines SSL1 and SSL2, respectively.

Referring to fig. 14A and 14B, the first sub-interconnect SBL1 and the second sub-interconnect SBL2 are connected to adjacent different bit lines through the second contact 154. The first sub-interconnect SBL1 may be connected to a first bit line BL1, and the second sub-interconnect SBL2 may be connected to a second bit line BL 2.

Fig. 19 is a perspective view of a memory block of a vertical type memory device according to some embodiments of the inventive concept. Fig. 20A is a top plan view of the vertical type memory device in fig. 19, and fig. 20B is a cross-sectional view taken along line a-a' in fig. 20A. Technical features similar to those of the embodiment described with reference to fig. 3 will not be described, but differences therebetween will be described in detail.

Referring to fig. 19, 20A and 20B, the gate structure GL may include adjacent first to third gate structures. The sixth gate electrode G6 of the first gate structure may be referred to as a first string selection line SSL1, the sixth gate electrode G6 of the second gate structure may be referred to as a second string selection line SSL2, and the sixth gate electrode G6 of the third gate structure may be referred to as a third string selection line SSL 3. The first to third string selection lines SSL1 to SSL3 may be alternately arranged in the second direction.

The vertical pillars PL may include vertical pillars PL1 to PL4 arranged in a zigzag manner. That is, the vertical posts PL1 to PL4 may be arranged offset from each other in both the first direction and the second direction. The first and fourth vertical pillars PL1 and PL4 may be disposed at both sides of the string selection lines SSL1 to SSL3, and the second and third vertical pillars PL2 and PL3 may be disposed between the first vertical pillar PL1 and the fourth vertical pillar PL 4. The second vertical column PL2 may be displaced in a first direction away from the first vertical column PL 1. The fourth vertical column PL4 may be displaced in the first direction away from the third vertical column PL 3. Immediately adjacent vertical pillars may be spaced from each other along the first direction by two pitches of bit lines BL 1-BL 4.

The sub-interconnects may include first to fourth sub-interconnects SBL1 to SBL 4. The first sub-interconnect SBL1 may connect the third vertical pillar PL3 coupled with the first string select line SSL1 to the second vertical pillar PL2 coupled with the second string select line SSL 2. The second sub-interconnect SBL2 may connect the third vertical pillar PL3 coupled with the second string select line SSL2 to the second vertical pillar PL2 coupled with the third string select line SSL 3. The third sub-interconnect SBL3 may connect the fourth vertical pillar PL4 coupled with the first string select line SSL1 to the first vertical pillar PL1 coupled with the second string select line SSL 2. The fourth sub-interconnect SBL4 may connect the fourth vertical pillar PL4 coupled with the second string select line SSL2 to the first vertical pillar PL1 coupled with the third string select line SSL 3.

The first sub-interconnects SBL1 and the third sub-interconnects SBL3 may be alternately arranged in the first direction, and the second sub-interconnects SBL2 and the fourth sub-interconnects SBL4 may be alternately arranged in the first direction. The first sub-interconnects SBL1 and the fourth sub-interconnects SBL4 may be alternately arranged in the second direction, and the second sub-interconnects SBL2 and the third sub-interconnects SBL3 may be alternately arranged in the second direction.

The first to fourth sub-interconnects SBL 1-SBL 4 may be connected to corresponding bit lines. For example, the first sub-interconnect SBL1 may be connected to a first bit line BL1, the second sub-interconnect SBL2 may be connected to a second bit line BL2, the third sub-interconnect SBL3 may be connected to a third bit line BL3, and the fourth sub-interconnect SBL4 may be connected to a fourth bit line BL 4.

In order to connect the vertical pillars PL1 to PL4 to the sub-interconnects SBL1 to SBL4, a first contact 152 may be provided. To connect the sub-interconnects SBL 1-SBL 4 to the bit lines BL 1-BL 4, a second contact 154 may be provided. The first contact 152 may be disposed on the vertical pillars PL1 to PL4, and the second contact 154 may be disposed on the first isolation insulating layer 141. For example, the second contacts 154 on the first and third sub-interconnects SBL1 and SBL3 may be shifted by half the bit line pitch from the first contacts 152 in a first direction, and the second contacts 154 on the second and fourth sub-interconnects SBL2 and SBL4 may be shifted by a quarter of the bit line pitch from the first contacts in a direction opposite to the first direction. The first to fourth sub-interconnects SBL 1-SBL 4 may extend in the second direction. The first and third sub-interconnects SBL1 and SBL3 may include first and third protrusions P1 and P3, respectively, protruding in the first direction. The second and fourth sub-interconnects SBL2 and SBL4 may include second and fourth protrusions P2 and P4, respectively, protruding in a direction opposite to the first direction. The protruding distance of the first and third protrusions P1 and P3 may be twice as long as that of the second and fourth protrusions P2 and P4. The second contacts 154 may be disposed on the protrusions P1 through P4. The protrusions P1-P4 may extend over the first isolation insulating layer 141 between the gate structures.

Fig. 20C shows a modified example of fig. 20A. Referring to fig. 20C, a modified example of a vertical type memory device according to some other embodiments of the inventive concept will now be described more fully. Technical features similar to those illustrated in fig. 20A and 20B will not be described, but differences therebetween will be described in detail.

The first and third sub-interconnects SBL1 and SBL3 may extend in the second direction, and may include protrusions P1 and P3 protruding in the first direction. The second and fourth sub-interconnects SBL2 and SBL4 may have a substantially rectangular shape extending in the second direction. The second contacts 154 on the first and third sub-interconnects SBL1 and SBL3 may be moved away from the first contacts 152 in the first direction, and the second contacts 154 on the second and fourth sub-interconnects SBL2 and SBL4 may not be moved away from the first contacts 152. For example, the second contacts on the first and third sub-interconnects SBL1 and SBL3 may be shifted in the first direction by one pitch from the first contact 152 bit lines BL1 to BL 4. As shown in FIG. 20C, sub-interconnects SBL 1-SBL 4 may be deformed into various shapes.

Referring back to fig. 20A, according to some embodiments of the inventive concept, the effective area for a single channel is reduced to 3.3F²(2F 5F/3 channel). Also, the unit cell area can be reduced, thereby increasing the integration density. Further, the number of bit lines (i.e., page size) selected by one string select gate may be increased four times when compared to a conventional VNAND. Thus, the programming and reading speed can be improved.

The vertical type memory device according to some embodiments of the inventive concept illustrated in fig. 19 may be formed by the method described with reference to fig. 6A through 12B. In addition, the vertical-type memory device according to some embodiments of the inventive concept illustrated in fig. 19 may be modified with the inventive concept described with reference to fig. 13, 14A, and 14B such that the sixth gate electrode G6 of one gate structure GL includes first and second string selection lines SSL1 and SSL 2. The effective area for a single channel can be reduced to less than 3.3F²(2F 5F/3 channel).

Fig. 21 is a perspective view of a memory block of a vertical type memory device according to some embodiments of the inventive concept. Fig. 22A is a top plan view of a portion of the vertical-type memory device in fig. 21, and fig. 22B is a cross-sectional view taken along line a-a' in fig. 22A. Technical features similar to those of the embodiment described with reference to fig. 3 will not be explained, but differences therebetween will be explained in detail.

Referring to fig. 21, 22A, and 22B, a substrate 110 is provided. The substrate 110 may have a first conductivity type, such as P-type. The gate structure GL is disposed on the substrate 110. The gate structure GL may include the insulating patterns 125, and the gate electrodes spaced apart from each other with the insulating patterns 125 therebetween. The gate electrode may include first to sixth gate electrodes G1 to G6 sequentially stacked on the substrate 110. The insulation pattern 125 may include silicon oxide. The gate electrodes G1-G6 may include doped silicon, a metal (e.g., tungsten), a metal nitride, a metal silicide, or a combination thereof. Although six gate electrodes are shown in the drawing, the number of gate electrodes is not limited to six and may be more or less than six.

The vertical pillars PL are arranged in the first and second directions, forming a matrix of vertical pillars PL. The vertical pillars PL are connected to the substrate 110 through the gate electrodes G1 to G6. The vertical pillars PL may have principal axes extending upward (i.e., in a third direction) from the substrate 110. Some end of the vertical pillar PL may be connected to the substrate 110, and the remaining end thereof may be connected to bit lines BL1 and BL2 extending in the second direction.

Sub-interconnects SBL1 and SBL2 are located between the vertical pillars PL and bit lines BL1 and BL 2. The vertical pillar PL and the sub-interconnects SBL1 and SBL2 may be connected by a first contact 152. The bit lines BL1 and BL2 and the sub-interconnects SBL1 and SBL2 may be connected through the second contact 154. The sub-interconnects SBL1 and SBL2 may connect the vertical pillars PL coupled to the immediately adjacent gate structures GL through the first contacts 152.

A plurality of cell strings of the flash memory device are disposed between the bit lines BL1 and BL2 and the substrate 110. The individual cell strings may include a string selection transistor connected to the bit lines BL1 and BL2, a ground selection transistor connected to the substrate 110, and a plurality of memory cells disposed between the string selection transistor and the ground selection transistor. The selection transistor and the plurality of memory cells may be disposed at a single semiconductor pillar PL. The first gate electrode G1 may be a ground selection gate line GSL of a ground selection transistor. The second to fifth gate electrodes G2 to G5 may be cell gates WL of a plurality of memory cells. The sixth gate electrode G6 may be divided into a plurality by the third division region 133 (fig. 21) to serve as a string selection line of the string selection transistor. The string select lines may include first and second string select lines SSL1 and SSL 2. The first and second string selection lines SSL1 and SSL2 may extend in the first direction, and may be alternately arranged in the second direction. For example, the third insulation layer 143 is disposed in the third partition region 133 between the first and second string selection lines SSL1 and SSL2, as shown in fig. 22B.

The information storage element 135 may be disposed between the first to sixth gate electrodes G1 to G6 and the vertical pillar PL. The information storage elements 135 may extend between the gate electrodes G1 through G6 and the insulation patterns 125. The information storage element 135 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer.

The substrate 110 may be provided with source regions (not shown) that form a path for current to flow from the bit lines BL1 and BL2 or to the bit lines BL1 and BL 2.

Since the vertical pillars PL1 and PL2 and the sub-interconnects SBL1 and SBL2 are similar to those described with reference to fig. 3, similar technical features will not be described in more detail. The protrusions P1 and P2 of the sub-interconnects SBL1 and SBL2 may extend over the third insulation layer 143. A second contact 154 may be disposed on sub-interconnects SBL1 and SBL2 over third isolation insulating layer 143.

As shown in fig. 5C and 5D, the sub-interconnects SBL1 and SBL2 may have various shapes.

Referring to fig. 22A, according to some embodiments of the inventive concept, the effective area of a single channel is reduced to 4F²(2F 4F/2 channel). Also, the unit cell area can be reduced to increase the integration density. Further, the number of bit lines (i.e., page size) selected by one string select gate may be doubled when compared to a conventional VNAND. Thus, programming and reading speeds can be increased.

A method of manufacturing the vertical type memory device in fig. 21 will now be described in detail. Fig. 23A to 25A are top plan views corresponding to fig. 22A, and fig. 23B to 25B are cross-sectional views corresponding to fig. 22B.

Referring to fig. 23A and 23B, a substrate 110 is provided. The substrate 110 may have a first conductivity type, such as P-type. Insulating layers 124 and conductive layers 122 are alternately formed on substrate 110. The insulating layer 124 may include, for example, silicon oxide. Conductive layer 122 may comprise, for example, doped silicon, a metal (e.g., tungsten), a metal nitride, a metal silicide, or a combination thereof.

A vertical hole 126 is formed to penetrate the conductive layer 122 and the insulating layer 124 to expose the substrate 110. The vertical holes 126 may be provided in the same manner as the vertical pillars PL1 and PL2 described with reference to fig. 22A.

Referring to fig. 24A and 24B, the information storage element 135 is formed on the sidewall of the vertical hole 126. The information storage element 135 may include a blocking insulating layer, a charge storage layer, and a tunnel insulating layer. The information storage element 135 is anisotropically etched to expose the substrate 110.

Vertical pillars PL1 and PL2 are formed adjacent to the information storage element 135 in the vertical hole 126. Vertical pillars PL1 and PL2 are connected to substrate 110.

In an aspect, the vertical pillars PL1 and PL2 may be a semiconductor layer of the first conductivity type. The semiconductor layer may be formed not to fill the vertical hole 126, and an insulating material may be formed on the semiconductor layer to fill the vertical hole 126. The semiconductor layer and insulating material may be planarized to expose the uppermost insulating layer 124'. Thus, cylindrical vertical pillars PL1 and PL2 filled with the filling insulation layer 127 may be formed. The semiconductor layer may be formed to fill the vertical hole 126. At this time, the filling insulating layer may not be required. The upper portions of the vertical pillars PL1 and PL2 may be recessed to be lower than the top surface of the uppermost insulating layer 124'. The conductive pattern 128 may be formed in a portion of the vertical hole 126 in which the vertical pillars PL1 and PL2 are recessed. The conductive pattern 128 may be doped polysilicon or metal. The drain region may be formed by introducing impurities of the second conductive type into the conductive pattern 128 and upper portions of the vertical pillars PL1 and PL 2. The second conductivity type may be N-type.

On the other hand, the vertical pillars PL1 and PL2 may include at least one of a conductive material such as a doped semiconductor, a metal, a conductive metal nitride, a silicide, or a nanostructure (such as a carbon nanotube or graphene). At this time, the information storage element may be a variable resistance pattern.

The insulating layer 124 and the conductive layer 122 may be patterned to form insulating patterns 125 and gate electrodes G1 through G6. The sixth gate electrode G6 may be additionally patterned to be separated into a plurality of gate electrodes. Accordingly, the sixth gate electrode G6 may include first and second string selection lines SSL1 and SSL 2.

Referring to fig. 25A and 25B, a third isolation insulating layer 143 is disposed in the third isolation region 133 between the first and second string selection lines SSL1 and SSL 2. The first contact 152 may be formed on the vertical pillars PL1 and PL 2. Sub-interconnects SBL1 and SBL2 may be formed on the first contact 152. The sub-interconnects SBL1 and SBL2 may interconnect the vertical pillar PL1 and the immediately adjacent vertical pillar PL2 through the first contact 152, wherein the vertical pillar PL1 and the immediately adjacent vertical pillar PL2 are tied together with different string select lines SSL1 and SSL 2.

The first sub-interconnect SBL1 and the second sub-interconnect SBL2 may extend in the second direction. The first sub-interconnect SBL1 may include a first protrusion P1 protruding in a first direction, and the second sub-interconnect SBL2 may include a second protrusion P2 protruding in a direction opposite to the first direction. The protrusions P1 and P2 may extend above the third insulation layer 143.

Referring back to fig. 22A and 22B, the first sub-interconnect SBL1 and the second sub-interconnect SBL2 are connected to different adjacent bit lines through the second contact 154. That is, the first sub-interconnect SBL1 may be connected to the first bit line BL1, and the second sub-interconnect SBL2 may be connected to the second bit line BL 2.

Fig. 26 is a perspective view of a vertical type memory device according to some embodiments of the inventive concept. Fig. 27A is a top plan view of the vertical type memory device in fig. 26, and fig. 27B is a cross-sectional view taken along line a-a' in fig. 27A. Technical features similar to those of the embodiment described with reference to fig. 21 will not be described, but differences therebetween will be described in detail.

Referring to fig. 26, 27A and 27B, the vertical pillars PL may include first to fourth vertical pillars PL1 to PL4, the first to fourth vertical pillars PL1 to PL4 being sequentially arranged in a zigzag manner. First and second vertical pillars PL1 and PL2 may be coupled with one side of each string select line SSL1 through SSL3, and third and fourth vertical pillars PL3 and PL4 may be coupled with the other side of each string select line SSL1 through SSL 3. The first and fourth vertical pillars PL1 and PL4 may be disposed at edges of the string selection lines SSL1 to SSL3, and the second and third vertical pillars PL2 and PL3 may be disposed between the first vertical pillar PL1 and the fourth vertical pillar PL 4. The second vertical column PL2 may be displaced in a first direction away from the first vertical column PL 1. The fourth vertical column PL4 may be displaced in the first direction away from the third vertical column PL 3. Immediately adjacent vertical pillars may be spaced apart from each other along the first direction by, for example, two pitches of bit lines BL 1-BL 4.

The sub-interconnects may include first to fourth sub-interconnects SBL1 to SBL 4. The first sub-interconnect SBL1 may connect the third vertical pillar PL3 of the first string select line SSL1 to the second vertical pillar PL2 of the second string select line SSL 2. The second sub-interconnect SBL2 may connect the third vertical pillar PL3 of the second string selection line SSL2 to the second vertical pillar PL2 of the third string selection line SSL 3. The third sub-interconnect SBL3 may connect the fourth vertical pillar PL4 of the first string select line SSL1 to the first vertical pillar PL1 of the second string select line SSL 2. The fourth sub-interconnect SBL4 may connect the fourth vertical pillar PL4 of the second string selection line SSL2 to the first vertical pillar PL1 of the third string selection line SSL 3. The first sub-interconnects SBL1 and the third sub-interconnects SBL3 may be alternately arranged in the first direction, and the second sub-interconnects SBL2 and the fourth sub-interconnects SBL4 may be alternately arranged in the first direction. The first and fourth sub-interconnects SBL1 and SBL4 may be alternately arranged in the second direction, and the second and third sub-interconnects SBL2 and SBL3 may be alternately arranged in the second direction. The first to fourth sub-interconnects SBL 1-SBL 4 may be connected to adjacent different bit lines. For example, the first sub-interconnect SBL1 may be connected to a first bit line BL1, the second sub-interconnect SBL2 may be connected to a second bit line BL2, the third sub-interconnect SBL3 may be connected to a third bit line BL3, and the fourth sub-interconnect SBL4 may be connected to a fourth bit line BL 4.

The first contact 152 connects the vertical pillars PL 1-PL 4 to the sub-interconnects SBL 1-SBL 4. The second contact 154 connects the sub-interconnects SBL 1-SBL 4 to the bit lines BL 1-BL 4. The first contacts 152 may be disposed on the vertical pillars PL1 to PL 4; the second contact 154 may be disposed over the third isolation insulating layer 143 or vertically aligned therewith. For example, the second contacts 154 on the first and third sub-interconnects SBL1 and SBL3 may be shifted by half the bit line pitch from the first contacts 152 in a first direction, and the second contacts 154 on the second and fourth sub-interconnects SBL2 and SBL4 may be shifted by a quarter of the bit line pitch from the first contacts in a direction opposite to the first direction. The first to fourth sub-interconnects SBL 1-SBL 4 may extend in the second direction. The first and third sub-interconnects SBL1 and SBL3 may include first and third protrusions P1 and P3, respectively, protruding in the first direction. The second and fourth sub-interconnects SBL2 and SBL4 may include second and fourth protrusions P2 and P4, respectively, protruding in a direction opposite to the first direction. For example, the protruding distance of the first and third protrusions P1 and P3 may be twice as long as that of the second and fourth protrusions P2 and P4. That is, the protruding distance of the first and third protrusions P1 and P3 may be greater to reach the corresponding bit lines. The second contacts 154 may be disposed on the protrusions P1 through P4. The protrusions P1-P4 may extend above the first isolation insulating layer 143 between the gate structures.

Referring to fig. 27A, in a fifth embodiment of the inventive concept, the effective area for a single channel is reduced to less than 3.3F²(2F 5F/3 channel). Also, the unit cell area can be reduced to increase the integration density. Further, due to the arrangement of the vertical pillars PL, the number of bit lines (i.e., page size) selected by one string select gate may be increased four times. Thus, programming and reading speeds can be increased.

Fig. 28 is a schematic block diagram illustrating an example of a memory system including semiconductor devices manufactured according to various embodiments of the inventive concept.

Referring to fig. 28, an electronic system 1100 may include a controller 1110, an input/output device (I/O)1120, a memory device 1130, an interface 1140, and a bus 1150. The controller 1110, the input/output device 1120, the storage device 1130, and/or the interface 1140 may be connected to each other via a bus 1150. Bus 1150 corresponds to the path along which data is transferred. The memory device 1130 may include semiconductor devices according to various embodiments of the inventive concept.

The controller 1110 may include at least one of the following: microprocessors, digital signal processors, microcontrollers, and logic devices capable of performing similar functions. The input/output device 1120 may include a keypad, keyboard, display device, or the like. The memory device 1130 may store data and/or commands. The interface 1140 may be used to transmit data to and receive data from a communication network. The interface 1140 may be a wired interface or a wireless interface. For example, the interface 1140 may include an antenna or a wired/wireless transceiver. Although not shown, the electronic system 1100 may also include a high speed DRAM device and/or an SRAM device as the operating memory device to improve the operation of the controller 1110.

Electronic system 1110 may be used in a Personal Digital Assistant (PDA), a portable computer, a web tablet, a cordless telephone, a mobile phone, a digital music player, a memory card, or all electronic devices capable of transmitting and/or receiving data in a wireless environment.

Fig. 29 is a schematic block diagram illustrating an example of a memory card including semiconductor devices manufactured according to embodiments of the inventive concept.

Referring to fig. 29, a memory card 1200 includes a memory device 1210. The memory device 1210 may include at least one of the semiconductor devices disclosed in the foregoing embodiments. In addition, the memory device 1210 may also include other types of semiconductor memory devices (e.g., DRAM devices and/or SRAM devices, etc.). The memory card 1200 may include a memory controller 1220 that controls data exchange between a host and the memory device 1210. The memory device 1210 and/or the controller 1220 may include a semiconductor device according to various embodiments of the inventive concept.

The memory controller 1220 may include a processing unit 1222 that controls the global operation of the memory card. The memory controller 1220 may include an SRAM 1221 serving as a working memory of the processing unit 1222. In addition, the storage controller 1220 may further include a host interface 1223 and a storage interface 1225. The host interface 1223 may include a data exchange protocol between the memory card 1200 and the host. A memory interface 1225 may connect the memory controller 1220 to the memory device 1210. In addition, memory controller 1220 may also include an Error Code Correction (ECC) block 1224. ECC block 1224 may detect and correct errors in data read from memory device 1210. Although not shown, the memory card 1200 may further include a ROM device that stores code data for connection with a host through an interface. The memory card 1200 may be used as a portable data memory card. Alternatively, the memory card 1200 may be implemented as a Solid State Disk (SSD), which may replace a hard disk of a computer system.

Fig. 30 is a schematic block diagram showing an example of an information processing system on which semiconductor devices formed according to embodiments of the present inventive concept are mounted.

Referring to fig. 30, a flash memory system 1310 according to embodiments of the inventive concept is installed on an information processing system such as a mobile device or a desktop computer. An information processing system 1300 according to various embodiments of the inventive concept includes a flash memory system 1310, a modem 1320 electrically connected to a system bus 1360, a Central Processing Unit (CPU)1330, a RAM 1340, and a user interface 1350. The flash memory system 1310 may have substantially the same construction as the memory system described above. Data processed by the CPU 1330 or externally input data is stored in the flash memory system 1310. As reliability increases, the flash memory system 1310 may reduce resources required for error correction, and thus may provide a high-speed data exchange function to the information processing system 1300. Although not shown in the drawings, it is apparent to those skilled in the art that the information processing system 1300 may further include an application chipset, a camera image processor (CIS), an input/output device, and the like.

In addition, a memory device or a memory system according to embodiments of the inventive concept may be packaged into one of various types to be embedded later. For example, a flash memory device or a memory system according to various embodiments of the inventive concept may be packaged by one of: PoP (package on package), ball grid array package (BGA), Chip Scale Package (CSP), plastic leaded chip carrier Package (PLCC), dual in-line plastic package (PDIP), Die in Waffle Pack (Die in Wafer Pack), Die in Wafer Form (Die in Wafer Form), chip on board package (COB), dual in-line ceramic package (CERDIP), plastic Metric Quad Flat Package (MQFP), Thin Quad Flat Package (TQFP), small outline package (SOIC), compact small outline package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flat Package (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer level fabricated package (WFP), and Wafer level stacked package (WSP).

As described so far, the unit cell area of the vertical memory device can be reduced, thereby increasing the density of the vertical memory device. Since the number of bit lines can be increased as compared with the conventional art, the page size can be increased and the operation speed can be increased.

Throughout the specification, features shown in one embodiment may be combined with other embodiments within the spirit and scope of the inventive concept.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Various operations may be described as multiple discrete steps performed in a manner that is most helpful in understanding the present invention. However, the order in which the steps are described does not imply that the operations are order dependent or that the order in which the steps are performed must be the order in which the steps occur.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims.

The disclosures of korean patent application No. 10-2012-0110751 filed on 5/2012 and of us patent application No. 13/844,337 filed on 15/3/2013, which are hereby incorporated by reference in their entireties, are claimed in this application.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a plurality of vertically stacked memory cell strings;

forming a single-body interconnect to couple at least two of the plurality of vertically stacked strings of memory cells; and

coupling a bit line to the uni-body interconnect,

wherein coupling the uni-body interconnect to the at least two of the strings of memory cells comprises forming the uni-body interconnect including a body extending in a first direction and a protrusion protruding from the body in a second direction,

wherein the first direction and the second direction are substantially perpendicular to a direction in which the memory cell strings are stacked, an

Wherein the uni-body interconnect has one end coupled to one string of memory cells and another end coupled to another string of memory cells.

2. The method of claim 1, wherein coupling the bitlines to the uni-body interconnect is performed after forming the uni-body interconnect.

3. The method of claim 1, wherein the monogon interconnect has a longitudinal axis and a minor axis, wherein a central portion of the monogon interconnect protrudes in the second direction along the minor axis, and wherein the bit line extends in the first direction along the longitudinal axis.

4. The method of claim 1, wherein the single body interconnect has a first portion having a first longitudinal central axis and a second portion disposed at a central portion of the single body interconnect, the second portion having a second longitudinal central axis parallel to and offset from the first longitudinal central axis.

5. The method of claim 1, wherein the first direction is substantially perpendicular to the second direction.

6. The method of claim 1, wherein the single body interconnect is coupled to the bit line through the protrusion.

7. A semiconductor device, comprising:

a selection line extending in a first direction;

a first vertically stacked memory cell string and a second vertically stacked memory cell string arranged in a second direction crossing the first direction, the first vertically stacked memory cell string and the second vertically stacked memory cell string being commonly coupled to the same select line;

first and second bit lines extending in the second direction, the first bit line spaced apart from the second bit line in the first direction;

a first sub-interconnect coupling the first vertically stacked memory cell string to the first bit line; and

a second sub-interconnect serially connecting the second vertically stacked storage units to the second bit line;

wherein the first sub-interconnect has a first protrusion protruding in the first direction, an

Wherein the second sub-interconnect has a second protrusion protruding in a direction opposite to the first direction.

8. The semiconductor device according to claim 7, wherein the selection line, the first sub-interconnect and the second sub-interconnect, and the first bit line and the second bit line are sequentially provided over a substrate,

the first and second strings of vertically stacked memory cells are connected to the substrate,

the first bit line and the second bit line are provided on the first vertically stacked memory cell string and the second vertically stacked memory cell string, an

The first and second sub-interconnects are provided between the first and second vertically stacked memory cell strings and the first and second bit lines.

9. The semiconductor device of claim 7, wherein each of the first sub-interconnect and the second sub-interconnect has a longitudinal axis and a short axis,

a central portion of the first sub-interconnection protrudes in the first direction along the minor axis, an

The central portion of the second sub-interconnect protrudes in a direction opposite to the first direction along the minor axis.

10. The semiconductor device of claim 9, wherein the first sub-interconnect has a length along the longitudinal axis that is shorter than a length along the longitudinal axis of the second sub-interconnect.

11. The semiconductor device of claim 7, wherein the select lines comprise first, second, and third select lines extending in the first direction, the first, second, and third select lines being spaced apart from one another in the second direction, and

wherein the semiconductor device further comprises a third vertically stacked memory cell string and a fourth vertically stacked memory cell string arranged in the second direction, wherein the third vertically stacked memory cell string is coupled to the first select line, the first vertically stacked memory cell string and the second vertically stacked memory cell string are commonly coupled to the second select line, and the fourth vertically stacked memory cell string is coupled to the third select line.

12. The semiconductor device of claim 11, wherein the first sub-interconnect connects the first and third vertically stacked strings of memory cells to the first bit line, an

The second sub-interconnect connects the second vertically stacked memory cell string and the fourth vertically stacked memory cell string to the second bit line.

13. The semiconductor device according to claim 11, wherein the first sub-interconnect is connected to the first bit line through the first protrusion, and the second sub-interconnect is connected to the second bit line through the second protrusion.

14. The semiconductor device of claim 11, further comprising:

a first isolation insulating layer extending in the first direction, the first isolation insulating layer being provided between the first select line and the second select line.

15. The semiconductor device of claim 14, wherein the first protrusion vertically overlaps the first isolation insulating layer.

16. The semiconductor device of claim 15, further comprising:

a second partition insulating layer extending in the first direction, the second partition insulating layer being provided between the second selection line and the third selection line, an

Wherein the second protrusion vertically overlaps the second partition insulating layer.

17. A semiconductor device, comprising:

a selection line extending in a first direction;

a second sub-interconnect serially connecting the second vertically stacked storage units to the second bit line,

wherein the first sub-interconnect has a protrusion protruding in the first direction, an

Wherein the second sub-interconnect has a substantially rectangular shape extending in the second direction in a top view.

18. The semiconductor device according to claim 17, wherein the selection line, the first sub-interconnect and the second sub-interconnect, and the first bit line and the second bit line are sequentially provided over a substrate,

19. The semiconductor device of claim 17, wherein each of the first sub-interconnect and the second sub-interconnect has a longitudinal axis and a short axis,

The second sub-interconnect extends along the second direction without a protrusion.

20. The semiconductor device of claim 19, wherein a length of the first sub-interconnect on the longitudinal axis is different from a length of the second sub-interconnect.

21. The semiconductor device of claim 17, wherein the select lines comprise first, second, and third select lines extending in the first direction, the first, second, and third select lines being spaced apart from one another in the second direction, and

22. The semiconductor device of claim 21, wherein the first sub-interconnect connects the first and third vertically stacked strings of memory cells to the first bit line, an

Wherein the second sub-interconnect connects the second vertically stacked memory cell string and the fourth vertically stacked memory cell string to the second bit line.

23. The semiconductor device according to claim 21, wherein the first sub-interconnect is connected to the first bit line through the protrusion.

24. The semiconductor device of claim 21, further comprising:

25. The semiconductor device of claim 24, wherein the protrusion vertically overlaps the first isolation insulating layer.

26. The semiconductor device of claim 25, further comprising:

a second partition insulating layer extending in the first direction, the second partition insulating layer being provided between the second selection line and the third selection line,

wherein a central portion of the second sub-interconnect vertically overlaps the second partition insulating layer.

27. A semiconductor device, comprising:

first and second selection lines extending in a first direction and spaced apart from each other in a second direction crossing the first direction;

a first vertically stacked memory cell string coupled to the first select line;

a second vertically stacked memory cell string coupled to the second select line;

a first sub-interconnect coupling one of the first vertically stacked strings of memory cells to one of the second vertically stacked strings of memory cells;

a second sub-interconnect adjacent to the first sub-interconnect in the first direction; and

bit lines extending in the second direction and coupled to respective ones of the first sub-interconnect and the second sub-interconnect,

wherein the first sub-interconnect and the second sub-interconnect include respective first and second protrusions protruding in the first direction, an

Wherein a length of the first sub-interconnect in the second direction is different from a length of the second sub-interconnect in the second direction.

28. The semiconductor device as set forth in claim 27,

wherein the first sub-interconnect comprises one among a plurality of first sub-interconnects, the second sub-interconnect comprises one among a plurality of second sub-interconnects, an

Wherein the plurality of first sub-interconnections and the plurality of second sub-interconnections are alternately arranged in the first direction.

29. The semiconductor device of claim 27, further comprising a substrate,

wherein the first and second select lines, the first and second sub-interconnects, and the bit line are sequentially arranged on the substrate,

wherein the bit lines are on the first and second vertically stacked strings of memory cells, an

Wherein the first and second sub-interconnects are between the first and second vertically stacked strings of memory cells and the bit line.

30. The semiconductor device as set forth in claim 27,

wherein each of the first sub-interconnect and the second sub-interconnect has a longitudinal axis and a short axis,

wherein a central portion of the first sub-interconnection protrudes in the first direction along the minor axis, an

Wherein a central portion of the second sub-interconnect protrudes in the first direction along the minor axis.

31. The semiconductor device of claim 30, wherein the first sub-interconnect comprises a shorter length along the longitudinal axis relative to the second sub-interconnect.

32. The semiconductor device of claim 27, wherein the first and second sub-interconnects are connected to the bit line through the respective first and second protrusions.

33. The semiconductor device of claim 27, further comprising:

a separation insulating layer between the first selection line and the second selection line and extending in the first direction,

wherein at least one of the first protrusion and the second protrusion vertically overlaps the separation insulating layer.

34. The semiconductor device of claim 27, further comprising:

a third selection line extending in the first direction;

a third vertically stacked memory cell string coupled to the third select line; and

a third sub-interconnect that couples one of the third string of vertically stacked memory cells to one of the second string of vertically stacked memory cells.

35. The semiconductor device as set forth in claim 34,

wherein the third sub-interconnect includes a third protrusion protruding in a direction opposite to the first direction.

36. The semiconductor device of claim 35, further comprising:

a first isolation layer between the first and second select lines and extending in the first direction; and

a second partition insulating layer between the second selection line and the third selection line and extending in the first direction,

wherein the first protrusion and the second protrusion vertically overlap the first separation insulating layer, an

Wherein the third protrusion vertically overlaps the second partition insulating layer.