KR102265240B1 - Memory device - Google Patents

Abstract

A memory device is provided. The memory device extends in a first direction and is coupled to first to third selection lines sequentially arranged in a second direction intersecting the first direction, each of the selection lines, and is sequentially arranged in the second direction first to third vertical pillars, a first auxiliary line connecting the third vertical pillar coupled to the first selection line and the first vertical pillar coupled to the second selection line, and the second selection line and a second auxiliary line connecting the third vertical pillar coupled to the first vertical pillar coupled to the third selection line, and a bit line connected to the auxiliary lines and extending in the second direction. .

Description

memory device {MEMORY DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a vertical memory device.

In order to meet excellent performance and low price, it is required to increase the degree of integration of semiconductor devices. In particular, the density of the memory device is an important factor determining the price of a product. Since the degree of integration of the conventional two-dimensional memory device is mainly determined by the area occupied by the unit memory cell, it is greatly affected by the level of the fine pattern forming technology. However, since ultra-expensive equipment is required for pattern miniaturization, the degree of integration of the 2D semiconductor memory device is increasing, but is still limited.

An object of the present invention is to provide a vertical memory device that is more highly integrated and has a high operating speed.

A memory device is disclosed. The memory device includes: first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction; first to third vertical pillars coupled to each of the selection lines and arranged in order in the second direction; a first auxiliary line connecting the third vertical pillar coupled to the first selection line and the first vertical pillar coupled to the second selection line; a second auxiliary line connecting the third vertical pillar coupled to the second selection line and the first vertical pillar coupled to the third selection line; and a bit line connected to the auxiliary lines and extending in the second direction.

For example, the bit line includes first to third bit lines immediately adjacent in the first direction, the first bit line is connected to the first auxiliary line, and the second bit line is the second vertical line. It may be connected to a pillar, and the third bit line may be connected to the second auxiliary line.

For example, the apparatus may further include a third auxiliary line connected to the second vertical pillar coupled to each of the selection lines, wherein the second bit line is connected to the second vertical pillar through the third auxiliary line. .

For example, the first and second auxiliary wires are connected to the first and third vertical pillars through first and third lower contacts, and the first and third bit lines are connected to first and third upper contacts. Each of the first and second auxiliary lines may be connected to the first and second auxiliary lines, and the second bit line may be connected to the second vertical column through a second lower contact and a second upper contact that are in contact with each other.

For example, in the memory device, the selection lines are provided on a substrate, and the memory device further includes a cell gate between the selection lines and the substrate, and the vertical pillars pass through the selection lines and the cell gate. , may be connected to the substrate.

For example, the memory device may further include a charge storage element provided between the vertical pillars and the cell gate.

The memory device includes a plurality of selection lines extending in a first direction and spaced apart from each other in a second direction crossing the first direction and having a plurality of vertical pillars coupled thereto, the selection lines being adjacent to each other and extending in the second direction first to third selection lines arranged in order according to the auxiliary wiring extending on the adjacent selection lines; and a bit line connected to the auxiliary line and extending in the second direction, wherein the vertical columns coupled to each of the selection lines are arranged in a zigzag manner, and first to second bit lines are sequentially arranged along the second direction. It may include first to fifth vertical columns respectively arranged in five columns.

For example, the second vertical pillar is shifted by a first distance from the first vertical pillar in the first direction, and the third vertical pillar is shifted by the first distance from the second vertical pillar in the first direction and the fourth vertical pillar is shifted by the first distance from the third vertical pillar in the first direction, and the fifth vertical pillar is shifted by the first distance from the fourth vertical pillar in the first direction. can be placed.

For example, the first vertical pillar coupled to the second selection line may be shifted by a first distance from the first vertical pillar coupled to the first selection line in the first direction.

For example, the auxiliary wiring may include: a first auxiliary wiring connecting a fourth vertical pillar of the first selection line and a first vertical pillar of the second selection line; a second auxiliary line connecting a fifth vertical pillar of the second selection line and a second vertical pillar of the third selection line; a third auxiliary line connecting a fifth vertical pillar of the first selection line and a second vertical pillar of the second selection line; and a fourth auxiliary line connecting the fourth vertical pillar of the second selection line and the first vertical pillar of the third selection line.

For example, the memory device may further include a fifth auxiliary line connected to the third vertical pillar coupled to each of the selection lines.

For example, the bit line may include first to fifth bit lines immediately adjacent in the first direction, and the first to fifth auxiliary lines may be connected to different bit lines.

For example, the auxiliary wirings are respectively connected to the vertical pillars through lower contacts disposed on the vertical pillars, and the bit lines are respectively connected to the auxiliary wirings through upper contacts disposed on the auxiliary wirings. can be connected

For example, the bit line may include first to fifth bit lines immediately adjacent in order in the first direction, and the first to fourth auxiliary wirings may include the first, second, fourth, and fifth vertical pillars. are connected to the first, second, fourth, and fifth vertical pillars through first lower contacts respectively disposed on the plurality of bit lines, and four of the bit lines are disposed on the first to fourth auxiliary lines. are respectively connected to the first to fourth auxiliary wirings through first upper contacts respectively disposed on the , and the other one of the bit lines is in contact with each other on the third vertical pillar coupled to each of the selection lines. It may be connected to the third vertical pillar through a second lower contact and a second upper contact.

As an example, the vertical pillars coupled to each of the selection lines further include a sixth vertical pillar disposed along a sixth column after the fifth column, and the sixth vertical pillar is the fifth vertical pillar from the fifth vertical pillar. It may be arranged to be shifted by the first distance in one direction.

For example, the auxiliary wiring may include: a first auxiliary wiring connecting a fifth vertical pillar of the first selection line and a first vertical pillar of the second selection line; a second auxiliary line connecting a fifth vertical pillar of the second selection line and a first vertical pillar of the third selection line; a third auxiliary line connecting a sixth vertical pillar of the first selection line and a second vertical pillar of the second selection line; and a fourth auxiliary line connecting the sixth vertical pillar of the second selection line and the second vertical pillar of the third selection line.

For example, the memory device may include: a fifth auxiliary line connected to the third vertical pillar coupled to each of the selection lines; and a sixth auxiliary line connected to the fourth vertical pillar coupled to each of the selection lines.

For example, the bit line may include first to sixth bit lines immediately adjacent in the first direction, and the first to sixth auxiliary wires may be connected to different bit lines.

For example, the auxiliary wirings are respectively connected to the vertical pillars through lower contacts disposed on the vertical pillars, and the bit lines are respectively connected to the auxiliary wirings through upper contacts disposed on the auxiliary wirings. can be connected

For example, the bit line may include first to sixth bit lines immediately adjacent in order in the first direction, and the first to fourth auxiliary lines may include the first, second, fifth, and sixth vertical pillars. The first, second, fifth, and sixth vertical pillars are respectively connected to the first, second, fifth and sixth vertical pillars through first lower contacts disposed on the first, second, fifth, and sixth vertical pillars, and the first, fourth, sixth and third bit lines are connected to the first to Each of the first to fourth auxiliary lines is connected to the first to fourth auxiliary lines through first upper contacts disposed on fourth auxiliary lines, and the second bit line is connected to each other on the third vertical pillar coupled to each of the selection lines. connected to the third vertical column through a second lower contact and a second upper contact that are in contact with each other, and the fifth bit line is a third lower contact and a third upper portion on the fourth vertical column coupled to each of the selection lines It may be connected to the fourth vertical pillar through a contact.

The memory device includes a plurality of selection lines extending in a first direction and spaced apart from each other in a second direction crossing the first direction and having a plurality of vertical pillars coupled thereto, the selection lines being adjacent to each other and extending in the second direction first to third selection lines arranged in order according to the auxiliary wiring extending on the adjacent selection lines; and a bit line connected to the auxiliary wiring and extending in the second direction, wherein the vertical columns coupled to each of the selection lines are arranged in a matrix, and first to second bit lines are sequentially arranged along the second direction. It may include first to third vertical columns respectively arranged in three rows.

For example, the auxiliary wiring may include: a first auxiliary wiring connecting a third vertical pillar coupled to the first selection line and a first vertical pillar coupled to the second selection line; and a second auxiliary line connecting a third vertical pillar coupled to the second selection line and a first vertical pillar coupled to the third selection line.

As an example, the memory device may further include third auxiliary wires connected to the second vertical pillar coupled to each of the selection lines.

For example, the bit line may include first to third bit lines immediately adjacent in the first direction, and the first to third auxiliary lines may be connected to different bit lines.

For example, the auxiliary wirings are respectively connected to the vertical pillars through lower contacts disposed on the vertical pillars, and the bit lines are respectively connected to the auxiliary wirings through upper contacts disposed on the auxiliary wirings. can be connected

For example, the bit line may include first to third bit lines immediately adjacent in order in the first direction, and the first and second auxiliary lines may be disposed on the first and third vertical pillars. It is respectively connected to the first and third vertical pillars through 1 lower contacts, and two of the bit lines are connected to the first and third vertical pillars through first upper contacts disposed on the first and second auxiliary lines. are respectively connected to second auxiliary wirings, and the other one of the bit lines is connected to the second vertical column through a second lower contact and a second upper contact which are in contact with each other on the second vertical pillar coupled to each of the selection lines. It can be connected to a pole.

The memory device includes: first and second vertical pillars coupled to one selection line extending in a first direction and sequentially arranged in a second direction orthogonal to the first direction; a first auxiliary line connected to the first vertical pillar through a first lower contact on the first vertical pillar; a second auxiliary line connected to the second vertical pillar through a second lower contact on the second vertical pillar; a first bit line connected to the first auxiliary line through a first upper contact offset from the first vertical pillar in the first direction and extending in the second direction; and a second bit line connected to the second auxiliary line through a second upper contact offset from the second vertical pillar in a direction opposite to the first direction and extending in the second direction.

For example, the memory device may include a third vertical pillar between the first vertical pillar and the second vertical pillar; and a third bit line connected to the third vertical pillar through a third lower contact and a third upper contact overlapping the third vertical pillar, and between the first bit line and the second bit line. can do.

According to the concept of the present invention, the unit cell area of the vertical memory device may be reduced, and thus the degree of integration may be increased. Compared to the general technique, the number of bit lines may increase to increase the page size. Along with this, the operating speed may be increased.

1 is a block diagram illustrating a memory device according to embodiments according to the concept of the present invention.
FIG. 2 is a block diagram illustrating an example of the memory cell array of FIG. 1 .
3 is a perspective view of a memory block of a vertical memory device according to an example of the first embodiment according to the concept of the present invention.
4A to 4I are enlarged views of FIG. 3A .
FIG. 5A is a plan view of the vertical memory device of FIG. 3 , and FIG. 5B is a cross-sectional view taken along line II′ of FIG. 5A .
6A to 11A and 6B to 11B illustrate a process of forming a vertical memory device according to an example of the first embodiment according to the concept of the present invention, and FIGS. 6A to 11A are diagrams corresponding to FIG. 5A It is a plan view, and FIGS. 6B to 11B are cross-sectional views corresponding to FIG. 5B.
12A is a plan view of a vertical memory device according to another example of the first embodiment according to the inventive concept, and FIG. 12B is a cross-sectional view taken along line II′ of FIG. 12A.
13A is a plan view of a vertical memory device according to an example of the second embodiment according to the concept of the present invention, and FIG. 13B is a cross-sectional view taken along line II′ of FIG. 13A.
14 is a plan view of a vertical memory device according to another example of the second embodiment according to the concept of the present invention.
15A is a plan view of a vertical memory device according to an example of a third embodiment according to the concept of the present invention, and FIG. 15B is a cross-sectional view taken along line II′ of FIG. 15A.
16A is a plan view of a vertical memory device according to another example of the third embodiment according to the inventive concept, and FIG. 16B is a cross-sectional view taken along line II′ of FIG. 16A.
17 is a plan view of a vertical memory device according to still another example of the third embodiment according to the concept of the present invention.
18 is a plan view of a vertical memory device according to an example of a fourth embodiment according to the concept of the present invention.
19 is a plan view of a vertical memory device according to another example of the fourth embodiment according to the concept of the present invention.
20 is a plan view of a vertical memory device according to still another example of the fourth embodiment according to the concept of the present invention.
21 is a plan view of a vertical memory device according to an example of the fifth embodiment according to the concept of the present invention.
22 is a plan view of a vertical memory device according to another example of the fifth embodiment according to the concept of the present invention.
23 is a plan view of a vertical memory device according to still another example of the fifth embodiment according to the concept of the present invention.
24 is a schematic block diagram illustrating an example of a memory system including a semiconductor device formed according to embodiments according to the inventive concept.
25 is a schematic block diagram illustrating an example of a memory card including a semiconductor device formed according to embodiments according to the inventive concept.
26 is a schematic block diagram illustrating an example of an information processing system equipped with a semiconductor device formed according to embodiments according to the inventive concept.

The above objects, other objects, features and advantages of the present invention will be easily understood through the following preferred embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed subject matter may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

In this specification, when a film (or layer) is referred to as being on another film (or layer) or substrate, it may be formed directly on the other film (or layer) 3 or the substrate or a third layer between them. A film (or layer) may be interposed. In addition, in the drawings, the sizes and thicknesses of components are exaggerated for clarity. Also, in various embodiments of the present specification, the terms first, second, third, etc. are used to describe various regions, films (or layers), etc., but these regions and films are limited by these terms. it shouldn't be These terms are only used to distinguish one region or film (or layer) from another region or film (or layer). Each embodiment described and illustrated herein also includes a complementary embodiment thereof. In the present specification, the expression 'and/or' is used to mean including at least one of the elements listed before and after. Parts indicated with like reference numerals throughout the specification indicate like elements.

Hereinafter, embodiments according to the concept of the present invention will be described in detail with reference to the drawings.

1 is a block diagram illustrating a memory device according to embodiments according to the concept of the present invention. Referring to FIG. 1 , a memory device according to example embodiments includes a memory cell array 10 , an address decoder 20 , a read/write circuit 30 , a data input/output circuit 40 , and a control logic 50 . ) may be included.

The memory cell array 10 may be connected to the address decoder 20 through a plurality of word lines WL, and may be connected to the read/write circuit 30 through bit lines BL. The memory cell array 10 includes a plurality of memory cells. For example, the memory cell array 10 is configured to store one or more bits per cell.

The address decoder 20 may be connected to the memory cell array 10 through word lines WL. The address decoder 20 is configured to operate in response to the control of the control logic 50 . The address decoder 20 may receive the address ADDR from the outside. The address decoder 20 decodes a row address among the received addresses ADDR and selects a corresponding word line from among the plurality of word lines WL. Also, the address decoder 20 decodes a column address among the received addresses ADDR and transmits the decoded column address to the read/write circuit 30 . For example, the address decoder 20 may include well-known components such as a row decoder, a column decoder, an address buffer, and the like.

The read/write circuit 30 may be connected to the memory cell array 10 through bit lines BL, and may be connected to the data input/output circuit 40 through data lines D/L. The read/write circuit 30 may operate in response to the control of the control logic 50 . The read/write circuit 30 is configured to receive the decoded column address from the address decoder 20 . Using the decoded column address, the read/write circuit 30 selects the bit line BL. For example, the read/write circuit 30 receives data from the data input/output circuit 40 and writes the received data to the memory cell array 10 . The read/write circuit 30 reads data from the memory cell array 10 and transfers the read data to the data input/output circuit 40 . The read/write circuit 30 reads data from the first storage area of the memory cell array 10 and writes the read data into the second storage area of the memory cell array 10 . For example, the read/write circuit 30 may be configured to perform a copy-back operation.

The read/write circuit 30 may include components including a page buffer (or page register) and a column selection circuit. As another example, the read/write circuit 30 may include components including a sense amplifier, a write driver, and a column selection circuit.

The data input/output circuit 40 may be connected to the read/write circuit 30 through data lines DL. The data input/output circuit 40 operates in response to the control of the control logic 50 . The data input/output circuit 40 is configured to exchange data DATA with the outside. The data input/output circuit 40 is configured to transmit data DATA transmitted from the outside to the read/write circuit 30 through the data lines DL. The data input/output circuit 40 is configured to output data DATA transferred from the read and write circuits through the data lines DL to the outside. For example, the data input/output circuit 40 may include components such as a data buffer.

The control logic 50 may be connected to the address decoder 20 , the read/write circuit 30 , and the data input/output circuit 40 . The control logic 50 is configured to control the operation of the semiconductor device. The control logic 50 may operate in response to a control signal CTRL transmitted from the outside.

FIG. 2 is a block diagram illustrating an example of the memory cell array 10 of FIG. 1 . Referring to FIG. 2 , the memory cell array 10 may include a plurality of memory blocks BLK1 to BLKn. Each memory block may have a three-dimensional structure (or a vertical structure). For example, each memory block may include structures extending in first to third directions crossing each other. For example, each memory block includes a plurality of cell strings extending in the third direction.

3 is a perspective view of a memory block of a vertical memory device according to an example of the first embodiment according to the concept of the present invention. 4A to 4I are enlarged views of FIG. 3A .

Referring to FIG. 3 , a substrate 110 is provided. The substrate 110 may have a first conductivity type, for example, a P-type. Gate structures GL may be provided on the substrate 110 . A buffer dielectric layer 121 may be provided between the substrate 110 and the gate structures GL. The buffer dielectric layer 121 may be a silicon oxide layer.

The gate structures GL may extend in the first direction. The gate structures GL may face each other in a second direction crossing (eg, orthogonal to) the first direction. The gate structures GL may include insulating patterns 125 and gate electrodes spaced apart from each other with insulating patterns interposed therebetween. The gate electrodes may include first to sixth gate electrodes G1 to G6 sequentially stacked on the substrate 110 . The insulating patterns 125 may be silicon oxide layers. The buffer dielectric layer 121 may be thinner than the insulating patterns 125 . The gate electrodes G1 to G6 may include doped silicon, metal (eg, tungsten), metal nitride, metal silicides, or a combination thereof. Although the drawing shows that there are six gate electrodes, the number of gate electrodes is not limited thereto and more may be used.

An isolation region 131 extending in the first direction may be provided between the gate structures GL. The isolation region 131 may be filled with a first isolation insulating layer (not shown, refer to 141 of FIG. 5B ). The common source lines CSL are provided on the substrate 110 of the isolation region 131 . The common source lines CSL may be spaced apart from each other and extend in the first direction within the substrate 110 . The common source lines CSL may have a second conductivity type (eg, N-type) different from the first conductivity type. Unlike the drawings, the common source lines CSL may be provided between the substrate 110 and the first gate electrode G1 and may have a line-shaped pattern extending in the first direction.

Vertical pillars PL arranged in a matrix in the first direction and the second direction are provided. A plurality of vertical pillars PL may be coupled to the gate structures GL. The plurality of vertical pillars PL may pass through the gate electrodes G1 to G6 to be connected to the substrate 110 . The vertical pillars PL may have a long axis extending upward from the substrate 110 (ie, extending in the third direction). One ends of the vertical pillars PL may be connected to the substrate 110 , and other ends thereof may be connected to the first and second bit lines BL1 and BL2 extending in the second direction.

Auxiliary lines SBL1 and SBL2 may be provided between the vertical pillars PL and the bit lines BL1 and BL2. The auxiliary lines SBL1 and SBL2 may be connected to the vertical pillars PL coupled to the immediately adjacent gate structures GL through the lower contacts 152 . The bit lines BL1 and BL2 may be connected to the auxiliary lines SBL1 and SBL2 through the upper contacts 154a and 154b.

A plurality of cell strings of the flash memory device are provided between the bit lines BL1 and BL2 and the common source lines CSL. One cell string includes a string select transistor connected to the bit lines BL1 and BL2, a ground select transistor connected to the common source lines CSL, and a plurality of memories provided between the string select transistor and the ground select transistor. It may contain cells. The selection transistors and the plurality of memory cells are provided on one semiconductor pillar PL. The first gate electrode G1 may be the ground select gate GSL of the ground select transistor. The second to fifth gate electrodes G2 to G5 may be cell gates WL of a plurality of memory cells. The sixth gate electrode G6 may be a string select gate line SSL of the string select transistor.

An information storage element 135 may be provided between the first to sixth gate electrodes G1 to G6 and the vertical pillars PL. 3 illustrates that the data storage element 135 extends between the gate electrodes G1 to G6 and the insulating patterns 125 and extends between the gate electrodes G1 to G6 and the vertical pillars PL. , but not limited thereto. It may be variously modified in the examples to be described later (see FIGS. 4A to 4I).

In one aspect, the vertical pillars PL may be semiconductor pillars including a semiconductor material. The vertical pillars PL may function as channels. The vertical pillars PL may have a hollow cylinder shape or a hollow cylinder shape (eg, macaroni shape). The inside of the macaroni type vertical pillars may be filled with a filling insulating layer 127. Filling insulating layer 127 may be formed of a silicon oxide layer.The filling insulating layer 127 directly contacts inner walls of the vertical pillars PL. Conductive patterns 128 are provided on one end of the vertical pillars PL. One end of the vertical pillars PL contacting the conductive patterns 128 may be a drain region. For example, referring to FIG. 4A , as shown in FIG. It may include a blocking insulating layer 135c adjacent to the gate electrodes G1 to G6, a tunnel insulating layer 135a adjacent to the vertical pillars PL, and a charge storage layer 135b therebetween. ) may extend between the gate electrodes G1 to G6 and the insulating patterns 125. The blocking insulating layer 135c may include a high dielectric layer (eg, an aluminum oxide layer or a hafnium oxide layer). Reference numeral 135c may be a multilayer film including a plurality of thin films.For example, the blocking insulating film 135c may include an aluminum oxide film and/or a hafnium oxide film, and the stacking order of the aluminum oxide film and the hafnium oxide film may vary. The charge storage layer 135b may be a charge trap layer or an insulating layer including conductive nanoparticles.The charge trap layer may include, for example, a silicon nitride layer. The tunnel insulating layer 135a includes a silicon oxide layer. As another example, referring to FIGS. 4B to 4D , at least a portion of the data storage element 135 may extend between the insulating patterns 125 and the vertical pillars PL, unlike that shown in FIG. 4B , the tunnel insulating layer 135a extends between the insulating patterns 125 and the vertical pillars PL, and the charge storage layer 135b and the blocking insulating layer 135c are the insulating patterns 125 . and gate It may extend between the electrodes G1 to G6. Referring to FIG. 4C , the tunnel insulating layer 135a and the charge storage layer 135b extend between the insulating patterns 125 and the vertical pillars PL, and the blocking insulating layer 135c is formed between the insulating patterns 125 and the gate. It may extend between the electrodes G1 to G6. Referring to FIG. 4D , the tunnel insulating layer 135a , the charge storage layer 135b , and the blocking insulating layer 135c may extend between the insulating patterns 125 and the vertical pillars PL. Unlike the above-described examples, referring to FIG. 4E , the charge storage layer 135b may be polysilicon. In this case, the charge storage layer 135b and the blocking insulating layer 135c may be defined between the gate electrodes G1 to G6 and the vertical pillars PL.

In another aspect, the vertical pillars PL may be conductive pillars. The vertical pillars PL may include at least one of conductive materials (eg, doped semiconductors, metals, conductive metal nitrides, silicides, or nanostructures (such as carbon nanotubes or graphene)). Referring to FIG. 4F , unlike that shown in FIG. 3 , the data storage element 135 may be defined between the gate electrodes G1 to G6 and the vertical pillars PL. 4G and 4H , the data storage element 135 is disposed between the insulating patterns 125 and the vertical pillars PL or between the insulating patterns 125 and the gate electrodes G1 to G6. can be extended In this case, the data storage element 135 may be a variable resistance pattern. The variable resistance pattern may include at least one of materials having a variable resistance characteristic, whose resistance can be changed. Hereinafter, examples of the variable resistance pattern used as the information storage element 135 will be described.

For example, the data storage element 135 may include a material (eg, a phase change material) whose electrical resistance can be changed by heat generated by a current passing through an electrode adjacent thereto. The phase change material may include at least one of antimony (Sb), tellurium (Te), and selenium (Se). For example, the phase change material may include, wherein tellurium (Te) has a concentration of about 20 atomic percent to about 80 atomic percent, antimony (Sb) has a concentration of about 5 atomic percent to about 50 atomic percent, and the remainder It may include a chalcogen compound that is germanium (Ge). In addition, the phase change material may include at least one of N, O, C, Bi, In, B, Sn, Si, Ti, Al, Ni, Fe, Dy, and La as impurities. Alternatively, the variable resistance pattern may be formed of one of GeBiTe, InSb, GeSb, and GaSb.

As another example, the data storage element 135 may be formed to have a thin film structure whose electrical resistance can be changed by using a spin transfer process by a current passing therethrough. The data storage element 135 may have a thin film structure configured to exhibit magnetoresistance characteristics, and may include at least one ferromagnetic material and/or at least one antiferromagnetic material.

As another example, the data storage element 135 may include at least one of perovskite compounds or transition metal oxides. For example, the data storage element 135 may include niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO ((Pr) ,Ca)MnO3), strontium-titanium oxide, barium-strontium-titanium oxide, strontium-zirconium oxide, barium-zirconium oxide zirconium oxide), or at least one of barium-strontium-zirconium oxide and the like.

According to some examples of the present invention, with reference to FIG. 4I , between the data storage element 135 and the gate electrodes G1 to G6, at least one of materials having a self-rectifying property (SW) , for example a PN junction diode) may be provided.

FIG. 5A is a plan view of the vertical memory device of FIG. 3 . 5B is a cross-sectional view taken along line I-I' of FIG. 5A. 5A and 5B, a vertical memory device according to an example of the first embodiment of the present invention will be described in more detail.

5A and 5B , the gate structures GL may include first and second gate structures GL1 and GL2 adjacent to each other. The sixth gate electrode G6 of the first gate structure GL1 is the first string select line SSL1 , and the sixth gate electrode G6 of the second gate structure GL2 is the second string select line SSL2 . can be named as The first and second string selection lines SSL1 and SSL2 may be alternately disposed along the second direction.

The vertical pillars coupled to each of the string selection lines may include a first vertical pillar PL1 and a second vertical pillar PL2 respectively disposed in first and second columns sequentially arranged in the second direction. The first and second vertical pillars PL1 and PL2 may be arranged in a matrix in the first direction and the second direction. Vertical pillars immediately adjacent in the first direction may be spaced apart by, for example, one pitch of the bit lines BL1 and BL2.

The auxiliary wires may connect the vertical pillars PL1 and PL2 coupled to the immediately adjacent first and second string selection lines SSL1 and SSL2, respectively, one-to-one. The auxiliary lines may include a first auxiliary line SBL1 and a second auxiliary line SBL2 . Accordingly, the auxiliary wirings may be connected to the vertical pillars PL1 and PL2 coupled to different string selection lines. For example, the first auxiliary line SBL1 connects the second vertical pillar PL2 of one first string selection line SSL1 and the first vertical pillar PL1 of the second string selection line SSL2, , the second auxiliary line SBL2 may connect the second vertical pillar PL2 of the second string selection line SSL2 and the first vertical pillar PL1 of the other first string selection line SSL1 .

The auxiliary lines SBL1 and SBL2 may be connected to the vertical pillars PL1 and PL2 through the lower contacts 152 . The lower contacts 152 may be respectively overlapped on the vertical pillars PL1 and PL2 . The first auxiliary line SBL1 and the second auxiliary line SBL2 may extend in the second direction. The first auxiliary wiring SBL1 may have a first protrusion P1 protruding in a first direction, and the second auxiliary wiring SBL2 may have a second protrusion P2 protruding in a direction opposite to the first direction. have. The protrusions P1 and P2 may extend on the isolation insulating layer 141 between the gate structures GL1 and GL2 .

The plurality of first auxiliary wires SBL1 may be disposed along the first direction. The plurality of second auxiliary wires SBL2 may be disposed along the first direction. The first and second auxiliary wires SBL1 and SBL2 may be alternately disposed along the second direction. The first auxiliary lines SBL1 and the second auxiliary lines SBL2 are connected to different bit lines adjacent to each other. For example, the plurality of first auxiliary lines SBL1 may be connected to the first bit line BL1 , and the plurality of second auxiliary lines SBL2 may be connected to the second bit line BL2 .

The bit lines BL1 and BL2 may be respectively connected to the auxiliary lines SBL1 and SBL2 through the upper contacts 154a and 154b. The upper contacts 154a and 154b may be disposed on the isolation insulating layer 141 between the gate structures GL1 and GL2 . The first upper contact 154a on the first auxiliary line SBL1 is shifted from the lower contacts 152 in the first direction, for example, by 1/2 a pitch of each of the bit lines BL1 and BL2, The second upper contact 154b on the second auxiliary line SBL2 is shifted from the lower contacts 152 in a direction opposite to the first direction, for example, by a half pitch of each of the bit lines BL1 and BL2. can The upper contacts 154a and 154b may be disposed on the protrusions P1 and P2 .

A method of forming the vertical memory device of FIG. 3 is described. 6A to 11A are plan views corresponding to FIG. 5A , and FIGS. 6B to 11B are cross-sectional views corresponding to FIG. 5B .

6A and 6B , a substrate 110 is provided. The substrate 110 may have a first conductivity type, for example, a P-type conductivity type. A buffer dielectric layer 121 may be formed on the substrate 110 . The buffer dielectric layer 121 may be, for example, a silicon oxide layer. The buffer dielectric layer 121 may be formed by, for example, a thermal oxidation process. Sacrificial layers 123 and insulating layers 124 are alternately stacked on the buffer dielectric layer 121 to provide. The thickness of the uppermost insulating layer 124 ′ may be thicker than that of other insulating layers. The insulating layers 124 may be, for example, silicon oxide layers. The sacrificial layers 123 may include materials having different wet-etch characteristics from those of the buffer dielectric layer 121 and the insulating layers 124 . The sacrificial layers 123 may include, for example, a silicon nitride layer, a silicon oxynitride layer, a polysilicon layer, or a polysilicon germanium layer. The sacrificial layers 123 and the insulating layers 124 may be formed by, for example, a chemical vapor deposition (CVD) method.

7A and 7B , vertical holes 126 exposing the substrate 110 are formed through the buffer dielectric layer 121 , the sacrificial layers 123 , and the insulating layers 124 . The vertical holes 126 may be disposed like the vertical pillars PL1 and PL2 described with reference to FIG. 5A .

Vertical pillars PL1 and PL2 are formed in the vertical holes 126 . In one aspect, the vertical pillars PL1 and PL2 may be semiconductor layers of the first conductivity type. The semiconductor layer may not completely fill the vertical holes 126 , and an insulating material may be formed on the semiconductor layer to completely fill the vertical holes 126 . The semiconductor layer and the insulating material may be planarized to expose the uppermost insulating layer 124 ′. Accordingly, the cylindrical vertical pillars PL1 and PL2 may be formed in which an empty space therein is filled with the insulating film 127 . The semiconductor layer may be formed to fill the vertical holes 126 . In this case, the filling insulating film may not be required. The upper portions of the vertical pillars PL1 and PL2 may be recessed to be lower than the upper surface 129 of the uppermost insulating layer 124 ′. Conductive patterns 128 may be formed in the vertical holes 126 in which the vertical pillars PL1 and PL2 are recessed. The conductive patterns 128 may be doped polysilicon or metal. Drain regions may be formed by implanting impurity ions of the second conductivity type into upper portions of the conductive patterns 128 and the vertical pillars PL1 and PL2 . The second conductivity type may be, for example, an N-type.

In another aspect, the vertical pillars PL1 and PL2 are at least one of conductive materials (eg, doped semiconductors, metals, conductive metal nitrides, silicides, or nanostructures (such as carbon nanotubes or graphene)). may include.

8A and 8B, the buffer dielectric layer 121, the sacrificial layers 123 and the insulating layers 124 are successively patterned to be spaced apart from each other and extend in the first direction to expose the substrate 110, An isolation region 131 is formed. The patterned insulating layers 124 become insulating patterns 125 .

9A and 9B , the sacrificial layers 123 exposed on the isolation region 131 are selectively removed to form the gate region 133 . The gate region 133 corresponds to a region from which the sacrificial layers 123 are removed, and is defined by vertical pillars PL1 and PL2 and insulating patterns 125 . When the sacrificial layers 123 include a silicon nitride layer or a silicon oxynitride layer, the removal process of the sacrificial layers may be performed using an etching solution containing phosphoric acid. Portions of sidewalls of the vertical pillars PL1 and PL2 are exposed by the gate region 133 .

10A and 10B , the data storage element 135 is formed in the gate region 133 .

In one aspect, the data storage element 135 may include a tunnel insulating layer in contact with the vertical pillars PL1 and PL2 , a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer (see FIG. 4A ). In this case, the vertical pillars PL1 and PL2 may be semiconductor pillars. The tunnel insulating layer may include a silicon oxide layer. The tunnel insulating layer may be formed by thermally oxidizing the vertical pillars PL1 and PL2 exposed in the recess region 133 . Alternatively, the tunnel insulating layer may be formed by an atomic layer lamination method. The charge storage layer may be a charge trap layer or an insulating layer including conductive nanoparticles. The charge trap film may include, for example, a silicon nitride film. The blocking insulating layer may include a high dielectric layer (eg, an aluminum oxide layer or a hafnium oxide layer). The blocking insulating film may be a multilayer film composed of a plurality of thin films. For example, the blocking insulating film may include an aluminum oxide film and a silicon oxide film, and the stacking order of the aluminum oxide film and the silicon oxide film may vary. The charge storage layer and the blocking dielectric layer may be formed by an atomic layer lamination method and/or a chemical vapor deposition method having excellent step application properties. On the contrary, when the data storage element 135 has the structure of FIGS. 4B to 4E , at least one of the tunnel insulating film, the charge storage film, and/or the blocking insulating film constituting the data storage element 135 is formed by vertical pillars PL1 . , PL2 may be formed in the vertical holes 126 before forming.

In another aspect, the data storage element 135 may be a variable resistance pattern. (See FIGS. 4F to 4H ) The variable resistance pattern may include at least one of materials having a variable resistance characteristic whose resistance can be selectively changed by a current passing therethrough. In this case, the vertical pillars PL1 and PL2 include at least one of conductive materials (eg, doped semiconductors, metals, conductive metal nitrides, silicides, or nanostructures (such as carbon nanotubes or graphene)). It may be a conductive pillar including. When the data storage element 135 has the structure of FIG. 4G , the data storage element 135 may be formed in the vertical holes 126 before forming the vertical pillars PL1 and PL2 .

A conductive layer is formed on the data storage element 135 of the gate region 133 . The conductive layer may be formed of at least one of a doped silicon layer, a metal layer (eg, tungsten), a metal nitride layer, or a metal silicide layer. The conductive layer may be formed by an atomic layer deposition method. When the conductive film is a metal silicide film, forming the conductive film includes forming a polysilicon film, removing a part of the polysilicon film adjacent to the isolation region 131 to recess the polysilicon film, and forming a metal film on the recessed polysilicon film forming, heat-treating the metal film, and removing the unreacted metal film. The metal film for the metal silicide film may include tungsten, titanium, cobalt, or nickel.

The conductive layer formed outside the gate region 133 (ie, the isolation region 131 ) is removed. Accordingly, gate electrodes G1 to G6 are formed in the recess region 133 . The gate electrodes G1 to G6 extend in the first direction. The gate structures GL may include gate electrodes G1 to G6. The gate structures GL may include first and second gate structures GL1 and GL2 alternately arranged in the second direction. First and second vertical pillars PL1 and PL2 arranged in a matrix in the first and second directions may be coupled to one gate structure.

The conductive layer formed on the isolation region 131 may be removed to expose the substrate 110 . A high concentration of impurity ions of the second conductivity type may be provided to the exposed substrate 110 to form common source lines CSL.

11A and 11B , an isolation insulating layer 141 filling the isolation region 131 is formed. The lower contacts 152 may be formed to overlap the vertical pillars PL1 and PL2 . Auxiliary lines SBL1 and SBL2 may be formed on the lower contacts 152 . The auxiliary wires SBL1 and SBL2 may connect the vertical pillars PL1 and PL2 coupled to the immediately adjacent string selection lines SSL1 and SSL2, respectively, one-to-one through the lower contacts 152 .

Referring back to FIGS. 5A and 5B , first and second upper contacts 154a and 154b may be respectively formed on the first auxiliary line SBL1 and the second auxiliary line SBL2 . Bit lines may be formed on the first and second upper contacts 154a and 154b. The first auxiliary line SBL1 and the second auxiliary line SBL2 are connected to other adjacent bit lines through the first and second upper contacts 154a and 154b, respectively. The first auxiliary line SBL1 may be connected to the first bit line BL1 through the first upper contact 154a. The second auxiliary line SBL2 may be connected to the second bit line BL2 through the second upper contact 154b.

12A is a plan view of a vertical memory device according to another example of the first embodiment according to the concept of the present invention, and FIG. 12B is a cross-sectional view taken along line II′ of FIG. 12A. A detailed description of technical features overlapping with the example of the first embodiment of the present invention described with reference to FIGS. 3, 5A and 5B will be omitted, and differences will be described in detail.

12A and 12B , the auxiliary lines may include a first auxiliary line SBL1 and a second auxiliary line SBL2 . The first auxiliary line SBL1 may be connected to the first vertical pillar PL1 through the first lower contact 152a overlapped on the first vertical pillar PL1 . The second auxiliary line SBL2 may be connected to the second vertical pillar PL2 through the second lower contact 152b overlapped on the second vertical pillar PL2 .

The plurality of first auxiliary wires SBL1 may be disposed along the first direction. The plurality of second auxiliary wires SBL2 may be disposed along the first direction. The first and second auxiliary wires SBL1 and SBL2 may be alternately disposed along the second direction. The plurality of first auxiliary lines SBL1 and the plurality of second auxiliary lines SBL2 are connected to different bit lines adjacent to each other.

The first auxiliary line SBL1 may be connected to the first bit line BL1 through the first upper contact 154a offset from the first vertical column PL1 in the first direction. The second auxiliary line SBL2 may be connected to the second bit line BL2 through a second upper contact 154b offset from the second vertical column PL2 in a direction opposite to the first direction.

The first upper contact 154a on the first auxiliary line SBL1 is shifted from the first lower contact 152a in the first direction, for example, by 1/2 the pitch of the bit lines BL1 and BL2, The second upper contact 154b on the second auxiliary wiring SBL2 is shifted from the second lower contact 152b in a direction opposite to the first direction, for example, by 1/2 the pitch of the bit lines BL1 and BL2. can

13A is a plan view of a vertical memory device according to an example of a second embodiment according to the concept of the present invention. 13B is a cross-sectional view taken along line I-I' of FIG. 13A. A detailed description of the technical features overlapping with those of the first embodiment of the present invention described with reference to FIGS. 3, 5A and 5B will be omitted, and differences will be described in detail.

13A and 13B , the gate structures GL may include first to third gate structures GL1 to GL3 adjacent to each other. The sixth gate electrode G6 of the first gate structure GL1 is the first string select line SSL1 , and the sixth gate electrode G6 of the second gate structure GL2 is the second string select line SSL2 . , and the sixth gate electrode G6 of the third gate structure GL3 may be referred to as a third string selection line SSL3 . The first to third string selection lines SSL1 to SSL3 may be repeatedly disposed along the second direction.

The vertical pillars coupled to each of the string selection lines are arranged in a zigzag manner and include first to fourth vertical pillars PL1 to PL4 arranged in first to fourth columns sequentially arranged along the second direction. can The second vertical pillar PL2 is shifted by a first distance from the first vertical pillar PL1 in the first direction, and the third vertical pillar PL3 is shifted by a first distance from the second vertical pillar PL2 in the first direction. , and the fourth vertical pillar PL4 may be shifted by a first distance from the third vertical pillar PL3 in the first direction. The first distance may be, for example, two pitches of the bit lines BL1 to BL4. Vertical pillars immediately adjacent in the first direction may be spaced apart from each other in the first direction by, for example, four times the pitch of each of the bit lines BL1 to BL4.

The auxiliary wirings may include first to fourth auxiliary wirings SBL1 to SBL4 . The first auxiliary line SBL1 may connect the fourth vertical pillar PL4 coupled to the first string selection line SSL1 and the first vertical pillar PL1 coupled to the second string selection line SSL2 . The second auxiliary line SBL2 may connect the third vertical pillar PL3 coupled to the second string selection line SSL2 and the second vertical pillar PL2 coupled to the third string selection line SSL3 . The third auxiliary line SBL3 may connect the third vertical pillar PL3 coupled to the first string selection line SSL1 and the second vertical pillar PL2 coupled to the second string selection line SSL2 . The fourth auxiliary line SBL4 may connect the fourth vertical pillar PL4 coupled to the second string selection line SSL2 and the first vertical pillar PL1 coupled to the third string selection line SSL3 .

The auxiliary wires SBL1 to SBL4 may be respectively connected to the vertical pillars PL1 to PL4 through the lower contacts 152 . The lower contacts 152 may be respectively overlapped on the vertical pillars PL1 to PL4 . The first to fourth auxiliary wires SBL1 to SBL4 may extend in the second direction. The first and third auxiliary wirings SBL1 and SBL3 have first and third projections P1 and P3 protruding in the first direction, respectively, and the second and fourth auxiliary wirings SBL2 and SBL4 are Each of the second and fourth protrusions P2 and P4 protruding in a direction opposite to the first direction may be provided. The protrusions P1 to P4 may extend on the isolation insulating layer 141 between the gate structures.

The first auxiliary wiring SBL1 and the third auxiliary wiring SBL3 are alternately arranged along the first direction, and the second auxiliary wiring SBL2 and the fourth auxiliary wiring SBL4 are alternately arranged along the first direction. can be arranged as The first and second auxiliary wires SBL1 and SBL2 may be alternately disposed along the second direction, and the third and fourth auxiliary wires SBL3 and SBL4 may be alternately disposed along the second direction. have. Each of the first to fourth auxiliary lines SBL1 to SBL4 may be connected to four other sequentially arranged bit lines. For example, the plurality of first auxiliary lines SBL1 are connected to the first bit line BL1 , the plurality of second auxiliary lines SBL2 are connected to the second bit line BL2 , and the plurality of The third auxiliary lines SBL3 may be connected to the third bit line BL3 , and the plurality of fourth auxiliary lines SBL4 may be connected to the fourth bit line BL4 . The first to fourth bit lines BL1 to BL4 may extend in the second direction and may be sequentially disposed adjacent to each other in the first direction.

The first to fourth bit lines BL1 to BL4 may be respectively connected to the first to fourth auxiliary lines SBL1 to SBL4 through the upper contacts 154a, 154b, 154c, and 154d. The upper contacts 154a to 154d may be disposed on the protrusions P1 to P4 . For example, the first and third upper contacts 154a and 154c on the first and third auxiliary wirings SBL1 and SBL3 have a half pitch of the bit lines from the lower contacts 152 in the first direction. , and the second and fourth upper contacts 154b and 154d on the second and fourth auxiliary wirings SBL2 and SBL4 move from the lower contacts 152 to one of the bit lines in a direction opposite to the first direction. It can be shifted by /2 pitch.

14 is a plan view of a vertical memory device according to another example of the second embodiment according to the concept of the present invention. The cross section of FIG. 14 may be understood with reference to FIG. 12B . A detailed description of technical features overlapping with those described with reference to FIG. 13 will be omitted, and differences will be described in detail.

Referring to FIG. 14 , the auxiliary wirings may include first to fourth auxiliary wirings SBL1 to SBL4 . The first auxiliary line SBL1 may be connected to the first vertical pillar PL1 through the first lower contact 152a overlapped on the first vertical pillar PL1 . The second auxiliary line SBL2 may be connected to the third vertical pillar PL3 through the third lower contact 152c overlapped on the third vertical pillar PL3 . The third auxiliary line SBL3 may be connected to the second vertical pillar PL2 through the second lower contact 152b overlapped on the second vertical pillar PL2 . The fourth auxiliary line SBL4 may be connected to the fourth vertical pillar PL4 through the fourth lower contact 152d overlapped on the fourth vertical pillar PL4 .

The plurality of first auxiliary wires SBL1 may be disposed along the first direction. The plurality of second auxiliary wires SBL2 may be disposed along the first direction. The plurality of third auxiliary lines SBL may be disposed along the first direction. The plurality of fourth auxiliary wires SBL4 may be disposed along the first direction. The first and second auxiliary wires SBL1 and SBL2 may be alternately disposed along the second direction. The third and fourth auxiliary wires SBL3 and SBL4 may be alternately disposed along the second direction. The first to fourth auxiliary lines SBL1 to SBL4 are connected to other bit lines adjacent to each other.

The plurality of first auxiliary lines SBL1 may be connected to the first bit line BL1 through the first upper contacts 154a offset from the first vertical pillar PL1 in the first direction. The plurality of second auxiliary lines SBL2 may be connected to the second bit line BL2 through the second upper contacts 154b offset from the third vertical pillar PL3 in a direction opposite to the first direction. The plurality of third auxiliary lines SBL3 may be connected to the third bit line BL3 through the third upper contacts 154c offset from the second vertical pillar PL2 in the first direction. The plurality of fourth auxiliary lines SBL4 may be connected to the fourth bit line BL4 through fourth upper contacts 154d offset from the fourth vertical pillar PL4 in a direction opposite to the first direction.

The first upper contacts 154a on the first auxiliary lines SBL1 are shifted from the first lower contact 152a in the first direction, for example, by 1/2 the pitch of the bit lines BL1 to BL4. can The second upper contacts 154b on the second auxiliary lines SBL2 are in a direction opposite to the first direction from the third lower contact 152c, for example, 1/2 the pitch of the bit lines BL1 to BL4. can be shifted by The third upper contacts 154c on the third auxiliary lines SBL3 are shifted from the second lower contact 152b in the first direction, for example, by 1/2 the pitch of the bit lines BL1 to BL4. can The fourth upper contacts 154d on the fourth auxiliary wires SBL4 are in a direction opposite to the first direction from the fourth lower contact 152d, for example, 1/2 the pitch of the bit lines BL1 to BL4. can be shifted by

15A is a plan view of a vertical memory device according to an example of a third embodiment according to the concept of the present invention, and FIG. 15B is a cross-sectional view taken along line II′ of FIG. 15A. A detailed description of the technical features overlapping with those of the first embodiment of the present invention described with reference to FIGS. 3, 5A and 5B will be omitted, and differences will be described in detail.

15A and 15B , the gate structures GL may include first to third gate structures GL1 to GL3 adjacent to each other. The sixth gate electrode G6 of the first gate structure GL1 is the first string select line SSL1 , and the sixth gate electrode G6 of the second gate structure GL2 is the second string select line SSL2 . , and the sixth gate electrode G6 of the third gate structure GL3 may be referred to as a third string selection line SSL3 . The first to third string selection lines SSL1 to SSL3 may be repeatedly disposed along the second direction.

The vertical pillars coupled to each of the string selection lines are first, second, and third vertical pillars PL1 , PL2 and PL3 arranged in first, second, and third columns sequentially arranged in the second direction, respectively. may include. The first to third vertical pillars PL1 to PL3 may be arranged in a matrix in the first direction D1 and the second direction D2 .

The auxiliary lines may include a first auxiliary line SBL1 , a second auxiliary line SBL2 , and a third auxiliary line SBL3 . For example, the first auxiliary line SBL1 connects the third vertical pillar PL3 coupled to the first string selection line SSL1 and the first vertical pillar PL1 coupled to the second string selection line SSL2 . and the third auxiliary line SBL3 connects the third vertical pillar PL3 coupled to the second string selection line SSL2 and the first vertical pillar PL1 coupled to the third string selection line SSL3. can The second auxiliary line SBL2 may be provided to overlap the second vertical column PL2 .

The first to third auxiliary wires SBL1 to SBL3 may be respectively connected to the first to third vertical pillars PL1 to PL3 through the first to third lower contacts 152a to 152c. The lower contacts 152a to 152c may be provided to overlap each of the first to third vertical pillars PL1 to PL3 .

Each of the first auxiliary line SBL1 and the third auxiliary line SBL3 may extend in the second direction. The first auxiliary wiring SBL1 may have a first protrusion P1 protruding in a first direction, and the third auxiliary wiring SBL3 may have a second protrusion P2 protruding in a direction opposite to the first direction. have. The protrusions P1 and P2 may extend on the isolation insulating layer 141 between the gate structures GL1 and GL2 . The second auxiliary line SBL2 may be provided on and adjacent to the second vertical column PL2 .

The plurality of first auxiliary wires SBL1 may be disposed along the first direction. The plurality of second auxiliary wires SBL2 may be disposed along the first direction. The plurality of third auxiliary wires SBL3 may be disposed along the first direction. The first to third auxiliary wires SBL1 to SBL3 may be repeatedly disposed along the second direction. The first auxiliary lines SBL1 , the second auxiliary lines SBL2 , and the third auxiliary lines SBL3 are connected to different bit lines adjacent to each other. For example, the plurality of first auxiliary lines SBL1 are connected to the first bit line BL1 , the plurality of second auxiliary lines SBL2 are connected to the second bit line BL2 , and the plurality of The third auxiliary lines SBL3 may be connected to the third bit line BL3 .

The first to third bit lines BL1 to BL3 may extend in the second direction and may be sequentially arranged in the first direction. The first bit line BL1 may be connected to the plurality of first auxiliary lines SBL1 through the first upper contacts 154a. The second bit line BL2 may be connected to the plurality of second auxiliary lines SBL2 through the second upper contacts 154b. The third bit line BL3 may be connected to the plurality of third auxiliary lines SBL3 through the third upper contacts 154c. The first and third upper contacts 154a and 154c may be disposed on the isolation insulating layer 141 between the gate structures GL1 to GL3 . The first upper contacts 154a are shifted from the first lower contact 152a in the first direction, for example, by one pitch of the bit lines BL1 to BL3, and the third upper contacts 154c are 3 It may be shifted from the lower contact 152c in a direction opposite to the first direction, for example, by one pitch of the bit lines BL1 to BL3. The second upper contacts 154b may be provided to overlap the second vertical pillars PL2 .

16A is a plan view of a vertical memory device according to another example of the third embodiment according to the inventive concept, and FIG. 16B is a cross-sectional view taken along line II′ of FIG. 16A. A detailed description of technical features overlapping with those described with reference to FIGS. 15A and 15B will be omitted, and differences will be described in detail.

16A and 16B , the second auxiliary lines SBL2 may not be formed. The second bit line BL2 may be directly connected to the second vertical pillars PL2 through the second lower contacts 152b and the second upper contacts 154b without the second auxiliary wires SBL2 . have.

17 is a plan view of a vertical memory device according to still another example of the third embodiment according to the concept of the present invention. The cross section of FIG. 17 may be understood with reference to FIG. 12B . A detailed description of technical features overlapping with those described with reference to FIGS. 15A and 15B will be omitted, and differences will be described in detail.

Referring to FIG. 17 , the first bit line BL1 is connected to a plurality of first upper contacts 154a offset from the first vertical pillars PL1 in the first direction by, for example, one pitch of the bit lines. It may be connected to the first auxiliary lines SBL1 . The third bit line BL3 is formed from the third vertical pillars PL3 in a direction opposite to the first direction, for example, through the third upper contacts 154c offset by one pitch of the bit lines. It may be connected to the wirings SBL3 . The second bit line BL2 may be connected to the plurality of second auxiliary lines SBL2 through the second upper contacts 154b overlapped on the second vertical pillars PL2 .

Furthermore, as described with reference to FIGS. 16A and 16B , the second auxiliary lines SBL2 may not be formed. The second bit line BL2 may be directly connected to the second vertical pillars PL2 through the second lower contacts 152b and the second upper contacts 154b without the second auxiliary wires SBL2 . have.

18 is a plan view of a vertical memory device according to an example of a fourth embodiment according to the concept of the present invention. The cross section of FIG. 18 may be understood with reference to FIG. 15B . A detailed description of technical features overlapping with those described with reference to FIGS. 15A and 15B will be omitted, and differences will be described in detail.

Referring to FIG. 18 , the vertical columns coupled to each of the string selection lines are arranged in a zigzag, and first to fifth vertical columns ( PL1 to PL5). The second vertical pillar PL2 is shifted by a first distance from the first vertical pillar PL1 in the first direction, and the third vertical pillar PL3 is shifted by a first distance from the second vertical pillar PL2 in the first direction. is shifted, the fourth vertical pillar PL4 is shifted by a first distance from the third vertical pillar PL3 in the first direction, and the fifth vertical pillar PL5 is shifted from the fourth vertical pillar PL4 in the first direction may be shifted by the first distance. Immediately adjacent vertical pillars may be spaced apart in the first direction by, for example, 5 pitches of the bit lines BL1 to BL4.

The auxiliary wirings may include first to fifth auxiliary wirings SBL1 to SBL5 . The first auxiliary line SBL1 may connect the fourth vertical pillar PL4 coupled to the first string selection line SSL1 and the first vertical pillar PL1 coupled to the second string selection line SSL2 . The second auxiliary line SBL2 may be provided on and adjacent to the second vertical pillar PL2 to be connected to the second vertical pillar PL2 . The third auxiliary line SBL3 may connect the fifth vertical pillar PL5 coupled to the second string selection line SSL2 and the second vertical pillar PL2 coupled to the third string selection line SSL3 . The fourth auxiliary line SBL4 may connect the fifth vertical pillar PL5 coupled to the first string selection line SSL1 and the second vertical pillar PL2 coupled to the second string selection line SSL2 . The fifth auxiliary line SBL5 may connect the fourth vertical pillar PL4 coupled to the second string selection line SSL2 and the first vertical pillar PL1 coupled to the third string selection line SSL3 . The first to fifth auxiliary wires SBL1 to SBL5 may be respectively connected to the first to fifth vertical pillars PL1 to PL5 through the lower contacts 152a, 152b, 152c, 152d, and 152e. The lower contacts 152a , 152b , 152c , 152d , and 152e may be disposed to overlap the first to fifth vertical pillars PL1 to PL5 , respectively.

The first auxiliary wirings SBL1 and the fourth auxiliary wirings SBL4 are alternately arranged along the first direction, and the third auxiliary wirings SBL3 and the fifth auxiliary wirings SBL5 are arranged in the first direction. may be alternately arranged along The first, second, and third auxiliary wires SBL1 , SBL2 , and SBL3 are repeatedly disposed along the second direction, and the fourth and fifth auxiliary wires SBL4 and SBL5 are repeatedly disposed along the second direction. can be placed. The first to fifth auxiliary lines SBL1 to SBL5 may be connected to other adjacent bit lines. For example, the plurality of first auxiliary lines SBL1 are connected to the first bit line BL1 , the plurality of second auxiliary lines SBL2 are connected to the second bit line BL2 , and the third The auxiliary lines SBL3 are connected to the third bit line BL3 , the plurality of fourth auxiliary lines SBL4 are connected to the fourth bit line BL4 , and the plurality of fifth auxiliary lines SBL5 . may be connected to the fifth bit line BL5. The first to fifth bit lines BL1 to BL5 may extend in the second direction and may be sequentially adjacent to each other in the first direction. The first to fifth bit lines BL1 to BL5 are connected to the first to fifth auxiliary wires SBL1 to SBL5 through the first to fifth upper contacts 154a, 154b, 154c, 154d, and 154e. Each can be connected. The first upper contact 154a may be shifted from the first lower contact 152a in the first direction, for example, by one pitch of the bit lines BL1 to BL5. The second upper contact 154b may be provided on the third vertical pillar PL3 . The third upper contact 154c may be shifted from the fifth lower contact 152e in a direction opposite to the first direction, for example, by one pitch of the bit lines BL1 to BL5 . The fourth upper contact 154d may be shifted from the second lower contact 152b in the first direction, for example, by one pitch of the bit lines BL1 to BL5 . The fifth upper contact 154e may be shifted from the fourth lower contact 152d in a direction opposite to the first direction, for example, by one pitch of the bit lines BL1 to BL5 .

19 is a plan view of a vertical memory device according to another example of the fourth embodiment according to the concept of the present invention. The cross section of FIG. 19 may be understood with reference to FIG. 16B . A detailed description of technical features overlapping with those described with reference to FIG. 18 will be omitted, and differences will be described in detail.

Referring to FIG. 19 , the third auxiliary lines SBL3 may not be formed. The third bit line BL3 may be connected to the third vertical pillars PL3 through the second lower contacts 152b and the third upper contacts 154c without the third auxiliary wires SBL3 . .

20 is a plan view of a vertical memory device according to still another example of the fourth embodiment according to the concept of the present invention. The cross section of FIG. 20 may be understood with reference to FIG. 12B . A detailed description of technical features overlapping with those described with reference to FIG. 18 will be omitted, and differences will be described in detail.

Referring to FIG. 20 , each of the first auxiliary wires SBL1 includes a fourth vertical pillar PL4 coupled to the first string selection line SSL1 and a first vertical pillar coupled to the second string selection line SSL2 , respectively. It can be connected to (PL1). The second auxiliary line SBL2 may be disposed on the third vertical pillar PL3 and connected to the third vertical pillar PL3 . Each of the third auxiliary wires SBL3 may be connected to a fifth vertical pillar PL5 coupled to the second string selection line SSL2 and a second vertical pillar PL2 coupled to the third string selection line SSL3 . have. Each of the fourth auxiliary wires SBL4 may be connected to a fifth vertical pillar PL5 coupled to the first string selection line SSL1 and a second vertical pillar PL2 coupled to the second string selection line SSL2 . have. Each of the fifth auxiliary wires SBL5 may be connected to a fourth vertical pillar PL4 coupled to the second string selection line SSL2 and a first vertical pillar PL1 coupled to the third string selection line SSL3 . have.

The first bit line BL1 may be connected to the plurality of first auxiliary lines SBL1 through the first upper contacts 154a offset from the silver first vertical pillars PL1 in the first direction. The second bit line BL2 may be connected to the plurality of second auxiliary lines SBL2 through the second upper contacts 154b overlapped on the third vertical pillars PL3 . The third bit line BL3 may be connected to the plurality of third auxiliary lines SBL3 through third upper contacts 154c offset from the fifth vertical pillars PL5 in a direction opposite to the first direction. . The fourth bit line BL4 may be connected to the plurality of fourth auxiliary lines SBL4 through fourth upper contacts 154d offset from the second vertical pillars PL2 in the first direction. The fifth bit line BL5 may be connected to the plurality of fifth auxiliary wires SBL5 through fifth upper contacts 154e offset from the fourth vertical pillars PL4 in a direction opposite to the first direction. .

Furthermore, as described with reference to FIG. 19 , the second auxiliary lines SBL2 may not be formed. The second bit line BL2 may be directly connected to the third vertical pillars PL3 through the third lower contacts 152c and the second upper contacts 154b without the second auxiliary wires SBL2 . have.

21 is a plan view of a vertical memory device according to an example of the fifth embodiment according to the concept of the present invention. The cross section of FIG. 21 may be understood with reference to FIG. 15B . A detailed description of technical features overlapping with those described with reference to FIG. 18 will be omitted, and differences will be described in detail.

Referring to FIG. 21 , the vertical columns coupled to each of the selection lines are arranged in a zigzag manner, and first to sixth vertical columns PL1 respectively arranged in first to sixth columns sequentially arranged along the second direction. ~ PL6). The second vertical pillar PL2 is shifted by a first distance from the first vertical pillar PL1 in the first direction, and the third vertical pillar PL3 is shifted by a first distance from the second vertical pillar PL2 in the first direction. is shifted, the fourth vertical pillar PL4 is shifted by a first distance from the third vertical pillar PL3 in the first direction, and the fifth vertical pillar PL5 is shifted from the fourth vertical pillar PL4 in the first direction is shifted by the first distance, and the sixth vertical pillar PL6 may be shifted by the first distance from the fifth vertical pillar PL5 in the first direction. Immediately adjacent vertical pillars may be spaced apart from each other by, for example, 6 pitches of the bit lines BL1 to BL6 in the first direction.

The auxiliary wirings may include first to sixth auxiliary wirings SBL1 to SBL6 . The first auxiliary line SBL1 may connect the fifth vertical pillar PL5 of the first string selection line SSL1 and the first vertical pillar PL1 of the second string selection line SSL2 . The second auxiliary line SBL2 may be provided on and adjacent to the third vertical pillar PL3 to be connected to the third vertical pillar PL3 . The third auxiliary line SBL3 may connect the fifth vertical pillar PL5 of the second string selection line SSL2 and the first vertical pillar PL1 of the third string selection line SSL3 . The fourth auxiliary line SBL4 may connect the sixth vertical pillar PL6 of the first string selection line SSL1 and the second vertical pillar PL2 of the second string selection line SSL2 . The fifth auxiliary line SBL5 may be provided on and adjacent to the fourth vertical pillar PL4 to be connected to the fourth vertical pillar PL4 . The sixth auxiliary line SBL6 may connect the sixth vertical pillar PL6 of the second string selection line SSL2 and the second vertical pillar PL2 of the third string selection line SSL3 . The first to sixth auxiliary wires SBL1 to SBL6 may be respectively connected to the first to sixth vertical pillars PL1 to PL6 through the lower contacts 152a, 152b, 152c, 152d, 152e, and 152f. have. The lower contacts 152a, 152b, 152c, 152d, 152e, and 152f may be disposed to overlap the vertical pillars PL1 to PL6.

The first auxiliary wirings SBL1 and the fourth auxiliary wirings SBL4 are alternately arranged along the first direction, and the third auxiliary wirings SBL3 and the sixth auxiliary wirings SBL6 are arranged in the first direction. may be alternately arranged along the The first, second, and third auxiliary wirings SBL1 , SBL2 , and SBL3 are repeatedly disposed along the second direction, and the fourth, fifth, and sixth auxiliary wirings SBL4 , SBL5 , and SBL6 are second It may be repeatedly arranged along the direction. The first to sixth auxiliary lines SBL1 to SBL6 may be connected to other adjacent bit lines. For example, the plurality of first auxiliary lines SBL1 are connected to the first bit line BL1 , the plurality of second auxiliary lines SBL2 are connected to the second bit line BL2 , and the plurality of The third auxiliary lines SBL3 are connected to the third bit line BL3 , the plurality of fourth auxiliary lines SBL4 are connected to the fourth bit line BL4 , and the plurality of fifth auxiliary lines BL3 are connected to each other. SBL5 may be connected to the fifth bit line BL5 , and the plurality of sixth auxiliary lines SBL6 may be connected to the sixth bit line BL6 . The first to sixth bit lines BL1 to BL6 may extend in the second direction and may be disposed immediately adjacent to each other in order in the first direction. The first upper contact 154a may be shifted from the first lower contact 152a in the first direction, for example, by one pitch of the bit lines BL1 to BL6. The second upper contact 154b may be provided on the third vertical pillar PL3 . The third upper contact 154c may be shifted from the fifth lower contact 152e in a direction opposite to the first direction, for example, by one pitch of the bit lines BL1 to BL6. The fourth upper contact 154d may be shifted from the second lower contact 152b in the first direction, for example, by one pitch of the bit lines BL1 to BL6. The fifth upper contact 154e may be provided on the fourth vertical pillar PL4 . The sixth upper contact 154f may be shifted from the sixth lower contact 152f in a direction opposite to the first direction, for example, by one pitch of the bit lines BL1 to BL6. The first to sixth bit lines BL1 to BL6 are connected to the first to sixth auxiliary wires SBL1 to SBL6 through the first to sixth upper contacts 154a, 154b, 154c, 154d, 154e, and 154f. ) can be connected to each.

22 is a plan view of a vertical memory device according to another example of the fourth embodiment according to the concept of the present invention. The cross section of FIG. 22 may be understood with reference to FIG. 16B . A detailed description of technical features overlapping with those described with reference to FIG. 21 will be omitted, and differences will be described in detail.

Referring to FIG. 22 , the second and fifth auxiliary lines SBL2 and SBL5 may not be formed. The second bit line BL2 may be directly connected to the third vertical pillars PL3 through the third lower contacts 152c and the second upper contacts 154b without the second auxiliary line SBL2 . . The fifth bit line BL5 may be directly connected to the fourth vertical pillars PL4 through the fourth lower contacts 152d and the fifth upper contacts 154e without the fifth auxiliary line SBL5 . .

23 is a plan view of a vertical memory device according to still another example of the fourth embodiment according to the concept of the present invention. The cross section of FIG. 23 may be understood with reference to FIG. 12B . A detailed description of technical features overlapping with those described with reference to FIG. 21 will be omitted, and differences will be described in detail.

Referring to FIG. 23 , each of the first auxiliary wires SBL1 may be connected to a first vertical column PL1 coupled to the first string selection line SSL1 . The second auxiliary line SBL2 may be disposed on the second vertical pillar PL2 and connected to the second vertical pillar PL2 . Each of the third auxiliary wires SBL3 may be connected to a third vertical column PL3 coupled to the third string selection line SSL3 . Each of the fourth auxiliary lines SBL4 may be connected to the fourth string selection line SSL4 . Each of the fifth auxiliary wires SBL5 may be connected to a fifth vertical column PL5 coupled to the fifth string selection line SSL5 .

The first bit line BL1 may be connected to the plurality of first auxiliary lines SBL1 through the first upper contacts 154a offset from the first vertical pillars PL1 in the first direction. The second bit line BL2 may be connected to the plurality of second auxiliary lines SBL2 through the second upper contacts 154b overlapped on the third vertical pillars PL3 . The third bit line BL3 may be connected to the plurality of third auxiliary lines SBL3 through third upper contacts 154c offset from the fifth vertical pillars PL5 in a direction opposite to the first direction. . The fourth bit line BL4 may be connected to the plurality of fourth auxiliary lines SBL4 through fourth upper contacts 154d offset from the second vertical pillars PL2 in the first direction. The fifth bit line BL5 may be connected to the plurality of fifth auxiliary wires SBL5 through fifth upper contacts 154e overlapped on the fourth vertical pillars PL4 . The sixth bit line BL6 may be connected to the plurality of sixth auxiliary wires SBL6 through sixth upper contacts 154f offset from the sixth vertical pillars PL6 in a direction opposite to the first direction. .

Furthermore, as described with reference to FIG. 22 , the second and fifth auxiliary lines SBL2 and SBL5 may not be formed. The second bit line BL2 may be directly connected to the third vertical pillars PL3 through the third lower contacts 152c and the second upper contacts 154b without the second auxiliary line SBL2 . . The fifth bit line BL5 may be directly connected to the fourth vertical pillars PL4 through the fourth lower contacts 152d and the fifth upper contacts 154e without the fifth auxiliary line SBL5 . .

In embodiments according to the concept of the present invention, connecting the vertical pillars and the bit lines through auxiliary wirings according to the configuration described herein may cause the immediately adjacent bit lines to be arranged more closely. Furthermore, the number of bit lines selected by one string select gate, ie, a page size, may be doubled compared to a normal VNAND. Accordingly, program and read speeds may be increased.

For example, referring to FIG. 5A , if the diameter of vertical columns is F in a horizontal perspective, an effective area may be defined as an average area occupied by one channel on the upper surface. In FIG. 5A , the effective area for one channel is 6F ^{2 (2F×3F/1 channel) in a typical VNAND layout, whereas 5F 2} (2F×5F/2) in embodiments according to the concept of the present invention. channel) is reduced. In this way, the unit cell area is reduced, so that the degree of integration can be increased.

24 is a schematic block diagram illustrating an example of an electronic system including a semiconductor device formed according to embodiments according to the inventive concept.

Referring to FIG. 24 , an electronic system 1100 according to embodiments of the present invention includes a controller 1110 , an input/output device 1120 , I/O, a memory device 1130 , an interface 1140 , and a bus. (1150, bus). The controller 1110 , the input/output device 1120 , the memory device 1130 , and/or the interface 1140 may be coupled to each other through the bus 1150 . The bus 1150 corresponds to a path through which data is moved. The memory device 1130 may include semiconductor devices according to embodiments of the present invention.

The controller 1110 may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic devices capable of performing functions similar thereto. The input/output device 1120 may include a keypad, a keyboard, and a display device. The memory device 1130 may store data and/or instructions. The interface 1140 may perform a function of transmitting data to or receiving data from a communication network. The interface 1140 may be wired or wireless. For example, the interface 1140 may include an antenna or a wired/wireless transceiver. Although not shown, the electronic system 1100 may further include a high-speed DRAM device and/or an SRAM device as a motion memory device for improving the operation of the controller 1110 .

The electronic system 1100 includes a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, and a digital music player ( digital music player), a memory card, or any electronic product capable of transmitting and/or receiving information in a wireless environment.

25 is a schematic block diagram illustrating an example of a memory system including a semiconductor device formed according to embodiments according to the inventive concept.

Referring to FIG. 25 , the memory system 1200 includes a storage device 1210 . The memory device 1210 may include at least one of the semiconductor devices disclosed in the above-described embodiments. Also, the memory device 1210 may further include other types of semiconductor memory devices (eg, DRAM devices and/or SRAM devices). The memory card 1200 may include a memory controller 1220 that controls data exchange between a host and the storage device 1210 . The memory device 1210 and/or the controller 1220 may include semiconductor devices according to embodiments of the present invention.

The memory controller 1220 may include a processing unit 1222 that controls the overall operation of the memory card. Also, the memory controller 1220 may include an SRAM 1221 (SRAM) used as an operation memory of the processing unit 1222 . In addition, the memory controller 1220 may further include a host interface 1223 and a memory interface 1225 . The host interface 1223 may include a data exchange protocol between the memory system 1200 and a host. The memory interface 1225 may connect the memory controller 1220 and the memory device 1210 . Furthermore, the memory controller 1220 may further include an error correction block 1224 (Ecc). The error correction block 1224 may detect and correct an error in data read from the memory device 1210 . Although not shown, the memory system 1200 may further include a ROM device for storing code data for interfacing with a host. The memory system 1200 may be used as a portable data storage card. Alternatively, the memory system 1200 may be implemented as a solid state disk (SSD) that can replace the hard disk of the computer system.

26 is a schematic block diagram illustrating an example of an information processing system equipped with a semiconductor device formed according to embodiments according to the inventive concept.

Referring to FIG. 26 , a flash memory system 1310 according to embodiments according to the concept of the present invention is mounted in an information processing system such as a mobile device or a desktop computer. The information processing system 1300 according to embodiments according to the concept of the present invention includes a flash memory system 1310 and a modem 1320 electrically connected to a system bus 1360, a central processing unit 1330, and a RAM 1340, respectively , a user interface 1350 . The flash memory system 1310 may be configured substantially the same as the aforementioned memory system. The flash memory system 1310 stores data processed by the central processing unit 1330 or data input from the outside. Here, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD). In this case, the information processing system 1300 may stably store a large amount of data in the flash memory system 1310 . In addition, as reliability increases, the flash memory system 1310 may reduce resources required for error correction, thereby providing a high-speed data exchange function to the information processing system 1300 . Although not shown, the information processing system 1300 according to embodiments according to the concept of the present invention may further include an application chipset, a camera image processor (CIS), an input/output device, and the like. It is self-evident to those who have acquired common knowledge in the field.

As described above, embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (28)

first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction;
first to third vertical pillars coupled to each of the selection lines and arranged in order in the second direction;
a first auxiliary line connecting the third vertical pillar coupled to the first selection line and the first vertical pillar coupled to the second selection line;
a second auxiliary line connecting the third vertical pillar coupled to the second selection line and the first vertical pillar coupled to the third selection line; and
and bit lines connected to the first and second auxiliary lines and extending in the second direction;
The bit lines are respectively connected to one of the first to third vertical pillars through one of the first auxiliary line and the second auxiliary line. The method according to claim 1,
the bit line includes first to third bit lines immediately adjacent in the first direction;
The first bit line is connected to the first auxiliary line, the second bit line is connected to the second vertical column, and the third bit line is connected to the second auxiliary line. 3. The method according to claim 2,
Further comprising a third auxiliary wiring connected to the second vertical column coupled to each of the selection lines,
The second bit line is connected to the second vertical column through the third auxiliary line. 3. The method according to claim 2,
The first and second auxiliary wires are connected to the first and third vertical pillars through first and third lower contacts,
the first and third bit lines are respectively connected to the first and second auxiliary lines through first and third upper contacts;
The second bit line is connected to the second vertical column through a second lower contact and a second upper contact that are in contact with each other. delete delete A plurality of selection lines extending in a first direction and spaced apart in a second direction intersecting the first direction and having a plurality of vertical columns coupled thereto, the selection lines being adjacent to each other and sequentially along the second direction disposed first to third selection lines;
auxiliary wiring extending on the adjacent selection lines; and
a bit line connected to the auxiliary wiring and extending in the second direction;
The vertical columns coupled to each of the selection lines are arranged in a zigzag, and first to fifth vertical columns are respectively arranged in first to fifth columns sequentially arranged along the second direction. 8. The method of claim 7,
the second vertical pillar is shifted by a first distance from the first vertical pillar in the first direction, and the third vertical pillar is shifted by the first distance from the second vertical pillar in the first direction, and a memory disposed such that a fourth vertical pillar is shifted by the first distance from the third vertical pillar in the first direction, and the fifth vertical pillar is shifted by the first distance from the fourth vertical pillar in the first direction Device. 9. The method of claim 8,
The first vertical pillar coupled to the second selection line is shifted by the first distance in the first direction from the first vertical pillar coupled to the first selection line. 10. The method of claim 9,
The auxiliary wiring is:
a first auxiliary line connecting a fourth vertical pillar coupled to the first selection line and a first vertical pillar coupled to the second selection line;
a second auxiliary line connecting a fifth vertical pillar coupled to the second selection line and a second vertical pillar coupled to the third selection line;
a third auxiliary line connecting a fifth vertical pillar coupled to the first selection line and a second vertical pillar coupled to the second selection line; and
and a fourth auxiliary line connecting a fourth vertical pillar coupled to the second selection line and a first vertical pillar coupled to the third selection line. 11. The method of claim 10,
and a fifth auxiliary line connected to the third vertical pillar coupled to each of the selection lines. 12. The method of claim 11,
the bit line includes first to fifth bit lines immediately adjacent in the first direction;
The first to fifth auxiliary lines are connected to the different bit lines. delete 11. The method of claim 10,
the bit line includes first to fifth bit lines immediately adjacent in order in the first direction;
The first to fourth auxiliary wires may be connected to the first, second, fourth, and fifth vertical pillars through first lower contacts respectively disposed on the first, second, fourth, and fifth vertical pillars. connected to,
four of the bit lines are respectively connected to the first to fourth auxiliary wirings through first upper contacts respectively disposed on the first to fourth auxiliary wirings;
The other one of the bit lines is connected to the third vertical pillar through a second lower contact and a second upper contact which are in contact with each other on the third vertical pillar coupled to each of the selection lines. 9. The method of claim 8,
The vertical columns coupled to each of the selection lines further include a sixth vertical column disposed along a sixth column after the fifth column,
The sixth vertical pillar is arranged to be shifted by the first distance from the fifth vertical pillar in the first direction. 16. The method of claim 15,
The auxiliary wiring is:
a first auxiliary line connecting a fifth vertical pillar coupled to the first selection line and a first vertical pillar coupled to the second selection line;
a second auxiliary line connecting a fifth vertical pillar coupled to the second selection line and a first vertical pillar coupled to the third selection line;
a third auxiliary line connecting a sixth vertical pillar coupled to the first selection line and a second vertical pillar coupled to the second selection line; and
and a fourth auxiliary line connecting a sixth vertical pillar coupled to the second selection line and a second vertical pillar coupled to the third selection line. 17. The method of claim 16,
a fifth auxiliary line connected to the third vertical pillar coupled to each of the selection lines; and
and a sixth auxiliary line connected to the fourth vertical pillar coupled to each of the selection lines. 18. The method of claim 17,
the bit line includes first to sixth bit lines immediately adjacent in the first direction;
The first to sixth auxiliary lines are connected to the different bit lines. delete 17. The method of claim 16,
the bit line includes first to sixth bit lines immediately adjacent in order in the first direction;
The first to fourth auxiliary wires are connected to the first, second, fifth and sixth vertical pillars through first lower contacts disposed on the first, second, fifth, and sixth vertical pillars. each connected,
the first, fourth, sixth and third bit lines are respectively connected to the first to fourth auxiliary lines through first upper contacts disposed on the first to fourth auxiliary lines;
The second bit line is connected to the third vertical pillar through a second lower contact and a second upper contact which are in contact with each other on the third vertical pillar coupled to each of the selection lines, and the fifth bit line is connected to the third vertical pillar. A memory device connected to the fourth vertical pillar through a third lower contact and a third upper contact on the fourth vertical pillar coupled to respective selection lines. A plurality of selection lines extending in a first direction and spaced apart in a second direction intersecting the first direction and having a plurality of vertical columns coupled thereto, the selection lines being adjacent to each other and sequentially along the second direction arranged first to third selection lines;
auxiliary wirings extending on the adjacent selection lines; and
a bit line connected to the auxiliary wirings and extending in the second direction;
The vertical columns coupled to each of the selection lines are arranged in a matrix, and include first to third vertical columns respectively arranged in first to third columns arranged in order along the second direction,
the bit line is connected to the vertical pillars through the auxiliary wirings;
Each of the auxiliary wirings connects vertical pillars respectively connected to different selection lines among the first to third selection lines. 22. The method of claim 21,
The auxiliary wires are:
a first auxiliary line connecting a third vertical pillar coupled to the first selection line and a first vertical pillar coupled to the second selection line; and
and a second auxiliary line connecting a third vertical pillar coupled to the second selection line and a first vertical pillar coupled to the third selection line. delete delete delete 23. The method of claim 22,
the bit line includes first to third bit lines immediately adjacent in order in the first direction;
the first and second auxiliary wires are respectively connected to the first and third vertical pillars through first lower contacts disposed on the first and third vertical pillars;
two of the bit lines are respectively connected to the first and second auxiliary lines through first upper contacts disposed on the first and second auxiliary lines;
The other one of the bit lines is connected to the second vertical pillar through a second lower contact and a second upper contact contacting each other on the second vertical pillar coupled to each of the selection lines. first and second vertical pillars coupled to one selection line extending in a first direction and sequentially arranged in a second direction orthogonal to the first direction;
a first auxiliary line connected to the first vertical pillar through a first lower contact on the first vertical pillar;
a second auxiliary line connected to the second vertical pillar through a second lower contact on the second vertical pillar;
a first bit line connected to the first auxiliary line through a first upper contact offset from the first vertical pillar in the first direction and extending in the second direction; and
a second bit line connected to the second auxiliary line through a second upper contact offset from the second vertical column in a direction opposite to the first direction and extending in the second direction;
The first bit line is connected to the first vertical column through the first auxiliary line, and the second bit line is connected to the second vertical column through the second auxiliary line.


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