CN108417560A - Semiconductor devices and its manufacturing method - Google Patents

Abstract

This disclosure relates to semiconductor devices and its manufacturing method.A kind of semiconductor devices includes：Multiple memory cell strings；Bit line；And interconnection, at least two memory cell strings are attached to bit line.Memory cell string can be attached to corresponding bit line by corresponding interconnection.Alternate memory cell string can be attached to different bit lines by corresponding different interconnection.

Description

Semiconductor devices and its manufacturing method

The application is No. 201310464865.9 hair for being on October 8th, 2013 and entitled " semiconductor devices " applying date The divisional application of bright patent application.

Technical field

The total concept of the invention of the present invention is related to semiconductor devices, more particularly, to vertical-type memory device.

Background technology

In order to realize higher performance and lower cost, to improve semiconductor devices density there are lasting demands. In particular, the density of semiconductor devices is the important determinant of price fixing.Because conventional two-dimensional semiconductor storage unit Density is mainly determined by the area that unit storage unit occupies, so notable shadow of the density by fine patterning technical merit It rings.However, it is necessary to which super high-cost equipment realizes such fine pattern.Therefore, two-dimensional semiconductor memory device is being improved Density in terms of still remain limitation.

Invention content

In one embodiment, a kind of semiconductor devices includes：Multiple vertical stacking memory cell strings, bit line and At least two vertical stacking memory cell strings are attached to the bit line by interconnection, the interconnection.

In another embodiment, a part for interconnection extends in a first direction, and bit line extends in a second direction.

In some embodiments, bit line is arranged essentially parallel to interconnection and extends.

In one embodiment, at least two memory cell string is arranged in a second direction, and in a first direction The part for deviateing bit line and the interconnection is protruded along first direction.

In another embodiment, bit line, interconnection and at least two memory cell string are referred to as the first bit line, first Interconnection and first group of at least two memory cell string, semiconductor devices further include：Second bit line and the second interconnection, described the Second group of at least two memory cell string is attached to the second bit line by two interconnection.

In one embodiment, a part for the first interconnection protrudes in a first direction, and second is interconnected in and first party It is upper in the opposite direction to protrude.

According to the one side of concept of the present invention, a kind of method includes：Form multiple memory cell strings；Interconnection is connected to At least two memory cell strings；And bit line is attached to the interconnection.

According to the another aspect of concept of the present invention, it is a kind of manufacture semiconductor devices method include：On a semiconductor substrate It is rectangular at buffering dielectric layer；The stacking of sacrificial layer and insulating layer is concatenated to form above buffering dielectric layer；It is formed across sacrificial The stacking of domestic animal layer and insulating layer extends to be connected to the vertical column of semiconductor substrate；Dielectric layer is buffered by composition, is sacrificed Layer and insulating layer form marker space to expose portion substrate；Patterned sacrificial layer is removed to form concave area, it is described recessed Time zone exposes the partial sidewall of vertical column；Information storage elements are formed in concave area；Information storage elements in concave area Upper formation conductive layer, to formed include first and second string selection lines memory cell string, first and second go here and there selection lines that This is spaced apart；The first contact is formed on vertical column；Son interconnection is formed in the first contact, by vertical column and first and second Selection line of going here and there interconnects；It mutually connects to form the second contact in the first and second sons；And bit line is formed in the second contact, wherein the One son interconnection and the second son are interconnected by the second contact and are connected to different adjacent bit lines.

Description of the drawings

Due to attached drawing and its detailed description, concept of the present invention will become clearer.The embodiment wherein described is by showing The mode of example provides, rather than is provided by the mode of limitation, wherein identical reference numeral refers to same or analogous element.It is attached Figure is not necessarily drawn to scale, on the contrary, it is preferred that emphasis is shows many aspects of concept of the present invention.

Fig. 1 is the block diagram according to the memory device of multiple embodiments of concept of the present invention；

Fig. 2 is the exemplary block diagram for showing memory cell array in Fig. 1；

Fig. 3 is the perspective view according to the memory block of the vertical-type memory device of the first embodiment of concept of the present invention；

Fig. 4 A to Fig. 4 I are the enlarged drawings of " A " in Fig. 3；

Fig. 5 A, Fig. 5 C and Fig. 5 D are the top plans of the vertical-type memory device in Fig. 3, and Fig. 5 B are the lines in Fig. 5 A The sectional view of A-A' interceptions；

Fig. 6 A to Figure 12 A are top plans corresponding with Fig. 5 A, and Fig. 6 B to 12B are sectional views corresponding with Fig. 5 B；

Figure 13 is the perspective view according to the memory block of the vertical-type memory device of the second embodiment of concept of the present invention；

Figure 14 A are the top plans of the vertical-type memory device in Figure 13, and Figure 14 B are the line A-A' interceptions along Figure 14 A Sectional view；

Figure 15 A to Figure 18 A correspond to the top plan of Figure 14 A, and Figure 15 B to Figure 18 B are sections corresponding with Figure 14 B Figure；

Figure 19 is the perspective view according to the memory block of the vertical-type memory device of the third embodiment of concept of the present invention；

Figure 20 A and Figure 20 C are the top plans of the vertical-type memory device in Figure 19, and Figure 20 B are the lines in Figure 20 A The sectional view of A-A' interceptions；

Figure 21 is the perspective view according to the memory block of the vertical-type memory device of the 4th embodiment of concept of the present invention；

Figure 22 A are the top plans of the vertical-type memory device in Figure 21, and Figure 22 B are that the line A-A' in Figure 22 A is cut The sectional view taken；

Figure 23 A to Figure 25 A are top plans corresponding with Figure 22 A, and Figure 23 B to Figure 25 B are sections corresponding with Figure 22 B Figure；

Figure 26 is the perspective view according to the memory block of the vertical-type memory device of the 5th embodiment of concept of the present invention；

Figure 27 A are the top plans of the vertical-type memory device in Figure 26, and Figure 27 B are that the line A-A' in Figure 27 A is cut The sectional view taken；

Figure 28 is the exemplary schematic block diagram for showing storage system, which includes according to concept of the present invention The semiconductor devices of multiple embodiment manufactures；

Figure 29 is the exemplary schematic block diagram for showing storage card, which includes according to the multiple of concept of the present invention The semiconductor devices of embodiment manufacture；And

Figure 30 is the exemplary schematic block diagram for showing information processing system, and basis is equipped in the information processing system The semiconductor devices of multiple embodiments of concept of the present invention.

Specific implementation mode

The advantages of concept of the present invention and feature and realize that their method will be shown because of following exemplary embodiment So, which is described in more detail with reference to the accompanying drawings.It is noted, however, that concept of the present invention is not It is limited to following exemplary embodiment, and can implements in a variety of manners.Therefore, illustrative embodiments are provided merely to public affairs The example of format concept of the invention, and allow those skilled in the art understand that concept of the present invention essence.

It will be understood that when an element is referred to as " " another element "upper", it can be directly in another element On or intervening elements there may be therebetween.On the contrary, when an element is referred to as " directly existing " another element "upper", then do not have With the presence of intervening elements.As used herein like that, term "and/or" includes one or more projects in related Listed Items Any and all combinations.Should be understood that, although term first, second, third, etc. may be used herein describe various elements, Component, regions, layers, and/or portions, but these elements, component, regions, layers, and/or portions should not be limited by these terms.This A little terms are only used for distinguishing an element, component, region, layer or part and another element, component, region, layer or part. Therefore, first element discussed below, component, region, layer or part can be referred to as second element, component, region, layer or portion Point, without departing from the introduction of concept of the present invention.Term used in this specification is only used for the purpose of description specific implementation mode, It is not intended to become limitation of the present invention.As used in this specification, singulative " one " and "the" are intended to Including plural form, unless context has clearly done other statements.Also it should be understood that, where used in this disclosure, term " packet Include " and/or "comprising" specify the presence of addressed feature, entirety, step, operation, element and/or component, but be not excluded for One or more other features, entirety, step, operation, element, component and/or a combination thereof presence or addition.Entire explanation In book, identical reference numeral indicates identical element.

Now, the excellent of concept of the present invention will be shown in the present invention is more fully described referring to the drawings concept, attached drawing Select embodiment.

Fig. 1 is the block diagram according to the memory device of some embodiments of concept of the present invention.Referring to Fig. 1, according to the present invention The memory device 100 of some embodiments of concept may include memory cell array 10, address decoder 20, read/write circuit 30, data input/output (I/O) circuit 40 and control logic 50.

Memory cell array 10 can be connected to address decoder 20 by a plurality of wordline WL, be connected to by bit line BL Read/write circuit 30.Memory cell array 10 includes multiple storage units.For example, memory cell array 10 is configured to single One or more positions are stored in unit.

Address decoder 20 can be configured to the control of response control logic 50 and operate.Address decoder 20 can be from Outside receives address AD DR.Address decoder 20 decodes the row address in received address AD DR, to select in wordline WL A corresponding wordline.In addition, address decoder 20 may include well known component, such as row decoder, row decoding Device, address buffer etc..

Read/write circuit 30 can be connected to memory cell array 10 by bit line BL, and data are connected to by data line D/L I/O circuits 40.Read/write circuit 30 can be configured to the control of response control logic 50 and operate.Read/write circuit 30 can be by It configures to receive decoded column address from address decoder 20.Read/write circuit 30 can be configured to utilize decoded row Address choice bit line BL.For example, read/write circuit 30 can be configured to receive data from data I/O circuits 40, and will be received The data write storage unit array 10 arrived.Read/write circuit 30 can be configured to read data from memory cell array 10, and By the data transmission of reading to data I/O circuits 40.Read/write circuit 30 can be configured to first from memory cell array 10 Data are read in memory block, and by the second memory block of the data write storage unit array 10 of reading.For example, read/write circuit 30 Copy-back operation can be configured to carry out.

Read/write circuit 30 can include the component of page buffer (or page register), column selector etc..As Another example, read/write circuit 30 can include the component of sense amplifier, write driver, column selector etc..

Data I/O circuits 40 can be connected to read/write circuit 30 by data line DL.Data I/O circuits 40 can by with It sets the control for carrying out response control logic 50 and operates.Data I/O circuits 40 can be configured to exchange data with external device (ED) DATA.The data DATA that data I/O circuits 40 are configured to be received externally is sent to read/write circuit by data line DL 30.The data DATA that data I/O circuits 40 are configured to transmit by data line DL is output to external device (ED).For example, data I/O circuit 40 may include the component of data buffer etc..

Control logic 50 can be connect with address decoder 20, read/write circuit 30 and data I/O circuits 40.Control logic 50 can be configured to control the operation of memory device 100.Control logic 50 can respond the control signal from outside transmission CTRL and operate.

Fig. 2 is block diagram, shows an example of the memory cell array 10 in Fig. 1.Referring to Fig. 2, memory cell array 10 can To include multiple memory block BLK1~BLKh.In memory block BLK1~BLKh each can have three-dimensional structure (or hang down Straight structure).For example, each in memory block BLK1~BLKh may include being corresponded in the first, second, and third direction upper edge Orthogonal axes of coordinates extend structure.For example, each in memory block BLK1~BLKh is included in what third party upwardly extended Multiple unit strings, and memory block BLK1~BLKh extends in a second direction.Additional memory block can prolong in a first direction It stretches.Then, memory block and associated structure can extend in three directions.

Fig. 3 is according to the perspective view of the vertical-type memory device of the first embodiment of concept of the present invention, Fig. 4 A to Fig. 4 I It is the enlarged drawing of " A " in Fig. 3.

Referring to Fig. 3, substrate 110 is provided.Substrate 110 can have the first conduction type, such as p-type.Grid structure GL can To be arranged on substrate 110.Buffering dielectric layer 121 can be arranged between substrate 110 and grid structure GL.Buffer dielectric layer 121 may include other suitable dielectric substances of Si oxide or such as high-k dielectric material.

Grid structure GL can in a first direction extend on substrate 110.Multigroup grid structure GL can be facing with each other, and can To extend in a second direction on substrate 110, wherein second direction is different from first direction.For example, second direction can be real It is orthogonal with first direction in matter.Grid structure GL may include insulating pattern 125 and be separated from each other and insulating pattern 125 Gate electrode G1~G6 therebetween.Gate electrode G1~G6 may include the first to the 6th grid electricity that sequence is stacked on substrate 110 Pole G1~G6.Insulating pattern 125 may include Si oxide.Buffering dielectric layer 121 can be thinner than insulating pattern 125.Grid electricity Pole G1~G6 may include doped silicon, metal (such as tungsten), metal nitride, metal silicide, a combination thereof etc..Although showing Six gate electrodes, but can have any number of gate electrode more than six in grid structure GL.It, can in a specific example To select the quantity of gate electrode based on the quantity of storage unit in memory cell string and controlling transistor.

The first marker space 131 extended in a first direction can be arranged between grid structure GL.First marker space 131 It can be filled with the first partition insulating layer (being not shown, see 141 in Fig. 5 B) herein.Common source polar curve CSL setting is with first In the neighbouring substrate 110 in marker space 131.Common source polar curve CSL can be formed in substrate 110.Common source polar curve CSL can be with that This is spaced apart, and extends in a first direction.Common source polar curve CSL can have second different from the first conduction type conductive Type (such as N-type).Different from figure, common source polar curve CSL, which can have, to be arranged between substrate 110 and first gate electrode G1 And the line-shaped conductive pattern extended in a first direction.

Vertical column PL is arranged to the matrix extended in the first and second direction.Multiple vertical column PL can be with grid structure GL couples.Multiple vertical column PL are connect with substrate 110, and are extended across gate electrode G1~G6.Vertical column PL can have from lining The main shaft that bottom 110 extends (i.e. on third direction) upwards.One end of vertical column PL can couple with substrate 110, and opposite end It can couple with the bit line BL1 and BL2 extended in a second direction.

Son interconnection SBL1 and SBL2 is arranged between vertical column PL and bit line BL1 and BL2.Optionally, vertical column PL and son Interconnecting SBL1 and SBL2 can be by 152 connection of the first contact.Optionally, bit line BL1 and BL2 and son interconnection SBL1 and SBL2 can To pass through 154 connection of the second contact.Son interconnection SBL1 and SBL2 can be mutual by adjacent vertical column PL by the first contact 152 Even, the adjacent vertical column PL can couple with adjacent grid structure GL.

Multiple unit strings setting of the nonvolatile semiconductor memory member of such as flash memory is in bit line BL1 and BL2 and public affairs Between common source line CSL.One individual unit string may include the string select transistor being connect with bit line BL1 and BL2 and public affairs The ground selection transistor (ground selection transistor) of common source line CSL connections and setting are brilliant in string selection Multiple storage units between body pipe and ground selection transistor.The selection transistor and the multiple storage unit can correspond to It is arranged in single semiconductor column PL.First gate electrode G1 can be the ground selection grid line GSL of ground selection transistor.Second to the 5th Gate electrode G2~G5 can be the unit grid WL of multiple storage units.6th gate electrode G6 can be the string choosing of string select transistor Select grid line SSL.

Information storage elements 135 can be arranged between second to the 5th gate electrode G2~G5 and vertical column PL.Although Fig. 3 Shown in be that information storage elements 135 extend between gate electrode G1~G6 and insulating pattern 125 and in gate electrode G1~G6 Extend between vertical column PL, but the location and shape of information storage elements 135 are without being limited thereto.In the embodiment party illustrated later In formula, information storage elements 135 can be changed in various ways (see Fig. 4 A to Fig. 4 I).

In one aspect, vertical column PL may include semi-conducting material.Therefore, vertical column PL may be used as the ditch of transistor Road.Vertical column PL can be solid cylindrical column or hollow cylindrical (such as macaroni type) column.Filling insulating layer 127 can be filled out It fills in hollow vertical column.It may include Si oxide to fill insulating layer 127.Filling insulating layer 127 can be in direct contact vertically The inner wall of column PL.Vertical column PL and substrate 110 can be substantial continuous semiconductor structures.In this case, vertical column PL It can be single crystal semiconductor.Therefore, vertical column PL can be formed with the growing technology of such as selective epitaxial growth (SEG).It replaces The interface of Dai Di, vertical column PL and substrate 110 may include boundary face and/or other discontinuous.In this case, vertical column PL It can be the vertical column of the polycrystalline or non crystalline structure that are formed for example, by chemical vapor deposition.Conductive pattern 128 can be set In one end of vertical column PL.The end of the contact conductive pattern 128 of vertical column PL can form the crystalline substance of such as string select transistor The drain region of body pipe.

As an example, referring to Fig. 4 A, be similar to Fig. 3, information storage elements 135 may include neighbouring gate electrode G1~ The tunnel insulation layer 135a and barrier insulating layer 135c and runnel insulator of the barrier insulating layer 135c of G6, neighbouring vertical column PL Charge storage layer 135b between layer 135a.Information storage elements 135 can be in gate electrode G1~G6 and insulating pattern 125 and vertical Right cylinder PL extends between the two.Barrier insulating layer 135c may include high-k dielectric (such as aluminum oxide or hafnium oxide).Blocking Insulating layer 135c can be the multilayer film for including plural layers.For example, barrier insulating layer 135c may include aluminum oxide and/or Hafnium oxide, and can have the aluminum oxide and hafnium oxide of various stacking orders.Charge storage layer 135b can be The insulating layer of electric charge capture layer, conductive nano-particles etc..Electric charge capture layer may include such as silicon nitride.Tunnel insulation layer 135a may include Si oxide or other suitable dielectric substances.

As another example, different from shown in Fig. 3 referring to Fig. 4 B to Fig. 4 D, information storage elements 135 some Part can not extend between insulating pattern 125 and gate electrode G1~G6, but some other portions of information storage elements 135 Divide and still can extend between gate electrode G1~G6 and vertical column PL.Referring to Fig. 4 B, tunnel insulation layer 135a can insulate Extend between pattern 125 and vertical column PL, and charge storage layer 135b and barrier insulating layer 135c can be in 125 He of insulating pattern Extend between gate electrode G1~G6.

It can be in 125 He of insulating pattern referring to some parts of Fig. 4 C, tunnel insulation layer 135a and charge storage layer 135b Extend between vertical column PL, and some parts of barrier insulating layer 135c can insulating pattern 125 and gate electrode G1~G6 it Between extend.Referring to Fig. 4 D, tunnel insulation layer 135a, charge storage layer 135b and barrier insulating layer 135c can be in insulating patterns Extend between 125 and vertical column PL, however insulating pattern 125 is in direct contact gate electrode G1~G6.

Different from above example, referring to Fig. 4 E, charge storage layer 135b may include polysilicon.At this point, tunnel insulation layer 135a, charge storage layer 135b and barrier insulating layer 135c can be arranged in gate electrode G1~G6, vertical column PL and insulating pattern Between 125.

On the other hand, vertical column PL can be conductive column.Vertical column PL may include such as doped semiconductor, metal, lead At least one of the conductive material of electric metal nitride, silicide or nanostructure (such as carbon nanotube or graphene).

Referring to Fig. 4 F, information storage elements 135 can be provided only on gate electrode G1~G6, vertical column PL and insulating pattern Between 125.

Referring to Fig. 4 G and Fig. 4 H, information storage elements 135 between insulating pattern 125 and vertical column PL or can insulate Extend between pattern 125 and gate electrode G1~G6.At this point, information storage elements 135 can be variable resistance pattern.Variable resistance Pattern may include at least one of the material for having variable resistance characteristics (that is, its resistance-variable).Hereinafter, it is used as letter Ceasing the example of the variable resistance pattern of memory element 135 will be explained below.

As an example, information storage elements 135 may include following material, depending on flowing through the electric current of its adjacent electrode The resistance of the heat of generation, the material can be changed.The material can be such as phase-change material.The phase-change material may include antimony (Sb), at least one of tellurium (Te) and selenium (Se).For example, the phase-change material may include chalcogenide compound, There is middle tellurium (Te) concentration of about 20 to about 80 atomic percents, antimony (Sb) to have the concentration of about 5 to about 50 atomic percents, Remaining is germanium (Ge).In addition, the phase-change material may include in N, O, C, Bi, In, B, Sn, Si, Ti, Al, Ni, Fe, Dy and La At least one is used as impurity.Alternatively, which can be by only a kind of in GeBiTe, InSb, GeSb and GaSb It is made.

As an example, information storage elements 135 can be formed to membrane structure, and the resistance of the membrane structure can Spin transfer process caused by the electric current of information storage elements 135 (spin transfer procedure) is flowed through with utilization to change Become.Information storage elements 135 can have membrane structure magnetoresistance characteristic is presented, and include in ferromagnetic material at least one At least one of kind and/or antiferromagnet.Information storage elements 135 then may include free layer and reference layer.

As another example, information storage elements 135 may include at least one of perovskite compound or transition At least one of metal.For example, information storage elements 135 may include niobium oxide, titanium oxide, nickel oxide, zirconium oxygen Compound, barium oxide, PCMO ((Pr, Ca) MnO3), strontium titanium oxide, barium strontium titanium oxide, strontium Zirconium oxide, barium Zirconium oxide At least one of with barium strontium Zirconium oxide.

According to some examples of concept of the present invention, referring to Fig. 4 I, at least one of the material SW with self-rectifying property (for example, PN junction diode) can be arranged between information storage elements 135 and gate electrode G1~G6.

Fig. 5 A are the top plans of the vertical-type memory device in Fig. 3, and Fig. 5 B are that the line A-A' in Fig. 5 A is intercepted Sectional view.It, now will be detailed according to the vertical-type memory device of some embodiments of concept of the present invention referring to Fig. 5 A and Fig. 5 B Thin description.

May include the first and second grid structure GL1 and GL2 referring to Fig. 5 A and Fig. 5 B, grid structure GL.First grid structure GL1 The 6th gate electrode G6 can be referred to as the first string selection line SSL1, the 6th gate electrode G6 of the second grid structure GL2 can be claimed For the second string selection line SSL2.First and second string selection line SSL1 and SSL2 can be alternately arranged in a second direction.

Vertical column may include the first and second vertical column PL1 and PL2 of sequence arrangement in a second direction.First and second Vertical column PL1 and PL2 can be arranged the matrix in the first and second directions.First vertical column PL1 is connected in string selection line The side of SSL1 or SSL2, the second vertical column PL2 can be connected in its other side.Adjacent vertical column can be in a first direction Be separated from each other two pitches of such as bit line BL1 and BL2.

Son interconnection can will be attached to vertical column PL1 and the PL2 interconnection of different string selection line SSL.Son interconnects The first son interconnection of interconnection SBL1 and second SBL2.For example, the first son interconnection SBL1 can be by one first string selection line SSL1 The second vertical column PL2 be connected to the first vertical column PL1 of the second string selection line SSL2, the second son interconnection SBL2 can be by second The second vertical column PL2 of string selection line SSL2 is connected to the first vertical column PL1 of another first string selection line SSL1.

Each first son interconnection SBL1 and each second son interconnection SBL2 can be arranged along first direction.First and second sons Interconnection SBL1 and SBL2 can be alternately arranged in a second direction.The first son interconnection of interconnection SBL1 and second SBL2 can be connected To different bit lines adjacent to each other.For example, the first son interconnection SBL1 can be connected to the first bit line BL1, the second son interconnection SBL2 can be connected to the second bit line BL2.

First son interconnection SBL1 may include along first direction the first protruding portion P1 outstanding, and the second son interconnection SBL2 can be with Including along with first party the second protruding portion P2 outstanding in the opposite direction.

In some embodiments, application is depended on, the first protruding portion P1 and the second protruding portion P2 can be arranged Identical side upwardly extends.

Protruding portion P1 and P2 can extend above the first partition insulating layer 141 between grid structure GL1 and GL2.

Vertical column PL1 and PL2 can be connected to sub- interconnection SBL1 and SBL2 by the first contact 152.Second contact 154 can be with Sub- interconnection SBL1 and SBL2 is connected to bit line BL1 and BL2.First contact 152 can be arranged on vertical column PL1 and PL2.The Two contacts 154 can be arranged on sub- interconnection SBL1 and SBL2, the first partition insulating layer 141 between grid structure GL1 and GL2 Top.For example, the second contact 154 can be right over the first partition insulating layer 141.

As shown in Figure 5A, the second contact 154 on the first son interconnection SBL1 is moved away from the first contact 152 in a first direction, Such as the half of the pitch of displacement bit line BL1 and BL2；Second son interconnection SBL2 on second contact 154 with first direction phase Anti- side moves upward away from the first contact 152, such as the half of the pitch of displacement bit line BL1 and BL2.Second contact 154 can be set It sets on protruding portion P1 and P2.

Fig. 5 C and Fig. 5 D show the modified example of Fig. 5 A.Referring to Fig. 5 C and Fig. 5 D, will be detailed below according to this hair The modified example of the vertical-type memory device of some embodiments of bright concept.With the technical characteristic phase illustrated in Fig. 5 A and Fig. 5 B As technical characteristic will not be illustrated that but difference therebetween will be described in detail.

Referring to Fig. 5 C, the first son interconnection SBL1 can extend in a second direction, and include outstanding prominent along first direction Go out portion P1.Second son interconnection SBL2 can have the rectangle or substantially rectangular in shape extended in a second direction, without Protruding portion P1 or P2.The second contact 154 on first son interconnection SBL1 can be moved away from the first contact 152, the second son interconnection SBL2 On the second contact 154 can contact 152 with first and be aligned.The second contact 154 on first son interconnection SBL1 can be along first Direction is moved away from a pitch of 152 bit line BL1 and BL2 of the first contact.

Referring to Fig. 5 D, the first and second son interconnection SBL1 and SBL2 can have the rectangle extended in a second direction or square Shape shape.For example, son interconnection SBL1 and SBL2 can have the width bigger than bit line BL1 and BL2, and with more straight than vertical column The small width of diameter.The second contact 154 that first son mutually connects can be moved away from the first such as bit line of contact 152 in a first direction The half pitch of BL1 and BL2, the second son interconnects the second contact 154 on SBL2 can be in a direction opposite the first direction It is moved away from the half pitch of the first contact 152 such as bit line BL1 and BL2.Son interconnection SBL1 and SBL2 have from first contact 152 to The width that second contact 154 extends.

As shown in Fig. 5 C and Fig. 5 D, sub- interconnection SBL1 and SBL2 may be modified as variously-shaped.Although specific shape It is utilized as example with size, but in other embodiments, other shapes, size etc. may be used in sub- interconnection SBL.

In the embodiment described above of concept of the present invention, it will be hung down by son interconnection according to the techniques described herein construction Right cylinder, which is connected to bit line, allows adjacent bit line (such as adjacent bit line) to be more closely arranged, integrated close to increase Degree.For example, if the diameter of vertical column is referred to as F when from top, effective area can be defined as single on top surface The average area that a raceway groove occupies.In the Butut of traditional VNAND arrangements, the effective area for single raceway groove is 6F²(2F× 3F/1 raceway grooves)；However the effective area for single raceway groove in the first embodiment of concept of the present invention is decreased to 5F²(2F × 5F/2 raceway grooves).Therefore, unit cell area can be reduced, to increase integration density.In addition, compared with traditional VNAND When, the quantity (that is, page size) of the bit line of a string selection grid selection can double.Then, programming and reading speed can be carried It is high.

The method to form the memory device of the vertical-type in Fig. 3 will now be described.Fig. 6 A to Figure 12 A are tops corresponding with Fig. 5 A Portion's vertical view, Fig. 6 B to Figure 12 B are sectional views corresponding with Fig. 5 B.

Referring to Fig. 6 A and Fig. 6 B, substrate 110 is provided.Substrate 110 can have the first conduction type, such as p-type.Buffering electricity Dielectric layer 121 can be formed on substrate 110.It may include such as Si oxide to buffer dielectric layer 121.Buffer dielectric layer 121 can form for example, by thermal oxidation technology.Sacrificial layer 123 and insulating layer 124 are alternately superimposed in buffering dielectric layer 121 On.The thickness of topmost insulating layer 124U can be more than the thickness of other insulating layers 124.Insulating layer 124,124U may include example Such as Si oxide.Sacrificial layer 123 may include have relative to buffering dielectric layer 121 and insulating layer 124,124U it is different wet The material of etching (etching selectivity).Sacrificial layer 123 may include such as silicon nitride, silicon-oxygen nitride, polysilicon or more Crystal silicon germanium.Sacrificial layer 123 and insulating layer 124 can be formed for example, by chemical vapor deposition (CVD).

Referring to Fig. 7 A and Fig. 7 B, vertical hole 126 is formed to expose substrate 110, passes through buffering dielectric layer 121, sacrificial Domestic animal layer 123 and insulating layer 124,124U.Vertical hole 126 can be by side identical with the vertical column PL1 and PL2 that are explained with reference to Fig. 5 A Formula is arranged.

Referring to Fig. 8 A and Fig. 8 B, vertical column PL1 and PL2 are formed in vertical hole 126.In one aspect, vertical column PL1 and PL2 can be the semiconductor layer of the first conduction type.The semiconductor layer can be formed to not fill up (that is, being partially filled with) vertically Hole 126, and insulating materials can be formed on the semiconductor layer to fill up vertical hole 126.The semiconductor layer and insulating materials It can be flattened, to expose topmost insulating layer 124U.Then, cylindrical orthogonal column PL1 and PL2 can be formed, With to fill the inside of the filling of insulating layer 127.

Alternatively, which can be formed to fill up vertical hole 126.At this point it is possible to which insulating layer need not be filled. The top of vertical column PL1 and PL2 can be recessed to be less than topmost insulating layer.Conductive pattern 128 can be formed in vertical hole 126 Interior, vertical column PL1 and PL2 are recessed in the vertical hole 126.Conductive pattern 128 can be by conductive material such as doped polycrystalline Silicon or metal are formed.Drain region can by by the impurity of the second conduction type introduce conductive pattern 128 and vertical column PL1 and The top of PL2 is formed.Second conduction type can be N-type.

On the other hand, vertical column PL1 and PL2 may include such as doped semiconductor, metal, conductive metal nitride, silicon At least one of the conductive material of compound or nanostructure (such as carbon nanotube or graphene).

Referring to Fig. 9 A and Fig. 9 B, buffering dielectric layer 121, sacrificial layer 123 and insulating layer 124 are by sequence composition, to be formed Marker space 131, marker space 131 are separated from each other, extend in a first direction, and expose portion substrate 110.Patterned insulation Layer 124,124U can become insulating pattern 125.

Referring to Figure 10 A and Figure 10 B, the patterned sacrificial layer 123 for being exposed to marker space 131 is selectively removed, with shape At concave area 133.Concave area 133 corresponds to the region that sacrificial layer 123 therein is removed, and by vertical column PL1 and PL2 and absolutely Edge pattern 125 defines.If sacrificial layer 123 includes silicon nitride or silicon-oxygen nitride, the technique for removing sacrificial layer 123 can be with It is carried out with the etchant of phosphoric acid.The partial sidewall of vertical column PL1 and PL2 are exposed relative to concave area 133.

Referring to Figure 11 A and Figure 11 B, information storage elements 135 are formed in concave area 133.In one embodiment, information Memory element 135 may include the tunnel insulation layer for contacting vertical column PL1 and PL2, the charge storage layer on tunnel insulation layer, with And the barrier insulating layer on charge storage layer (see, for example, Fig. 4 A).At this point, vertical column PL1 and PL2 can be semiconductor columns.Tunnel Road insulating layer may include Si oxide.The vertical column that tunnel insulation layer can be exposed by thermal oxide relative to concave area 133 PL1 and PL2 is formed.Alternatively, tunnel insulation layer can be formed by atomic layer deposition (ALD) technique.Charge storage layer can be with It is electric charge capture layer or the insulating layer including conductive nano-particles.Electric charge capture layer may include such as silicon nitride.Blocking is exhausted Edge layer may include high-k dielectric (such as aluminum oxide or hafnium oxide).Barrier insulating layer can be include plural layers Multilayer film.For example, barrier insulating layer may include aluminum oxide and Si oxide, and there can be the alumina of various stacking orders Compound and Si oxide.Charge storage layer and barrier insulating layer can pass through the ALD techniques covered with excellent step and/or change Vapor deposition (CVD) technique is learned to be formed.Alternatively, when information storage elements 135 are with structure shown in Fig. 4 B to Fig. 4 E, At least one of tunnel insulation layer, charge storage layer and/or barrier insulating layer of configuration information memory element 135 can hang down It is formed in vertical hole 126 before the formation of right cylinder PL1 and PL2.

In some other embodiments, information storage elements 135 can be variable resistance pattern (see Fig. 4 F to Fig. 4 H). Variable resistance pattern may include the material for having variable resistance characteristics (that is, its resistance depends on flowing through its electric current and can be changed) At least one of material.In this case, vertical column PL1 and PL2 can include conductive material (for example, doped semiconductor, gold Category, conductive metal nitride, silicide or nanostructure (such as carbon nanotube or graphene)) conductive column.When information is deposited When storing up element 135 has structure shown in Fig. 4 G, information storage elements 135 can be before the formation of vertical column PL1 and PL2 It is formed in vertical hole 126.

Conductive layer is formed on the information storage elements 135 in concave area 133.Conductive layer can be by doped silicon, metal (example Such as tungsten), at least one of metal nitride and metal silicide formed.Metal conducting layer can be formed by ALD techniques.When When conductive layer is metal silicide layer, neighbouring first marker space 131 of formation polysilicon layer, removal polysilicon layer can be passed through Part is so that polysilicon layer is recessed, forms metal layer, heat treated metal layer and removal unreacted on recessed polysilicon layer Metal layer, form the conductive layer.Metal layer for metal silicide layer may include tungsten, titanium, cobalt or nickel.

The conductive layer for being formed in the outside (that is, in first marker space 131) of concave area 133 is removed.Then, gate electrode G1~G6 is formed in concave area 133.Gate electrode G1~G6 extends in a first direction.Grid structure GL may include gate electrode G1 ~G6.Grid structure GL may include the first and second grid structure GL1 and GL2 being alternately arranged in a second direction.By first and First and second vertical column PL1 and PL2 of the matrix arrangements in two directions can couple with a grid structure.

The conductive layer formed in marker space 131 can be removed, to expose substrate 110.The impurity of second conduction type can To be introduced into high concentration in exposed substrate 110, to form common source polar curve CSL.

Referring to Figure 12 A and Figure 12 B, the first partition insulating layer 141 is formed to filling marker space 131.First contact 152 can To be formed on vertical column PL1 and PL2.Son interconnection SBL1 and SBL2 can be formed in the first contact 152.Son interconnection SBL1 and SBL2 can by first contact 152 connection be respectively attached to adjacent string selection line SSL1 and SSL2 vertical column PL1 and PL2.That is, son interconnection SBL1 and SBL2 can cross over the first partition insulating layer 141.

The first son interconnection of interconnection SBL1 and second SBL2 can extend in a second direction.First son interconnection SBL1 can be wrapped It includes along first direction the first protruding portion P1 outstanding, the second son interconnection may include along outstanding in the opposite direction with first party Second protruding portion P2.Protruding portion P1 and P2 can extend above the first partition insulating layer 143 between grid structure GL1 and GL2.

Return to Fig. 5 A and Fig. 5 B, the first son of interconnection SBL1 and second interconnection SBL2 by the second contact 154 from it is different Adjacent bit line connection.First son interconnection SBL1 can be connected to the first bit line BL1, and the second son interconnection SBL2 can be connected to the Two bit line BL2.

Figure 13 is the perspective view according to the memory block of the vertical-type memory device of some embodiments of concept of the present invention.Figure 14A is the top plan of the vertical-type memory device in Figure 13, and Figure 14 B are the sectional views of the line A-A' interceptions along Figure 14 A.With It will not be illustrated with reference to the similar technical characteristic of technical characteristic of Fig. 3 embodiments illustrated, but difference therebetween will be detailed It describes in detail bright.

Referring to Figure 13, Figure 14 A and Figure 14 B, four vertical columns PL1, PL2, PL1 and PL2 are sequentially arranged in a second direction In single grid structure GL.Four vertical columns PL1, PL2, PL1 and PL2 are arranged to matrix, and the also edge in grid structure GL First direction extends.

The 6th gate electrode G6 of one grid structure GL may include the first and second string selection line SSL1 and SSL2.First string The string selection lines of selection line SSL1 and second SSL2 can be located adjacent one another, and is alternately arranged in a second direction.Second partition insulating layer 142 are formed between the string selection lines of the first string selection line SSL1 and second SSL2.Second partition insulating layer 142 can have than the The small width of one partition insulating layer 141.

First protruding portion P1 can extend above the first partition insulating layer 141, and the second protruding portion P2 can be at second point 142 top of used outside insulated layer extends.The second contact 154 on first son interconnection SBL1 can be arranged in the first partition insulating layer 141 On, the second contact 154 on the second son interconnection SBL2 can be arranged on the second partition insulating layer 142.

As shown in Fig. 5 C and Fig. 5 D, sub- interconnection SBL1 and SBL2 may be modified as variously-shaped.

The effective area of single raceway groove is reduced in this embodiment of concept of the present invention referring to Figure 14 A 4F²(2F × 4F/2 raceway grooves).Similarly, unit cell area can be reduced to increase integration density.In addition, working as and tradition When VNAND is compared, it can be doubled by the quantity (that is, page size) of the bit line of a string selection grid selection.Then, it programs and reads Take speed that can improve.

The method that the vertical-type memory device in manufacture Figure 13 will now be described.Figure 15 A to Figure 17 A correspond to Figure 14 A Top plan, Figure 15 B to Figure 17 B correspond to the sectional view of Figure 14 B.With the embodiment party illustrated with reference to Fig. 6 A to Figure 12 B The similar technical characteristic of formula will not be illustrated, but difference therebetween will be described in detail.

Referring to Figure 15 A and Figure 15 B, similar to the embodiment illustrated with reference to Fig. 6 A to Fig. 8 B, vertical column PL1 and PL2 shape At in vertical hole, the vertical hole is through buffering dielectric layer 121, sacrificial layer 123 and insulating layer 124 to expose substrate 110. Vertical column PL1 and PL2 can be recessed, and conductive pattern 128 can be formed in recessed vertical hole.

Referring to Figure 16 A and Figure 16 B, buffering dielectric layer 121, sacrificial layer 123 and insulating layer 124 can be patterned, with shape At the marker space 131 being separated from each other.Marker space 131 extends in a first direction, and a part for exposure substrate 110.Composition The insulating layer 124 crossed becomes insulating pattern 125.Be exposed to marker space 131 sacrificial layer 123 be selectively removed it is recessed to be formed Area 133.

Referring to Figure 17 A and Figure 17 B, information storage elements 135 and conductive layer are formed in concave area 133.It is formed in recessed The conductive layer of time zone 133 outer (that is, in marker space 131) is removed.Then, gate electrode G1~G6 is formed in above-mentioned concave area In 133.Gate electrode G1~G6 is extended in a first direction.

The conductive layer formed in marker space 131 can be removed, with expose portion substrate 110.Second conduction type it is miscellaneous Matter can be introduced exposed substrate 110 to form common source polar curve CSL in high concentration.

First partition insulating layer 141 is formed to fill marker space 131.6th gate electrode G6 is patterned, to single The first and second string selection line SSL1 and SSL2 are formed in grid structure GL.Second marker space 132 is formed in the choosing of the first and second strings It selects between line SSL1 and SSL2.First and second string selection line SSL1 and SSL2 are located adjacent one another, and are alternately arranged in a second direction. The first and second the vertical column PL1 and PL2 for being arranged to matrix can couple with a string selection line.For example, in this embodiment In, in single grid structure GL, the first and second vertical column PL1 and PL2 can with first and second string selection line SSL1 and One of SSL2 couples.

Referring to Figure 18 A and Figure 18 B, the second partition insulating layer 142 is formed to the second marker space 132 of filling.First contact 152 can be formed on vertical column PL1 and PL2.Son interconnection SBL1 and SBL2 can be formed in the first contact 152.First son The son interconnection of interconnection SBL1 and second SBL2 can extend in a second direction.Son interconnection SBL1 and SBL2 can be by one-to-one Mode, by the first contact 152 connection vertical column PL1 and PL2, the vertical column PL1 and PL2 respectively with adjacent string selection line SSL1 and SSL2 connections.

Referring to Figure 14 A and Figure 14 B, the first son of interconnection SBL1 and second interconnection SBL2 is connected to by the second contact 154 Adjacent not corresponding lines.First son interconnection SBL1 can be connected to the first bit line BL1, and the second son interconnection SBL2 can be connected to the Two bit line BL2.

Figure 19 is the perspective view according to the memory block of the vertical-type memory device of some embodiments of concept of the present invention.Figure 20A is the top plan of the vertical-type memory device in Figure 19, and Figure 20 B are the sectional views of the line A-A' interceptions in Figure 20 A. Technical characteristic similar with the embodiment illustrated with reference to Fig. 3 will not be illustrated, but difference therebetween will be described in detail.

Referring to Figure 19, Figure 20 A and Figure 20 B, grid structure GL may include neighbouring first to third grid structure.First grid knot 6th gate electrode G6 of structure can be referred to as the first string selection line SSL1, and the 6th gate electrode G6 of the second grid structure can be referred to as Second string selection line SSL2, the 6th gate electrode G6 of third grid structure can be referred to as third string selection line SSL3.First to Three string selection line SSL1~SSL3 can be alternately arranged in a second direction.

Vertical column PL may include the vertical column PL1~PL4 arranged by zigzag mode.That is, vertical column PL1~PL4 can be with It is arranged with offsetting with one another in second direction both direction in a first direction.First and the 4th vertical column PL1 and PL4 can be arranged In the both sides of string selection line SSL1~SSL3, second and third vertical column PL2 and PL3 can be arranged in the first vertical column PL1 and Between 4th vertical column PL4.Second vertical column PL2 can be moved away from the first vertical column PL1 along first direction.4th vertical column PL4 Third vertical column PL3 can be moved away from along first direction.Adjacent vertical column can be separated from each other along first direction bit line BL1~ Two pitches of BL4.

Son interconnection may include first to fourth son interconnection SBL1~SBL4.First son interconnection SBL1 can will go here and there with first The third vertical column PL3 of selection line SSL1 connections is connected to the second vertical column PL2 coupled with the second string selection line SSL2.Second The third vertical column PL3 coupled with the second string selection line SSL2 can be connected to and third string selection line SSL3 by son interconnection SBL2 Second vertical column PL2 of connection.The 4th vertical column PL4 that third interconnection SBL3 can will couple with the first string selection line SSL1 It is connected to the first vertical column PL1 coupled with the second string selection line SSL2.4th son interconnection SBL4 can will be selected with the second string 4th vertical column PL4 of line SSL2 connections is connected to the first vertical column PL1 coupled with third string selection line SSL3.

First son interconnection SBL1 and third interconnection SBL3 can be alternately arranged along first direction, second son interconnection SBL2 and 4th son interconnection SBL4 can be alternately arranged along first direction.The first son interconnection of interconnection SBL1 and the 4th SBL4 can be along second Direction is alternately arranged, and the second son interconnection SBL2 and third interconnection SBL3 can be alternately arranged in a second direction.

First to fourth son interconnection SBL1~SBL4 can be connected to corresponding bit line.For example, the first son interconnection SBL1 The first bit line BL1 can be connected to, the second son interconnection SBL2 can be connected to the second bit line BL2, and third interconnects SBL3 can be with The 4th bit line BL4 can be connected to by being connected to third bit line BL3, the 4th son interconnection SBL4.

In order to which vertical column PL1~PL4 is connected to sub- interconnection SBL1~SBL4, the first contact 152 can be set.In order to incite somebody to action Son interconnection SBL1~SBL4 is connected to bit line BL1~BL4, and the second contact 154 can be arranged.First contact 152 can be arranged On vertical column PL1~PL4, the second contact 154 can be arranged on the first partition insulating layer 141.For example, first and third The second contact 154 on interconnection SBL1 and SBL3 can be moved away from 152 half of bit line pitch of the first contact, the second He along first direction The second contact 154 on 4th son interconnection SBL2 and SBL4 can divide along the first contact four is moved away from the opposite direction with first party One of bit line pitch.First to fourth son interconnection SBL1~SBL4 can extend in a second direction.First and third interconnection SBL1 and SBL3 can be respectively included along first direction outstanding first and third protruding portion P1 and P3.Second and the 4th son interconnection SBL2 and SBL4 can respectively include along with first party in the opposite direction outstanding second and the 4th protruding portion P2 and P4.First Protrusion distance with third protruding portion P1 and P3 can be second and the 4th twice of protrusion distance of protruding portion P2 and P4.Second Contact 154 can be arranged on protruding portion P1~P4.The first separation that protruding portion P1~P4 is extended between grid structure is exhausted On edge layer 141.

Figure 20 C show the modified example of Figure 20 A.Referring to Figure 20 C, according to some other embodiments of concept of the present invention The modified example of vertical-type memory device will be more fully described below now.With the technical characteristic illustrated in Figure 20 A and Figure 20 B Similar technical characteristic will not be illustrated, but difference therebetween will be described in detail.

First and third interconnection SBL1 and SBL3 can extend in a second direction, and may include being protruded along first direction Protruding portion P1 and P3.Second and the 4th son interconnection SBL2 and SBL4 can have the substantial rectangular shape that extends in a second direction Shape.The second contact 154 on first and third interconnection SBL1 and SBL3 can be moved away from the first contact 152 along first direction, the The second contact 154 on two and the 4th son interconnection SBL2 and SBL4 can not be moved away from the first contact 152.For example, first and third The second contact on son interconnection SBL1 and SBL3 can be moved away from a section of 152 bit line BL1~BL4 of the first contact along first direction Away from.As shown in Figure 20 C, sub- interconnection SBL1~SBL4 can be deformed into variously-shaped.

Figure 20 A are referred back to, according to some embodiments of concept of the present invention, the effective area of single raceway groove is subtracted As low as 3.3F²(2F × 5F/3 raceway grooves).Equally, unit cell area can be reduced, to increase integration density.In addition, when with When traditional VNAND is compared, the quantity (that is, page size) of the bit line of a string selection grid selection can be increased to four times.Then, it compiles Journey and reading speed can be enhanced.

It can be by referring to according to the vertical-type memory device of some embodiments of concept of the present invention shown in Figure 19 The method of Fig. 6 A to Figure 12 B description is formed.In addition, hanging down according to some embodiments of concept of the present invention shown in Figure 19 Straight type memory device can be changed with the concept of the invention of referring to Fig.1 3, Figure 14 A and Figure 14 B descriptions so that a grid structure GL The 6th gate electrode G6 include the first and second string selection line SSL1 and SSL2.The effective area of single raceway groove can be subtracted It is small to be less than 3.3F²(2F × 5F/3 raceway grooves).

Figure 21 is the perspective view according to the memory block of the vertical-type memory device of some embodiments of concept of the present invention.Figure 22A is the top plan of a part for the vertical-type memory device in Figure 21, and Figure 22 B are the line A-A' interceptions in Figure 22 A Sectional view.Technical characteristic similar with the embodiment described with reference to Fig. 3 will not be illustrated, but difference therebetween will be detailed It describes in detail bright.

Referring to Figure 21, Figure 22 A and Figure 22 B, substrate 110 is provided.Substrate 110 can have the first conduction type, such as P Type.Grid structure GL is arranged on substrate 110.Grid structure GL may include insulating pattern 125 and be separated from each other and insulation figure The therebetween gate electrode of case 125.Gate electrode may include sequence be stacked in the first to the 6th gate electrode G1 on substrate 110~ G6.Insulating pattern 125 may include Si oxide.Gate electrode G1~G6 may include doped silicon, metal (such as tungsten), metal nitrogen Compound, metal silicide or a combination thereof.Although showing six gate electrodes in figure, the quantity of gate electrode is not limited to six, It can be more than six or few.

Vertical column PL is arranged along the first and second directions, forms the matrix of vertical column PL.Through gate electrode G1~G6, vertically Column PL is connected to substrate 110.Vertical column PL can have from the main shaft that (that is, on third direction) extends upwards of substrate 110. Certain end of vertical column PL can be connect with substrate 110, and its remaining end can be connected to the bit line BL1 that extends in a second direction and BL2。

Son interconnection SBL1 and SBL2 is located between vertical column PL and bit line BL1 and BL2.Vertical column PL and son interconnection SBL1 and SBL2 can pass through 152 connection of the first contact.Bit line BL1 and BL2 can contact 154 with son interconnection SBL1 and SBL2 by second Connection.The vertical column PL that son interconnection SBL1 and SBL2 can be coupled by 152 connection of the first contact with adjacent grid structure GL.

Multiple unit strings of flash memory are arranged between bit line BL1 and BL2 and substrate 110.Individual unit string May include the string select transistor being connect with bit line BL1 and BL2, the ground selection transistor being connect with substrate 110 and setting Multiple storage units between string select transistor and ground selection transistor.Selection transistor and multiple storage units can be set It sets at single semiconductor column PL.First gate electrode G1 can be the ground selection grid line GSL of ground selection transistor.Second to the 5th Gate electrode G2~G5 can be the unit grid WL of multiple storage units.6th gate electrode G6 can be separated by third marker space 133 At multiple (Figure 21), for use as the string selection line of string select transistor.Selection line of going here and there may include the first and second string selection lines SSL1 and SSL2.First and second string selection line SSL1 and SSL2 can be extended in a first direction, and can be handed in a second direction For arrangement.For example, third partition insulating layer 143 is arranged on the third between the first and second string selection line SSL1 and SSL2 point In septal area 133, as shown in Figure 22 B.

Information storage elements 135 can be arranged between first to the 6th gate electrode G1~G6 and vertical column PL.Information is deposited Storage element 135 can extend between gate electrode G1~G6 and insulating pattern 125.Information storage elements 135 may include blocking Insulating layer, charge storage layer and tunnel insulation layer.

Substrate 110 can be provided with source area (not shown), which, which forms, flows from the electric current of bit line BL1 and BL2 Channel, or it flow to the channel of the electric current of bit line BL1 and BL2.

Since vertical column PL1 and PL2 and son interconnection SBL1 and SBL2 are similar to illustrating with reference to Fig. 3, so similar skill Art feature will not be described in more detail.The protruding portion P1 and P2 of son interconnection SBL1 and SBL2 can be in third partition insulating layer 143 tops extend.Second contact 154 can be arranged on sub- interconnection SBL1 and SBL2 above third partition insulating layer 143.

As shown in Fig. 5 C and Fig. 5 D, sub- interconnection SBL1 and SBL2 can have variously-shaped.

Referring to Figure 22 A, according to some embodiments of concept of the present invention, the effective area of single raceway groove is reduced to 4F² (2F × 4F/2 raceway grooves).Similarly, unit cell area can be reduced to increase integration density.In addition, working as and traditional VNAND phases Than when, can be doubled by the quantity (that is, page size) of bit line of a string selection grid selection.Then, programming and reading speed It can improve.

The method that will be described in the vertical-type memory device in manufacture Figure 21 now.Figure 23 A to Figure 25 A are and Figure 22 A Corresponding top plan, Figure 23 B to Figure 25 B are sectional views corresponding with Figure 22 B.

Referring to Figure 23 A and Figure 23 B, substrate 110 is provided.Substrate 110 can have the first conduction type, such as p-type.Insulation Layer 124 and conductive layer 122 are formed alternately on substrate 110.Insulating layer 124 may include such as Si oxide.Conductive layer 122 can To include such as doped silicon, metal (such as tungsten), metal nitride, metal silicide.

Vertical hole 126 is formed to penetrate conductive layer 122 and insulating layer 124, to expose substrate 110.Can by with reference Vertical hole 126 is arranged in the identical mode of vertical column PL1 and PL2 that Figure 22 A illustrate.

Referring to Figure 24 A and Figure 24 B, information storage elements 135 are formed on the side wall of vertical hole 126.Information storage elements 135 may include barrier insulating layer, charge storage layer and tunnel insulation layer.Information storage elements 135 be anisotropically etched with Exposure substrate 110.

Vertical column PL1 and PL2, which are formed in vertical hole 126, adjoins information storage elements 135.Vertical column PL1 and PL2 and lining Bottom 110 connects.

On the one hand, vertical column PL1 and PL2 can be the semiconductor layer of the first conduction type.The semiconductor layer can be by It is formed not fill up vertical hole 126, and insulating materials can be formed on the semiconductor layer to fill up vertical hole 126.It should be partly Conductor layer and insulating materials can be flattened, to expose topmost insulating layer 124'.Then, it is filled with filling insulating layer 127 Cylindrical orthogonal column PL1 and PL2 can be formed.The semiconductor layer can be formed to fill up vertical hole 126.At this point, The filling insulating layer can not needed.The top of vertical column PL1 and PL2 can be recessed with the top less than topmost insulating layer 124' Surface.Conductive pattern 128 can be formed in the recessed part wherein vertical column PL1 and PL2 of vertical hole 126.Conductive pattern 128 can be DOPOS doped polycrystalline silicon or metal.Drain region can by by the impurity of the second conduction type introduce conductive pattern 128 with And the top of vertical column PL1 and PL2 is formed.Second conduction type can be N-type.

On the other hand, vertical column PL1 and PL2 may include such as doped semiconductor, metal, conductive metal nitride, silicon At least one of the conductive material of compound or nanostructure (such as carbon nanotube or graphene).At this point, information storage is first Part can be variable resistance pattern.

Insulating layer 124 and conductive layer 122 can be patterned, to form insulating pattern 125 and gate electrode G1~G6.6th Gate electrode G6 can be by additional composition, to be divided into multiple gate electrodes.Then, the 6th gate electrode G6 may include the first He Second string selection line SSL1 and SSL2.

Referring to Figure 25 A and Figure 25 B, the setting of third partition insulating layer 143 is in the first and second string selection line SSL1 and SSL2 Between third marker space 133 in.First contact 152 can be formed on vertical column PL1 and PL2.Son interconnection SBL1 and SBL2 It can be formed in the first contact 152.Son interconnection SBL1 and SBL2 can by first contact 152 by vertical column PL1 and close to Vertical column PL2 interconnection, wherein the vertical column PL1 and adjacent vertical column PL2 and different string selection line SSL1 and SSL2 It connects together.

The first son interconnection of interconnection SBL1 and second SBL2 can extend in a second direction.First son interconnection SBL1 can be with Including along first direction the first protruding portion P1 outstanding, the second son interconnection SBL2 may include along with first party in the opposite direction Second protruding portion P2 outstanding.Protruding portion P1 and P2 are extended on third partition insulating layer 143.

Referring back to Figure 22 A and Figure 22 B, the first son of interconnection SBL1 and second interconnection SBL2 is connected by the second contact 154 It is connected to different adjacent bit lines.That is, the first son interconnection SBL1 can be connected to the first bit line BL1, the second son interconnection SBL2 can To be connected to the second bit line BL2.

Figure 26 is the perspective view according to the vertical-type memory device of some embodiments of concept of the present invention.Figure 27 A are figures The top plan of vertical-type memory device in 26, Figure 27 B are the sectional views of the line A-A' interceptions in Figure 27 A.With reference The similar technical characteristic of technical characteristic for the embodiment that Figure 21 illustrates will not be illustrated, but difference therebetween will be detailed It describes in detail bright.

Referring to Figure 26, Figure 27 A and Figure 27 B, vertical column PL may include first to fourth vertical column PL1~PL4, first to 4th vertical column PL1~PL4 is sequentially arranged by zigzag mode.First and second vertical column PL1 and PL2 can be with each string The side of selection line SSL1~SSL3 couples, the third and fourth vertical column PL3 and PL4 can with each string selection line SSL1~ The other side of SSL3 couples.First and the 4th vertical column PL1 and PL4 can be arranged string selection line SSL1~SSL3 edge, Second and third vertical column PL2 and PL3 can be arranged between the first vertical column PL1 and the 4th vertical column PL4.Second vertical column PL2 can be moved away from the first vertical column PL1 along first direction.4th vertical column PL4 can be moved away from third vertical column along first direction PL3.Adjacent vertical column can be separated from each other two pitches of such as bit line BL1~BL4 along first direction.

Son interconnection may include first to fourth son interconnection SBL1~SBL4.First son interconnection SBL1 can select the first string The third vertical column PL3 for selecting line SSL1 is connected to the second vertical column PL2 of the second string selection line SSL2.Second son interconnection SBL2 can The third vertical column PL3 of the second string selection line SSL2 to be connected to the second vertical column PL2 of third string selection line SSL3.Third The 4th vertical column PL4 of first string selection line SSL1 can be connected to the first of the second string selection line SSL2 and hung down by son interconnection SBL3 Right cylinder PL1.The 4th vertical column PL4 of second string selection line SSL2 can be connected to third string selection line by the 4th son interconnection SBL4 The first vertical column PL1 of SSL3.First son interconnection SBL1 and third interconnection SBL3 can be alternately arranged along first direction, and second The son interconnection of interconnection SBL2 and the 4th SBL4 can be alternately arranged along first direction.First and the 4th son interconnection SBL1 and SBL4 can To be alternately arranged in a second direction, second and third interconnection SBL2 and SBL3 can be alternately arranged in a second direction.First to 4th son interconnection SBL1~SBL4 can be connected to adjacent different bit lines.For example, the first son interconnection SBL1 can be connected to First bit line BL1, the second son interconnection SBL2 can be connected to the second bit line BL2, and third interconnection SBL3 can be connected to third Bit line BL3, the 4th son interconnection SBL4 can be connected to the 4th bit line BL4.

Vertical column PL1~PL4 is connected to sub- interconnection SBL1~SBL4 by the first contact 152.Second contacts 154 by sub- interconnection SBL1~SBL4 is connected to bit line BL1~BL4.First contact 152 can be arranged on vertical column PL1~PL4；Second contact 154 can be arranged on third partition insulating layer 143 or alignment normal thereto.For example, first and third interconnection SBL1 Can be moved away from 152 half of bit line pitch of the first contact along first direction with the second contact 154 on SBL3, second and the 4th son mutually Even the second contact 154 on SBL2 and SBL4 can be along being moved away from the first contact a quarter bit line with first party in the opposite direction Pitch.First to fourth son interconnection SBL1~SBL4 can extend in a second direction.First and third interconnection SBL1 and SBL3 It can respectively include along first direction outstanding first and third protruding portion P1 and P3.Second and the 4th son interconnection SBL2 and SBL4 Can respectively include along with first party in the opposite direction outstanding second and the 4th protruding portion P2 and P4.For example, first and The protrusion distance of three protruding portion P1 and P3 can be second and the 4th twice of protrusion distance of protruding portion P2 and P4.That is, first Protrusion distance with third protruding portion P1 and P3 can be with bigger to arrive at corresponding bit line.Second contact 154 can be arranged prominent Go out on portion P1~P4.Protruding portion P1~P4 extends to 143 top of the first partition insulating layer between grid structure.

Referring to Figure 27 A, in the 5th embodiment of concept of the present invention, the effective area of single raceway groove is reduced to come Less than 3.3F²(2F × 5F/3 raceway grooves).Similarly, unit cell area can be reduced to increase integration density.In addition, being attributed to The arrangement of vertical column PL can be increased to four times by the quantity (that is, page size) of the bit line of a string selection grid selection.Then, Programming and reading speed can improve.

Figure 28 is the exemplary schematic block diagram for showing storage system, which includes according to concept of the present invention The semiconductor devices of multiple embodiment manufactures.

Referring to Figure 28, electronic system 1100 may include controller 1110, input/output device (I/O) 1120, memory Part 1130, interface 1140 and bus 1150.It controller 1110, input/output device 1120, memory device 1130 and/or connects Mouth 1140 can be connected to each other by bus 1150.Bus 1150 is corresponding to data along the path of its transmission.Memory device 1130 It may include the semiconductor devices according to multiple embodiments of concept of the present invention.

Controller 1110 may include at least one of following devices：Microprocessor, digital signal processor, microcontroller Device and the logical device that similar functions can be executed.Input/output device 1120 may include keypad, keyboard, display device Or the like.Memory device 1130 can store data and/or order.Interface 1140 can be used for sending data to communication Net, or receive data from communication network.Interface 1140 can be wireline interface or wireless interface.For example, interface 1140 can wrap Include antenna or wire/wireless transceiver.Although it is not shown, electronic system 1100 can also include being used as run memory Part is to improve the high-speed DRAM device and/or SRAM device of the operation of controller 1110.

Electronic system 1110 can be used for personal digital assistant (PDA), pocket computer, online flat board computer, wireless electricity Words, mobile phone, digital music player, storage card or all electricity that can send and/or receive in wireless environments data Sub-device.

Figure 29 is the exemplary schematic block diagram for showing storage card, which includes according to the multiple of concept of the present invention The semiconductor devices of embodiment manufacture.

Referring to Figure 29, storage card 1200 includes memory device 1210.Memory device 1210 may include aforementioned embodiments Disclosed at least one of semiconductor devices.In addition, memory device 1210 can also be deposited including other types of semiconductor Memory device (such as DRAM device and/or SRAM device etc.).Storage card 1200 may include control host and memory device 1210 Between data exchange storage control 1220.Memory device 1210 and/or controller 1220 may include according to the present invention The semiconductor devices of multiple embodiments of concept.

Storage control 1220 may include the processing unit 1222 for the global operation for controlling storage card.Storage control 1220 may include the SRAM 1221 of the working storage as processing unit 1222.In addition, storage control 1220 can be with Including host interface 1223 and memory interface 1225.Host interface 1223 may include the data between storage card 1200 and host Exchange agreement.Storage control 1220 can be connected to memory device 1210 by memory interface 1225.In addition, storage control 1220 can also include that error code corrects (ECC) block 1224.ECC Block 1224 can be detected and be corrected and be read from memory device 1210 The mistake of the data taken.Although it is not shown, storage card 1200 can also include ROM device, ROM device is stored for passing through The code data that interface is connect with host.Storage card 1200 is used as portable data storage card.Alternatively, storage card 1200 It can be realized with solid state disk (SSD), which can replace the hard disk of computer system.

Figure 30 is the exemplary schematic block diagram for showing information processing system, and basis is equipped in the information processing system The semiconductor devices that multiple embodiments of concept of the present invention are formed.

Referring to Figure 30, it is mounted on according to the flash memory system 1310 of multiple embodiments of concept of the present invention and is such as moved In the information processing system of device or desktop computer.According to the information processing system of multiple embodiments of concept of the present invention 1300 include flash memory system 1310 and are electrically connected to the modem 1320 of system bus 1360, central processing Device (CPU) 1330, RAM 1340 and user interface 1350.Flash memory system 1310 can have basic with above-mentioned storage system Upper identical construction.The data or externally input data of the processing of CPU 1330 are stored in flash memory system 1310. With the raising of reliability, flash memory system 1310 can reduce the resource needed for error correction, so as to information processing system System 1300 provides high-speed data function of exchange.Although it is not shown in the figure, to those skilled in the art it is apparent that letter It can also includes application chip group, camera image processor (CIS), input/output device etc. to cease processing system 1300.

In addition, can be packaged into subsequently according to the memory device of multiple embodiments of concept of the present invention or storage system By one of various types being embedded into.For example, according to the flash memory of multiple embodiments of concept of the present invention or storage System can pass through one of following encapsulation：PoP (laminate packaging), BGA Package (BGA), chip size packages (CSP), modeling Expect tube core (the Die in leaded chip carrier encapsulation (PLCC), dual inline type Plastic Package (PDIP), Waffle pack Waffle Pack), the tube core (Die in Wafer Form) of wafer format, chip on board encapsulation (COB), dual inline type pottery Porcelain encapsulates (CERDIP), plastics metric system quad flat package (MQFP), slim quad flat package (TQFP), small outline packages (SOIC), tighten small outline packages (SSOP), Outline Package (TSOP), slim quad flat package (TQFP), system Grade encapsulation (SIP), multi-chip package (MCP), wafer scale manufacture encapsulation (WFP) and wafer scale storehouse encapsulation (WSP).

As described so far like that, the unit cell area of vertical memory device can be reduced, and vertically be deposited to increase The density of memory device.Since bit line quantity can increase compared with traditional technology, so page size can increase, the speed of service can carry It is high.

In the whole instruction, technical characteristic can be incorporated into other embodiment shown in an embodiment, And in the spirit and scope of concept of the present invention.

Mean to contact the embodiment to " embodiment " or referring to for " embodiment " throughout this specification The specific features of description, structure or characteristic are included at least one embodiment of the present invention.Thus, phrase is " at one In embodiment " or " in one embodiment " the appearance throughout the various places of this specification be not be necessarily all referring to it is same Embodiment.In addition, specific feature, structure or characteristic can be incorporated into one or more realities in any suitable manner It applies in mode.

A variety of operations can be described as the multiple discrete steps executed in a manner of most beneficial for the present invention is understood.So And the sequence that step is described does not mean that the operation is order dependent, does not mean that the sequence that step executes must be yet The sequence that step occurs.

Although specifically illustrating and describing concept of the present invention with reference to the illustrative embodiments of concept of the present invention, For those of ordinary skill in the art it is apparent that in the purport for not departing from the concept of the present invention defined such as appended claims In the case of range, various changes in form and details can be done.

This application claims the South Korea patent applications submitted on October 5th, 2012 No. 10-2012-0110751 and 2013 3 The priority for the U.S. Patent Application No. 13/844,337 that the moon is submitted on the 15th, entire contents are tied by reference to reference hereby It closes.

Claims (2)

1. a kind of semiconductor devices, including：

Multiple vertical stacking memory cell strings；

Interconnection interconnects at least two vertical stacking memory cell strings；And

Bit line is attached to the interconnection.

2. a kind of method of manufacture semiconductor devices, including：

Form multiple memory cell strings；

Interconnection is attached at least two memory cell strings to interconnect described at least two memory cell strings；With And

Bit line is attached to the interconnection.