SG11202008495TA - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
SG11202008495TA
SG11202008495TA SG11202008495TA SG11202008495TA SG11202008495TA SG 11202008495T A SG11202008495T A SG 11202008495TA SG 11202008495T A SG11202008495T A SG 11202008495TA SG 11202008495T A SG11202008495T A SG 11202008495TA SG 11202008495T A SG11202008495T A SG 11202008495TA
Authority
SG
Singapore
Prior art keywords
memory device
semiconductor memory
semiconductor
memory
Prior art date
Application number
SG11202008495TA
Inventor
Takeshi Nagatomo
Tatsuo Izumi
Ryota Suzuki
Takuya Nishikawa
Yasuhito Nakajima
Daiki Takayama
Hiroaki Naito
Genki Kawaguchi
Original Assignee
Kioxia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kioxia Corp filed Critical Kioxia Corp
Publication of SG11202008495TA publication Critical patent/SG11202008495TA/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
SG11202008495TA 2018-03-20 2019-03-11 Semiconductor memory device SG11202008495TA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018052558A JP2021089905A (en) 2018-03-20 2018-03-20 Semiconductor storage device
PCT/JP2019/009686 WO2019181606A1 (en) 2018-03-20 2019-03-11 Semiconductor storage device

Publications (1)

Publication Number Publication Date
SG11202008495TA true SG11202008495TA (en) 2020-10-29

Family

ID=67987758

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202008495TA SG11202008495TA (en) 2018-03-20 2019-03-11 Semiconductor memory device

Country Status (6)

Country Link
US (1) US11569253B2 (en)
JP (1) JP2021089905A (en)
CN (1) CN111989776B (en)
SG (1) SG11202008495TA (en)
TW (1) TWI692853B (en)
WO (1) WO2019181606A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021141283A (en) * 2020-03-09 2021-09-16 キオクシア株式会社 Semiconductor storage device
JP7534046B2 (en) 2020-08-19 2024-08-14 東京エレクトロン株式会社 Etching method and plasma processing apparatus
KR102603209B1 (en) * 2021-03-26 2023-11-16 한양대학교 산학협력단 3d flash memory with improved stack connection and manufacturing method thereof
WO2024057540A1 (en) * 2022-09-16 2024-03-21 キオクシア株式会社 Semiconductor storage device and method of manufacturing semiconductor storage device

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5175525B2 (en) * 2007-11-14 2013-04-03 株式会社東芝 Nonvolatile semiconductor memory device
JP4468433B2 (en) 2007-11-30 2010-05-26 株式会社東芝 Nonvolatile semiconductor memory device
JP2010225741A (en) * 2009-03-23 2010-10-07 Toshiba Corp Nonvolatile semiconductor memory device
US8420480B2 (en) * 2011-03-31 2013-04-16 Freescale Semiconductor, Inc. Patterning a gate stack of a non-volatile memory (NVM) with formation of a gate edge diode
US9741736B2 (en) * 2011-05-20 2017-08-22 Kabushiki Kaisha Toshiba Semiconductor memory device
JP2013197419A (en) * 2012-03-21 2013-09-30 Toshiba Corp Semiconductor device manufacturing method
JP2014053447A (en) * 2012-09-07 2014-03-20 Toshiba Corp Nonvolatile semiconductor storage device
US9799671B2 (en) * 2015-04-07 2017-10-24 Sandisk Technologies Llc Three-dimensional integration schemes for reducing fluorine-induced electrical shorts
JP6434877B2 (en) * 2015-08-26 2018-12-05 東芝メモリ株式会社 Semiconductor device
US9768191B2 (en) * 2015-10-19 2017-09-19 Toshiba Memory Corporation Semiconductor device
US20170141124A1 (en) * 2015-11-17 2017-05-18 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing same
US10373967B2 (en) * 2015-12-18 2019-08-06 Floadia Corporation Memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device
US9991280B2 (en) * 2016-02-17 2018-06-05 Sandisk Technologies Llc Multi-tier three-dimensional memory devices containing annular dielectric spacers within memory openings and methods of making the same
US10242994B2 (en) 2016-03-16 2019-03-26 Sandisk Technologies Llc Three-dimensional memory device containing annular etch-stop spacer and method of making thereof
US9780034B1 (en) * 2016-03-16 2017-10-03 Sandisk Technologies Llc Three-dimensional memory device containing annular etch-stop spacer and method of making thereof
US9768192B1 (en) 2016-03-16 2017-09-19 Sandisk Technologies Llc Three-dimensional memory device containing annular etch-stop spacer and method of making thereof
US9953993B2 (en) * 2016-07-25 2018-04-24 Toshiba Memory Corporation Semiconductor memory device

Also Published As

Publication number Publication date
CN111989776A (en) 2020-11-24
US11569253B2 (en) 2023-01-31
JP2021089905A (en) 2021-06-10
US20200395371A1 (en) 2020-12-17
TWI692853B (en) 2020-05-01
TW201946254A (en) 2019-12-01
WO2019181606A1 (en) 2019-09-26
CN111989776B (en) 2024-01-05

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