SG10202006171VA - Nonvolatile memory device - Google Patents
Nonvolatile memory deviceInfo
- Publication number
- SG10202006171VA SG10202006171VA SG10202006171VA SG10202006171VA SG10202006171VA SG 10202006171V A SG10202006171V A SG 10202006171VA SG 10202006171V A SG10202006171V A SG 10202006171VA SG 10202006171V A SG10202006171V A SG 10202006171VA SG 10202006171V A SG10202006171V A SG 10202006171VA
- Authority
- SG
- Singapore
- Prior art keywords
- memory device
- nonvolatile memory
- nonvolatile
- memory
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020190128221A KR20210045538A (en) | 2019-10-16 | 2019-10-16 | Nonvolatile memory device |
US16/878,756 US11430806B2 (en) | 2019-10-16 | 2020-05-20 | Nonvolatile memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10202006171VA true SG10202006171VA (en) | 2021-05-28 |
Family
ID=75403157
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10202006171VA SG10202006171VA (en) | 2019-10-16 | 2020-06-26 | Nonvolatile memory device |
Country Status (4)
Country | Link |
---|---|
US (1) | US11430806B2 (en) |
KR (1) | KR20210045538A (en) |
CN (1) | CN112670292A (en) |
SG (1) | SG10202006171VA (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200078784A (en) * | 2018-12-21 | 2020-07-02 | 삼성전자주식회사 | Three-dimensional semiconductor memory devices |
US11404091B2 (en) * | 2020-06-19 | 2022-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array word line routing |
US11355516B2 (en) | 2020-07-16 | 2022-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
US11647634B2 (en) | 2020-07-16 | 2023-05-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional memory device and method |
US11423966B2 (en) | 2020-07-30 | 2022-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory array staircase structure |
US11348640B1 (en) * | 2021-04-05 | 2022-05-31 | Micron Technology, Inc. | Charge screening structure for spike current suppression in a memory array |
KR20230020366A (en) * | 2021-08-03 | 2023-02-10 | 어플라이드 머티어리얼스, 인코포레이티드 | Selection gate structure and fabrication method for 3d memory |
KR20230075014A (en) | 2021-11-22 | 2023-05-31 | 삼성전자주식회사 | Nonvolatile memory devices and mehtods of operatig nonvoltaile memory devices |
KR20240034542A (en) * | 2022-09-07 | 2024-03-14 | 삼성전자주식회사 | Semiconducotr memory device and electronic system including the same |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100582422B1 (en) | 2004-05-15 | 2006-05-22 | 에스티마이크로일렉트로닉스 엔.브이. | Nand flash memory device |
KR101226685B1 (en) | 2007-11-08 | 2013-01-25 | 삼성전자주식회사 | Vertical type semiconductor device and Method of manufacturing the same |
US8044448B2 (en) | 2008-07-25 | 2011-10-25 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
KR101691092B1 (en) | 2010-08-26 | 2016-12-30 | 삼성전자주식회사 | Nonvolatile memory device, operating method thereof and memory system including the same |
US8553466B2 (en) | 2010-03-04 | 2013-10-08 | Samsung Electronics Co., Ltd. | Non-volatile memory device, erasing method thereof, and memory system including the same |
US9536970B2 (en) | 2010-03-26 | 2017-01-03 | Samsung Electronics Co., Ltd. | Three-dimensional semiconductor memory devices and methods of fabricating the same |
KR101682666B1 (en) | 2010-08-11 | 2016-12-07 | 삼성전자주식회사 | Nonvolatile memory devicwe, channel boosting method thereof, programming method thereof, and memory system having the same |
KR101855324B1 (en) | 2011-05-04 | 2018-05-09 | 삼성전자주식회사 | Three dimmensional semiconductor memory deivces and methods of fabricating the same |
KR20130072522A (en) | 2011-12-22 | 2013-07-02 | 에스케이하이닉스 주식회사 | Three dimension non-volatile memory device and method for manufacturing the same |
JP2014027104A (en) | 2012-07-26 | 2014-02-06 | Toshiba Corp | Semiconductor device and manufacturing method of the same |
KR102259943B1 (en) * | 2014-12-08 | 2021-06-04 | 삼성전자주식회사 | Nonvolatile memory device including multi-plane |
US9941209B2 (en) | 2016-03-11 | 2018-04-10 | Micron Technology, Inc. | Conductive structures, systems and devices including conductive structures and related methods |
KR102550571B1 (en) | 2016-05-02 | 2023-07-04 | 에스케이하이닉스 주식회사 | Semiconductor device and method of manufacturing the same |
US10249640B2 (en) | 2016-06-08 | 2019-04-02 | Sandisk Technologies Llc | Within-array through-memory-level via structures and method of making thereof |
KR20190013347A (en) | 2017-08-01 | 2019-02-11 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method thereof |
KR20200114285A (en) | 2019-03-28 | 2020-10-07 | 에스케이하이닉스 주식회사 | Semiconductor memory device |
-
2019
- 2019-10-16 KR KR1020190128221A patent/KR20210045538A/en not_active Application Discontinuation
-
2020
- 2020-05-20 US US16/878,756 patent/US11430806B2/en active Active
- 2020-06-26 SG SG10202006171VA patent/SG10202006171VA/en unknown
- 2020-07-30 CN CN202010755054.4A patent/CN112670292A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US11430806B2 (en) | 2022-08-30 |
CN112670292A (en) | 2021-04-16 |
KR20210045538A (en) | 2021-04-27 |
US20210118903A1 (en) | 2021-04-22 |
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