CN107731834B - A kind of core space layer insulation oxide layer CMP method for 3D NAND - Google Patents
A kind of core space layer insulation oxide layer CMP method for 3D NAND Download PDFInfo
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- CN107731834B CN107731834B CN201710761488.3A CN201710761488A CN107731834B CN 107731834 B CN107731834 B CN 107731834B CN 201710761488 A CN201710761488 A CN 201710761488A CN 107731834 B CN107731834 B CN 107731834B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
One kind being used for 3D NAND core space layer insulation oxide layer CMP method, comprising: provides substrate；In the upper cvd nitride object and oxide stack of substrate；SiON layers are deposited on nitride and oxide stack, and carry out ISSG processing；The deposited oxide layer on ISSG treated SiON layer；Step structure is etched, to complete core space；Core space layer insulation oxide layer is deposited, at least filling step structure neighboring area；CMP processing is carried out to the substrat structure that deposited core space layer insulation oxide layer, using the SiON layer of ISSG processing as polish stop layer.It is used as polish stop layer by using processed SiON layers of ISSG, improves the grinding selectivity ratio of polish stop layer, reduces the thickness of mask stop-layer, and then reduces the step height after polish stop layer removal.The uniformity of channel hole plug oxide thickness can be improved using the CMP method, and reduce the variation of memory device characteristic.
Description
Technical field
The present invention relates to core space layers in a kind of manufacturing method of 3D nand memory more particularly to 3D nand memory
Between insulating oxide (IND Core Oxide) CMP method.
Background technique
3D nand memory is a kind of technology for stacking data cell, can realize 32 layers or more or even 72 numbers of plies at present
According to the stacking of unit.3D nand flash memory overcomes the limitation of the true extension limit of plane nand flash memory, further improves and deposits
Capacity is stored up, the carrying cost of each data bit is reduced, reduces energy consumption.
3D nand memory mostly uses the mode of vertical stacking multi-layer data unit to form storage organization, as storage is held
The increase of amount, NO stacking number gradually increase, and are used to form the difference in height of the step structure of the nucleus of storage unit gradually
Increase.To stacking nitride and oxide stack 20 etching form step structure after, deposited oxide layer 40, such as SiO2Layer,
Fill step structure around region, then by chemical mechanical grinding (CMP) technique planarize surface, the CMP process generally with
SiN layer 30 on nitride and oxide stack 20 is used as polish stop layer, as shown in Fig. 1 (a).Then, it is removed by etching
SiN layer 30 as polish stop layer.Since the grinding selectivity of oxide layer 40 and SiN layer 30 is not good enough, thicker SiN is needed
Stop-layer of the layer as CMP.Due to CMP load effect, edge SiN thickness change be will be present after subsequent removal SiN layer one big
Step height need subsequent CMP to make its planarization as shown in the a-quadrant Fig. 1 (b).
Summary of the invention
To solve the above-mentioned problems, present applicant proposes one kind to be used for 3D NAND core space layer insulation oxide layer
(ILDC) CMP method is used as polish stop layer by using processed SiON layers of ISSG, improves grinding for polish stop layer
Mill selection ratio, can reduce the thickness of polish stop layer, and then reduce the step height after polish stop layer removal.Using the CMP
Method can improve the uniformity of channel hole plug oxide thickness, and reduce the variation of memory device characteristic.
The present invention provides a kind of for 3D NAND core space layer insulation oxide layer CMP method, comprising:
Substrate is provided；
In the upper cvd nitride object and oxide stack of substrate；
SiON layers are deposited on nitride and oxide stack, and carry out ISSG processing；
The deposited oxide layer on ISSG treated SiON layer；
Etch nitride and oxide stack, and step structure is formed in nucleus；
Core space layer insulation oxide layer is deposited, at least filling step structure neighboring area；
CMP processing is carried out to the substrat structure that deposited core space layer insulation oxide layer, is stopped using SiON layers as grinding
Only layer；
The SiON layer of etching removal ISSG processing.
According to CMP method of the invention, wherein the etching of SiON layer of removal is dry etching, preferably plasma etching, more
Preferably, etching gas CF4/O2Gas.
It further include that SiON layers of deposition use PECVD method, deposition atmosphere SiH according to CMP method of the invention4、N2O and
N2The combination of gas or NH3Gas.
According to CMP method of the invention, wherein core space layer insulation oxide layer is TEOS oxide layer.
According to CMP method of the invention, wherein SiON layers with a thickness of 10-50nm.
According to CMP method of the invention, wherein oxide layer with a thickness of 10-60nm.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
The CMP process of Fig. 1 core space layer insulation oxide layer in the prior art.
The block diagram of the step of Fig. 2 core space layer insulation oxide layer CMP process according to the present invention.
The sectional view of the step of Fig. 3 core space layer insulation oxide layer CMP process according to the present invention.
Grinding selectivity ratio of Fig. 4 different materials with respect to TEOS oxide layer.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened is fully disclosed to those skilled in the art.
Referring to figs. 2 and 3 (a), substrate 10 has nucleus and peripheral region, and peripheral region is used to form single with storage
The relevant control circuit of member, is formed with multiple transistor arrangements, and deposition forms nitride and oxide stack on substrate
(NO stack) 20, is used to form the memory cell of 3D NAND.Deposit the method for forming nitride and oxide stack 20
It can be any one depositional mode, such as PECVD, the quantity of nitride and oxide stack can be set according to memory capacity
Meter, such as 8 layers, 32 layers.
It deposits to form SiON layer 31 using such as PECVD method on nitride and oxide stack 20, PECVD deposition can adopt
Use SiH4、N2O and N2The combination of gas or NH3Gas, the SiON thickness degree of growth can be 10-50nm.The SiON layer 31 can also rise
To the effect of anti-reflecting layer.Situ steam generation (ISSG) processing is carried out to SiON layer 31.Nitrogen can be introduced in ISSG processing
Gas or other inert gases are as diluent gas, and oxygen flow can be 2 to 15slm in ISSG processing, and hydrogen flowing quantity can be
0.1 to 3slm, temperature is 800 to 1200 DEG C, and chamber pressure is 5 to 20Torr, and the time of ISSG processing can be 1 to 200
Second.Then deposition forms oxide layer 32 on SiON layer 31, and the thickness of oxide layer 32 can be 10-60nm.
Referring to figs. 2 and 3 (b), the substrat structure after forming oxide layer 32 to deposition carries out step etching, forms Step-edge Junction
Structure.Step etching can be used trimming-etching (Trim-etch) method and be formed, other appropriate ways can also be used.Etching forms platform
After stage structure, core space layer insulation oxide layer is deposited, silica is such as formed using TEOS method, at least fill Step-edge Junction
Around structure, core space layer insulation oxide layer can be such as deposited in the whole surface of substrate 10, the thickness of oxide layer is greater than platform
The highest step of stage structure and the difference in height of minimum step cause gap by the difference in height of step structure around filling step.
To deposited oxide layer substrate 10 carry out CMP grinding, the CMP grinding using ISSG treated SiON layer as grind stopping
Layer, i.e. CMP are stopped on the SiON layer of ISSG processing.
Fig. 4 shows the grinding selectivity ratio of the SiON, polysilicon of SiN, SiON, ISSG processing relative to TOES oxide.
Wherein SiON is 11.5 relative to the grinding selectivity ratio of TOES oxide, and a little higher than SiN is selected relative to the grinding of TOES oxide
It selects than 10.9, and the SiON of ISSG processing is up to 35.0 relative to the grinding selectivity ratio of TOES oxide, is much higher than SiN, this makes
Using ISSG processing SiON as polish stop layer when, thickness can than use SiN when it is thin very much.
Referring to figs. 2 and 3 (c), plasma etching is carried out to the substrat structure after CMP grinding, is stopped with removal grinding
Layer.Plasma etching preferably uses CF4/O2 gas to carry out, this is because SiON layer with the plasma etching of silicon oxide layer
Rate is essentially identical, therefore after plasma etching removal polish stop layer, has the oxide layer of essentially identical thickness to be removed, serve as a contrast
The surface more smooth of bottom structure.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (6)
1. one kind is used for 3D NAND core space layer insulation oxide layer CMP method, comprising:
Substrate is provided；
In the upper cvd nitride object and oxide stack of substrate；
SiON layers are deposited on nitride and oxide stack, and carry out ISSG processing；
The deposited oxide layer on ISSG treated SiON layer；
Etch nitride and oxide stack, and step structure is formed in nucleus；
Core space layer insulation oxide layer is deposited, at least filling step structure neighboring area；
To deposited core space layer insulation oxide layer substrat structure carry out CMP processing, using ISSG processing SiON layer as
Polish stop layer；
SiON layers of etching removal, wherein
SiON layers of deposition use PECVD method, deposition atmosphere SiH4、N2O and N2The combination of gas or NH3Gas.
2. CMP method according to claim 1, wherein the etching removes SiON layers as using plasma etching.
3. CMP method according to claim 2, wherein the etching gas of plasma etching is CF4/O2Gas.
4. CMP method according to claim 1, wherein core space layer insulation oxide layer is TEOS oxide layer.
5. CMP method described in any one of -4 according to claim 1, wherein SiON layers with a thickness of 10-50nm.
6. CMP method described in any one of -4 according to claim 1, wherein oxide layer with a thickness of 10-60nm.
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| CN108389786B (en) * | 2018-03-08 | 2019-06-21 | 长江存储科技有限责任公司 | The hard mask processing method of memory block manufacturing process for three-dimensional storage part |
| CN109065545A (en) * | 2018-08-14 | 2018-12-21 | 长江存储科技有限责任公司 | The flattening method of three-dimensional storage and its stack layer |
| KR102635678B1 (en) * | 2018-11-19 | 2024-02-14 | 에스케이하이닉스 주식회사 | Semiconductor memory device and method for forming the same |
| WO2020248091A1 (en) * | 2019-06-10 | 2020-12-17 | Intel Corporation | 3d memory device with top wordline contact located in protected region during planarization |
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| CN103633030A (en) * | 2012-08-22 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Method for improving in-plane uniformity of reliability of SONOS flash device |
| CN105047553A (en) * | 2015-08-26 | 2015-11-11 | 上海华力微电子有限公司 | Surface treatment method for depositing high-dielectric value gate medium layer |
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| US7696094B2 (en) * | 2006-12-27 | 2010-04-13 | Spansion Llc | Method for improved planarization in semiconductor devices |
| US8822287B2 (en) * | 2010-12-10 | 2014-09-02 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103633030A (en) * | 2012-08-22 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Method for improving in-plane uniformity of reliability of SONOS flash device |
| CN105047553A (en) * | 2015-08-26 | 2015-11-11 | 上海华力微电子有限公司 | Surface treatment method for depositing high-dielectric value gate medium layer |
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