CN107731844B - Etching method of 3D memory - Google Patents
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- CN107731844B CN107731844B CN201710761489.8A CN201710761489A CN107731844B CN 107731844 B CN107731844 B CN 107731844B CN 201710761489 A CN201710761489 A CN 201710761489A CN 107731844 B CN107731844 B CN 107731844B
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- 238000005530 etching Methods 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 37
- 239000010410 layer Substances 0.000 claims abstract description 81
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 6
- 239000000126 substance Substances 0.000 claims abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 5
- 238000007517 polishing process Methods 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 8
- 238000011065 in-situ storage Methods 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 230000008021 deposition Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical compound [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- JMANVNJQNLATNU-UHFFFAOYSA-N oxalonitrile Chemical compound N#CC#N JMANVNJQNLATNU-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 125000003367 polycyclic group Chemical group 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides an etching method of a 3D memory, which comprises the steps of forming a hard mask by using an SiON layer, etching to form a top selection gate layer groove and a step structure by using the hard mask, depositing a second silicon dioxide layer, depositing an interlayer dielectric layer, flattening the surface by adopting a chemical mechanical polishing process, removing the SiON layer, and then etching a channel through hole to form a plurality of channel through holes. The method combines the mask for forming the steps and the mask for forming the top selection gate line (TSG) into one mask, so that the etching of the initial step layer and the etching of the top selection gate line (TSG) groove are realized in the same step by using the same hard mask, the alignment of the step etching and the top selection gate groove etching is realized, the alignment precision is improved, and unnecessary errors are avoided.
Description
Technical Field
The invention relates to an etching method of a 3D memory.
Background
3D NAND memory is a technology for stacking data units, and stacking of more than 32 layers, even 72 layers of data units, has been achieved. The 3D NAND flash memory overcomes the limit of the practical expansion limit of the plane NAND flash memory, further improves the storage capacity, reduces the storage cost of each data bit and reduces the energy consumption.
In the fabrication of 3D NAND memory, the process of exposure transfer to the substrate is the core step, and a series of complex and time-consuming etching processes in semiconductor manufacturing are mainly performed by corresponding exposure machines, wherein the line width, overlay (overlay) accuracy and yield are the three important indexes for the development of etching technology.
The step making process and the preparation method of the top selection gate trench in the prior art are shown in fig. 1-4, and comprise the following steps: fig. 1 shows a semiconductor substrate (1) is provided, an oxide/nitride stack layer is deposited on the semiconductor substrate (1), and a SiON layer (4) is formed on top of the stack layer, as a hard mask layer, and a stepped stack layer is formed by etching from an initial step (SS 0, for short) layer by layer; fig. 2 shows that an interlayer dielectric (ILDC) layer is formed on the core region, a deposition region which is flush with the gate layer (4) and covers the entire step-type etching surface, i.e., an interlayer dielectric layer (5), is formed by oxide deposition, and a Chemical Mechanical Polishing (CMP) process is used to planarize the surface; FIG. 3 shows the SiON layer (4) being removed by etching and the surface being planarized by a chemical mechanical polishing process; figure 4 shows that a channel etch is performed to form the top gate layer trench (6).
The above process has a problem that alignment and overlay accuracy of a mask cannot be directly checked in an etching process of a step and a top select gate trench, so that overlay deviation is easily generated in step etching and top select gate trench etching. How to detect and avoid the alignment problem and the alignment deviation problem of the step etching and the top selection gate layer groove as much as possible is a technical problem to be solved at present.
Disclosure of Invention
The purpose of the invention is realized by the following technical scheme.
In view of the above existing problems, the present invention provides an etching method for a 3D memory, the method comprising:
providing a semiconductor substrate, depositing a first silicon oxide/silicon nitride stack layer on the semiconductor substrate, and forming a SiON layer on the top of the stack layer;
forming a hard mask by using the SiON layer, enabling the hard mask to have a pattern corresponding to the groove of the top selection gate layer, and etching to form the groove of the top selection gate layer by using the hard mask;
enabling the hard mask to have a mask pattern corresponding to the step structure, etching by utilizing the hard mask to form the step structure, and finally enabling the top layer of the step structure to be the hard mask layer pattern which is not etched partially;
depositing a second silicon oxide layer on the groove and the step area of the top selection gate layer, wherein the second silicon oxide layer fills the inside of the etched groove of the top selection gate layer and covers the surface of the step;
forming an interlayer dielectric layer on the whole device, and then carrying out surface planarization by adopting a chemical mechanical polishing process until the SiON layer is exposed;
removing the SiON layer;
and etching the channel through holes to form a plurality of channel through holes.
Preferably wherein the substrate comprises a single crystal material, single crystal SOI (Silicon-On-Insulator) structure.
The SiON layer is preferably grown using an in-situ moisture generation process (ISSG).
Preferably, the second silicon dioxide layer is formed using Atomic Layer Deposition (ALD).
Preferably, the SiON layer formed by the in-situ moisture generation process (ISSG) is removed using dry etching.
A 3D memory comprising a 3D memory made by any of the above methods.
The invention has the advantages that:
according to the etching process provided by the invention, the mask for forming the step and the mask for forming the top selection gate line (TSG) are combined into one mask, so that the etching of the step and the etching of the top selection gate line (TSG) are realized in the same hard mask and the same step, and compared with the prior art, the alignment of the step etching and the top selection gate groove etching is realized, the alignment precision is improved, and unnecessary errors are avoided.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIGS. 1-4 are schematic diagrams of a conventional etch process for forming a semiconductor;
FIGS. 5-11 are schematic diagrams of semiconductor etching processes in accordance with embodiments of the present invention.
Detailed Description
Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout the specification.
The invention discloses an etching process of a semiconductor, which comprises the following steps of:
step one, as shown in fig. 5, providing a semiconductor substrate (1), depositing a first silicon oxide (2)/silicon nitride (3) stack layer on the semiconductor substrate, and forming a SiON layer (4) on top of the stack layer as a substrate of a hard mask layer; the substrate (1) may comprise a bulk single crystal material, a single crystal SOI (Silicon-On-Insulator) structure, or other suitable substrate structures.
Step two, as shown in fig. 6, the SiON layer is used as a hard mask, the hard mask is made to have a pattern corresponding to the trench (Cut) of the top select gate layer (TSG) by etching, the patterned hard mask is used to etch and form the top select gate layer trench (TSG Cut) (6), and simultaneously, an initial step (SS 0) layer is formed.
Step three, as shown in fig. 7, making the hard mask have a mask pattern corresponding to the step structure, forming the step structure shown in fig. 7 by etching the hard mask and the silicon oxide (2)/silicon nitride (3) stacked layer for multiple times, and finally, the top layer of the step structure is the hard mask layer pattern which is not etched partially;
step four, as shown in fig. 8, depositing a second silicon oxide layer (7) on the trench and the step area of the top selection gate layer, wherein the second silicon oxide layer (7) is used for filling the inside of the trench (6) of the etched top selection gate layer (TSG) and covering the surface of the step;
step five, as shown in fig. 9, an interlayer dielectric layer (ILD) (8) is formed over the entire device. For example, the interlevel dielectric layer of low-k materials including, but not limited to, organic low-k materials (e.g., organic polymers containing aryl or polycyclic rings), inorganic low-k materials (e.g., amorphous carbon nitride films, polyboronitride films, fluorosilicone glass, BSG, PSG, BPSG), porous low-k materials (e.g., disiloxane (SSQ) -based porous low-k materials, porous silicon dioxide, porous SiOCH, C-doped silicon dioxide, F-doped porous amorphous carbon, porous diamond, porous organic polymers) may be formed by spray coating, spin coating, CVD deposition, and the like. Subsequently, carrying out surface planarization by adopting a Chemical Mechanical Polishing (CMP) process until the SiON layer (4) is exposed;
sixthly, as shown in FIG. 10, removing the SiON layer;
step seven, as shown in fig. 11, Channel Hole (CH for short) etching is performed to form a plurality of Channel holes (9).
Preferably, in the step one, an in-situ steam generation (ISSG) process is used to grow the SiON layer;
the SiON layer can be formed by the following steps:
In-Situ Steam oxidation (ISSG) process is used to form SiO on the surface of semiconductor substrate2A gate dielectric;
doping nitrogen into the gate dielectric by adopting a Decoupling Plasma Nitridation (DPN) process, thereby enabling SiO2The gate dielectric becomes an SiON gate dielectric;
Post-Nitridation annealing (PNA) is performed on the SiON gate dielectric to repair plasma damage in the dielectric and stabilize the doped N.
Preferably, the second silicon oxide layer (07) of the stepped structure is formed in step using Atomic Layer Deposition (ALD);
preferably, as shown in fig. 10, the SiON layer formed by the in-situ water vapor generation process is removed by dry etching;
in this embodiment, the etching gas for the dry etching includes NF3And NH3Or a mixture of (A) and (B) or comprises H2And NF3A mixture of (a).
By adopting the etching process provided by the invention, the mask for forming the steps and the mask for forming the top selection gate line (TSG) are combined into one mask, so that the etching of the initial step layer and the etching of the top selection gate line (TSG) groove are realized in the same step by using the same hard mask. Before etching the multi-step, a top select gate line (TSG) trench and an initial step layer are simultaneously formed in one step, and after etching the step, the top select gate line (TSG) trench is filled using an atomic layer deposition process. Compared with the prior art, the whole process method realizes the alignment of step etching and top selective gate groove etching, improves the alignment precision and avoids unnecessary errors.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (5)
1. A method of etching a 3D memory, the method comprising:
providing a semiconductor substrate, depositing a first silicon oxide/silicon nitride stacked layer on the semiconductor substrate, and forming a SiON layer on the top of the stacked layer by utilizing an in-situ water vapor generation process;
forming a hard mask by using the SiON layer, enabling the hard mask to have a pattern corresponding to the groove of the top selection gate layer, and etching to form the groove of the top selection gate layer by using the hard mask;
enabling the hard mask to have a mask pattern corresponding to the step structure, etching by utilizing the hard mask to form the step structure, and finally enabling the top layer of the step structure to be the hard mask layer pattern which is not etched partially;
depositing a second silicon oxide layer on the groove and the step area of the top selection gate layer, wherein the second silicon oxide layer fills the inside of the etched groove of the top selection gate layer and covers the surface of the step;
forming an interlayer dielectric layer on the whole device, and then carrying out surface planarization by adopting a chemical mechanical polishing process until the SiON layer is exposed;
removing the SiON layer;
and etching the channel through holes to form a plurality of channel through holes.
2. The method of claim 1, wherein the substrate comprises a single crystal material, a single crystal SOI structure.
3. The method of claim 1, wherein the second silicon dioxide layer is formed using atomic layer deposition.
4. The method of claim 1, wherein the SiON layer formed by the in-situ moisture generation process is removed using dry etching.
5. A 3D memory comprising a 3D memory made by the method of any of the preceding claims.
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| KR20210091822A (en) * | 2018-12-04 | 2021-07-22 | 선라이즈 메모리 코포레이션 | Method for forming multi-layer horizontal NOR-type thin film memory strings |
| KR102629727B1 (en) | 2019-02-11 | 2024-01-25 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Novel etching method by in situ formation of protective layer |
| CN112071755B (en) * | 2020-09-17 | 2024-04-23 | 长江存储科技有限责任公司 | Etching method and manufacturing method of three-dimensional memory |
| CN112397519B (en) * | 2020-11-16 | 2022-04-19 | 长江存储科技有限责任公司 | Semiconductor device and preparation method thereof |
| CN114758942B (en) * | 2022-03-24 | 2023-05-30 | 中国科学院光电技术研究所 | Reactive ion etching mask |
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| CN102569206A (en) * | 2010-12-30 | 2012-07-11 | 海力士半导体有限公司 | Non-volatile memory device and method of fabricating the same |
| CN103915398A (en) * | 2013-01-07 | 2014-07-09 | 爱思开海力士有限公司 | Semiconductor device and method of manufacturing the same |
| CN104396004A (en) * | 2012-05-23 | 2015-03-04 | 桑迪士克科技股份有限公司 | Multi-level contact to a 3d memory array and method of making |
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| JP2006128390A (en) * | 2004-10-28 | 2006-05-18 | Toshiba Corp | Semiconductor device and manufacturing method therefor |
| US8829646B2 (en) * | 2009-04-27 | 2014-09-09 | Macronix International Co., Ltd. | Integrated circuit 3D memory array and manufacturing method |
| US9911748B2 (en) * | 2015-09-28 | 2018-03-06 | Sandisk Technologies Llc | Epitaxial source region for uniform threshold voltage of vertical transistors in 3D memory devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102569206A (en) * | 2010-12-30 | 2012-07-11 | 海力士半导体有限公司 | Non-volatile memory device and method of fabricating the same |
| CN104396004A (en) * | 2012-05-23 | 2015-03-04 | 桑迪士克科技股份有限公司 | Multi-level contact to a 3d memory array and method of making |
| CN103915398A (en) * | 2013-01-07 | 2014-07-09 | 爱思开海力士有限公司 | Semiconductor device and method of manufacturing the same |
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