CN111540747B

CN111540747B - Method for manufacturing 3D memory device

Info

Publication number: CN111540747B
Application number: CN202010342461.2A
Authority: CN
Inventors: 李卫东; 徐伟; 周文斌
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-04-27
Filing date: 2020-04-27
Publication date: 2021-07-16
Anticipated expiration: 2040-04-27
Also published as: CN111540747A

Abstract

The application discloses a method of manufacturing a 3D memory device. The manufacturing method comprises the following steps: forming a sacrificial stacked structure on a substrate; forming a plurality of channel pillars and a plurality of dummy channel pillars penetrating the sacrificial stacked structure, the plurality of channel pillars and the plurality of dummy channel pillars being located in a cell region and a peripheral region adjacent to each other, respectively; forming a plurality of gate line slits through the openings of the resist mask; and replacing a plurality of sacrificial layers with a plurality of gate conductors using a plurality of gate line slits as an etching path and a deposition path to form a gate stack structure, wherein an opening width of the resist mask in the peripheral region varies with a distance from a boundary between the cell region and the peripheral region. The manufacturing method can form the grid line gap with the same width in the unit area and the peripheral area, thereby improving the product yield and reliability of the 3D memory device.

Description

Method for manufacturing 3D memory device

Technical Field

The present invention relates to a memory technology, and more particularly, to a method of manufacturing a 3D memory device.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration in multiples on a unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as non-volatile flash memories. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. The read speed is slightly slower in the NAND memory device compared to the NOR memory device, but the write speed is fast, the erase operation is simple, and a smaller memory cell can be realized, thereby achieving higher memory density. Therefore, the 3D memory device adopting the NAND structure is widely used.

There are complicated patterns in the 3D memory device, such as a first pillar array of a plurality of channel pillars (channel pillars) and a second pillar array of a plurality of dummy channel pillars (dummy pillars) formed in the cell region and the peripheral region, respectively. There is a large stress gradient in the transition region due to the large difference in pattern density between the two. After the channel pillars and the dummy channel pillars are formed, a gate line slit extending from the cell region to the peripheral region is further formed using etching. With the increasing storage density of the 3D memory device, the lateral etching rate difference generated by the internal structure difference of the intermediate structure of the 3D memory device becomes more and more obvious, resulting in the variation of the width of the gate line gap from the cell region to the peripheral region. The width change channel column of the gate line gap is exposed in the gate line gap to generate electric leakage, so that the product yield and reliability of the 3D memory device are reduced.

It is desirable to further improve the structure of the 3D memory device and the method of fabricating the same to improve the yield and reliability of the 3D memory device.

Disclosure of Invention

An object of the present invention is to provide an improved method of fabricating a 3D memory device, in which a lateral etching rate difference generated by an internal structure difference of an intermediate structure of the 3D memory device is pre-compensated using a variation in an opening width of a resist mask, thereby forming a gate line slit having a uniform width in a cell region and a peripheral region.

According to an aspect of the present invention, there is provided a method of manufacturing a 3D memory device, including: forming a sacrificial stacked structure on a substrate, the sacrificial stacked structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers which are alternately stacked; forming a plurality of channel pillars and a plurality of dummy channel pillars penetrating the sacrificial stacked structure, the plurality of channel pillars and the plurality of dummy channel pillars being located in a cell region and a peripheral region adjacent to each other, respectively; forming a plurality of gate line slits extending from the cell region to the peripheral region through openings of a resist mask and separating the plurality of sacrificial layers into a plurality of portions spaced apart from each other; and replacing the plurality of sacrificial layers with a plurality of gate conductors using the plurality of gate line slits as an etching path and a deposition path to form a gate stack structure, wherein an opening width of the resist mask in the peripheral region varies with a distance from a boundary between the cell region and the peripheral region.

Preferably, in the peripheral region, the number of the plurality of sacrificial layers through which the plurality of gate line slits penetrate decreases with a distance from a boundary between the cell region and the peripheral region.

Preferably, in the peripheral region, an opening width of the resist mask decreases as a distance from a boundary between the cell region and the peripheral region increases.

Preferably, the opening width of the resist mask changes stepwise or continuously.

Preferably, the plurality of sacrificial layers extend from the cell region to the peripheral region and are stepped in the peripheral region.

Preferably, the plurality of gate conductors extend from the cell region to the peripheral region and are stepped in the peripheral region.

Preferably, at least a portion of the plurality of gate conductors forms a stepped surface, and a stepped edge of a topmost level gate conductor of the plurality of gate conductors corresponds to a boundary between the cell region and the peripheral region.

Preferably, the plurality of gate line slits partition the plurality of gate conductors into a plurality of gate lines corresponding to the plurality of finger storage regions, respectively.

Preferably, the plurality of channel pillars are arranged in a first pillar array in the plurality of gate lines, respectively, and the plurality of dummy channel pillars are arranged in a second pillar array in the plurality of gate lines, respectively.

Preferably, the method further comprises the following steps: forming a common source region in the substrate, the plurality of channel pillars reaching the common source region.

According to the method of manufacturing the 3D memory device of this embodiment, the step structure is formed in the peripheral region, the number of the plurality of sacrificial layers penetrated by the plurality of gate line slits is gradually decreased as the distance from the boundary between the cell region and the peripheral region is increased, and the lateral etching rate of the etching of the plurality of gate line slits is gradually increased, and thus, the step structure of the peripheral region of the 3D memory device causes a difference in the lateral etching rate of the etching of the gate line slits. In the manufacturing method of an embodiment of the present invention, in the step of forming the plurality of gate line slits, the opening width of the resist mask is varied (e.g., the opening width of the mask is gradually decreased) with a distance from the boundary between the cell region and the peripheral region, thereby pre-compensating for the intermediate structure of the 3D memory device. Therefore, the gate line slit extends from the cell region to the peripheral region, and the gate line slits formed in the cell region and the peripheral region have substantially the same width. Therefore, the distance between the channel column in the cell region and the dummy channel column in the peripheral region is kept approximately the same as the distance between the gate line gaps, so that the phenomenon that the channel column is exposed in the gate line gap to cause electric leakage due to overlarge gate line gap can be avoided, the phenomenon that the storage transistor fails due to the generation of a hollow hole when the sacrificial laminated layer is replaced by the metal layer can be avoided, and the product yield and the reliability of the 3D memory device can be improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device.

Fig. 2 shows a perspective view of a 3D memory device.

Fig. 3a and 3b show a top view and a cross-sectional view of a 3D memory device.

Fig. 4 illustrates a mask and a top view used at a step of forming a gate line slit according to a related art 3D memory device manufacturing method.

Fig. 5 illustrates a top view of a mask and an intermediate structure used in a step of forming a gate line slit according to a method of manufacturing a 3D memory device according to an embodiment of the present invention.

Fig. 6 illustrates another mask used at the step of forming a gate line slit and a top view of an intermediate structure in a 3D memory device manufacturing method according to an embodiment of the present invention.

Fig. 7 to 10 show a top view and a cross-sectional view, respectively, of a main stage of a method of manufacturing a 3D memory device according to an embodiment of the present invention, wherein fig. 7a to 10a show a top view, respectively, and fig. 7b to 10b show a cross-sectional view, respectively.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly on another layer, another area, the expression "directly on … …" or "on … … and adjacent thereto" will be used herein.

In the present application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

In the 3D memory device of the NAND structure, gate conductors of the selection transistor and the memory transistor are provided in a stacked structure, channel layers of the selection transistor and the memory transistor and a dielectric stack between the gate conductors and the channel layers are provided in a channel pillar penetrating the stacked structure. The gate conductor is formed, for example, using an alternative process including removing the sacrificial layer using the gate line gap as an etch path and forming the gate conductor using the gate line gap as a deposition path. The gate line slit separates the plurality of gate conductors into a plurality of gate lines corresponding to a plurality of finger (finger) storage regions, respectively. The 3D memory device includes a cell region (cell region) for providing an active portion of a selection transistor and a memory transistor, and a peripheral region (parallel region) for providing an interconnection path between a gate conductor and a word line. The gate conductors at multiple levels may be stepped to provide contact surfaces for wordline interconnect channels. Therefore, the peripheral region is also referred to as a step region (standing step region). A plurality of channel columns are formed in a cell region of the 3D memory device, and a plurality of dummy channel columns are formed in a peripheral region to reduce device failure caused by stress generated due to pattern nonuniformity.

The inventor of the present invention has noticed that, although the above improved device design has been adopted, as the storage density of the 3D memory device is getting larger and larger, the thickness of the 3D memory device is getting larger and larger, and the widths of the gate line gaps formed in the cell region and the peripheral region are different, so that the distance between the channel pillar and the gate line gap in the peripheral region is too close, even directly connected, and the leakage between the channel pillar and the gate line, between the gate line and the gate line, and between the gate line and the gate line gap is significantly increased, so that the yield and reliability of the 3D memory device are reduced. The inventors of the present application have noticed the above-mentioned problems affecting the yield and reliability of the 3D memory device, and thus have proposed a further improved method of manufacturing the 3D memory device.

The present invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a bit line BL, and a second terminal is connected to a source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first select transistor Q1, memory transistors M1-M4, and a second select transistor Q2. The gate of the first select transistor Q1 is connected to a string select line SSL, and the gate of the second select transistor Q2 is connected to a ground select line GSL. The gates of the memory transistors M1 through M4 are connected to corresponding ones of the word lines WL1 through WL4, respectively.

As shown in fig. 1b, the first and second select transistors Q1 and Q2 of the memory cell string 100 include gate conductors 122 and 123, respectively, and the memory transistors M1 through M4 include gate conductors 121, respectively. The

gate conductors

121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. Channel pillar 110 extends through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are interposed between the gate conductor 121 and the channel layer 111, thereby forming memory transistors M1 through M4. A blocking dielectric layer 114 is sandwiched between the gate conductors 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are respectively composed of an oxide such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or a semiconductor, and the

gate conductors

121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 serves to provide channel regions for controlling the selection transistor and the memory transistor, and the doping type of the channel layer 111 is the same as that of the selection transistor and the memory transistor. For example, for N-type select and memory transistors, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure surrounding the core.

In this embodiment, the first and second selection transistors Q1 and Q2, the memory transistors M1 to M4 use the common channel layer 111 and the blocking dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layer and the blocking dielectric layer of the first and second selection transistors Q1 and Q2 and the semiconductor layer and the blocking dielectric layer of the memory transistors M1 to M4, respectively, may be formed in separate steps from each other.

In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 through M4 using FN tunneling efficiency. Taking memory transistor M2 as an example, while the source line SL is grounded, the ground selection line GSL is biased to a voltage of about zero volts, causing the selection transistor Q2 corresponding to the ground selection line GSL to be turned off, and the string selection line SGD is biased to a high voltage VDD, causing the selection transistor Q1 corresponding to the string selection line SGD to be turned on. Further, the bit line BL is grounded, the word line WL2 is biased at the programming voltage VPG, e.g. around 20V, and the remaining word lines are biased at the low voltage VPS 1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges stored in the charge storage layer 113 of the memory transistor M2.

In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer from the on-state of a selected one of the memory transistors M1 through M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS 2. The on state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that a data value can be determined according to the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the conductive state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2 shows a perspective view of a 3D memory device. Fig. 3a and 3b show a top view and a cross-sectional view of a 3D memory device. For clarity, the various insulating layers in the 3D memory device are not shown in fig. 2, 3a and 3b, as well as the bit lines connected to the channel pillars, the word lines connected to the gate conductors and their conductive channels.

The 3D memory device 100 includes a substrate 101 and a gate stack structure 120 on the substrate 101. The substrate 101 includes an N-type or P-type doped region therein as a common source region (not shown). The gate stack structure includes a plurality of gate conductors 121 stacked in a vertical direction, and an interlayer insulating layer (not shown) separating the plurality of gate conductors 121 from each other. The step edge of the gate conductor 121 of the topmost level among the plurality of gate conductors corresponds to a boundary between the cell area CA and the peripheral area SS. For example, the plurality of gate conductors 121 are formed using an alternative process. To this end, the gate conductor of each layer is divided into a plurality of gate lines by gate line slits (gate line slit) 105. The alternative process includes, for example, removing the sacrificial layer using the gate line slit 105 as an etching path, and forming a gate conductor using the gate line slit 105 as a deposition path. At least one gate line of the gate conductors at the same level is connected to the same word line.

Further, the 3D memory device 100 is divided into a cell region (cell region) CA and a peripheral region (parallel region) SS along a lateral direction. The former is used to provide the active portions of the select transistors and the memory transistors, and the latter is used to provide the interconnect channel between the gate conductor and the word line.

In the cell area CA, a plurality of channel pillars 110 penetrate the gate stack structure 120. The channel pillar 110 includes, for example, channel layers of a select transistor and a memory transistor and a dielectric stack between a gate conductor and the channel layers. The plurality of channel pillars 110 have first ends connected to bit lines and second ends connected to a common source region in the substrate 101. The first end of at least one of the plurality of channel pillars 110 is connected to the same bit line and accordingly forms one memory cell string.

The internal structure of the channel pillar 110 is shown in fig. 1b and will not be described in detail. In the middle portion of the channel pillar 110, the gate conductor layer 121 forms a memory transistor together with the channel layer 111, the tunnel dielectric layer 112, the charge storage layer 113, and the gate dielectric layer 114 inside the channel pillar 110. Preferably, at both ends of the channel pillar 110, a selection transistor may also be formed.

In the peripheral region SS, the plurality of gate conductors 121 may be stepped to provide a contact surface for a wordline interconnection channel, and thus, the peripheral region SS is also referred to as a step region (step region). A plurality of dummy channel pillars (dummy pillars) 130 penetrating the gate stack structure 120 are formed in the peripheral region SS. Since the pillar arrays are formed in the cell area CA and the peripheral area SS, respectively, device failure due to stress generated by pattern unevenness can be reduced.

In this embodiment, the internal structure of the dummy channel pillar 130 is, for example, the same as that of the channel pillar 110. The dummy channel pillar 130 is a passive channel structure, that is, the dummy channel pillar 130 is not electrically connected to the bit line, and the dummy channel pillar 130 and the gate conductor 121 are spaced apart from each other with an insulating layer therebetween. Accordingly, the dummy channel pillar 130 and the gate conductor 121 do not form any transistor. In an alternative embodiment, the internal structure of the dummy channel pillar 130 is different from the internal structure of the channel pillar 110. For example, the dummy channel pillars 130 are composed of an insulating material or include an insulating surface layer. The lateral dimension of the dummy channel pillar 130 may be the same as or different from the lateral dimension of the channel pillar 110.

In this embodiment, the plurality of gate conductors 121 extend from the cell area CA to the peripheral area SS, and a step structure is formed in the peripheral area SS. Since the gate stack structure 120 is formed using an alternative process, the gate line slit 105 is used to provide an etching path and a deposition path, and thus, the gate line slit 105 accordingly extends from the cell area CA to the peripheral area SS. The plurality of channel pillars 110 constitute a first pillar array, which is located in the cell area CA. The plurality of dummy channel pillars 130 constitute a second pillar array, and a portion of the second pillar array is located in the cell area CA and another portion is located in the peripheral area SS. The row pitch of the dummy channel pillars 130 adjacent to each other is greater than the row pitch of the channel pillars 110 adjacent to each other, and the column pitch of the dummy channel pillars 130 adjacent to each other is greater than the column pitch of the channel pillars 110 adjacent to each other.

In this embodiment, an alternative process is used to form the gate stack structure. Channel pillars 110 and dummy channel pillars 130 formed through the sacrificial stack structure are formed in the cell area CA and the peripheral area SS, respectively. A gate line slit 105 is further formed through the sacrificial stacked structure, the gate line slit 105 extending from the cell area CA to the peripheral area SS. However, the sacrificial layer in the sacrificial stack structure is removed through the gate line slit 105 to form a cavity, and the metal layer is filled through the gate line slit 105 to form a gate stack structure.

In the above-described method of manufacturing a 3D memory device using an alternative process for forming a gate stack structure, in the step of forming the gate line slit 105, a resist mask PR1 is used to cover the surface of the insulating layer 102 over the sacrificial stack structure. The portions of the layers of the sacrificial stack structure exposed through the openings of the resist mask PR1 are removed in turn using anisotropic etching, for example dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time so that the etching is stopped near the surface of the semiconductor substrate 101, the gate line slit 105 penetrating the sacrificial stack structure is formed.

The opening of the resist mask PR1 extends from the cell area CA to the peripheral area SS, and has a width W1 in both the cell area CA and the peripheral area. Although the gate line slit 105 should have the same pattern as the resist mask PR1 under ideal process conditions, in an actual semiconductor structure, the internal structural difference of the cell area CA and the peripheral area SS causes the width of the gate line slit 105 in the cell area CA and the peripheral area to vary accordingly.

In the cell area CA, etching performed when forming the gate line slit 105 needs to penetrate all the sacrificial layers and all the interlayer insulating layers of the sacrificial stack structure. In the peripheral region SS, due to the formation of the stepped structure of the sacrificial stacked structure, etching is only required to penetrate a part of the sacrificial layer and a part of the interlayer insulating layer of the sacrificial stacked structure. As the distance from the boundary between the cell area CA and the peripheral area SS becomes larger, the number of sacrificial layers and interlayer insulating layers that need to be penetrated by etching becomes smaller. The opening width of the resist mask varies correspondingly with the number of the plurality of sacrificial layers that need to be penetrated by the etching. As shown, the gate line slit 105 extends from the cell area CA to the peripheral area SS, and the width of the gate line slit 105 is increased as the distance from the boundary between the cell area CA and the peripheral area SS is increased.

The width of the grid line gap formed in the cell region is different from that of the grid line gap formed in the peripheral region, so that the distance between the channel column of the peripheral region and the grid line gap is too close, even the channel column is directly connected with the grid line gap, the electric leakage between the channel column and the grid line, between the grid line and the grid line gap is obviously increased, and the product yield and the reliability of the 3D storage device are reduced.

In the above-described method of manufacturing a 3D memory device using an alternative process for forming a gate stack structure, in the step of forming the gate line slit 105, a resist mask PR2 is used to cover the surface of the insulating layer 102 over the sacrificial stack structure. The portions of the layers of the sacrificial stack structure exposed through the openings of the resist mask PR2 are removed in turn using anisotropic etching, for example dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time so that the etching is stopped near the surface of the semiconductor substrate 101, the gate line slit 105 penetrating the sacrificial stack structure is formed.

The opening of the resist mask PR2 extends from the cell area CA to the peripheral area SS, and has a width W1 in the cell area CA, and the opening width of the resist mask PR2 changes stepwise from W1 to W3 in the peripheral area SS as the distance from the boundary between the cell area CA and the peripheral area SS becomes larger, and W3 is smaller than W1. The variation in the opening width of the resist mask PR2 is used to pre-compensate for a lateral etch rate difference generated by an internal structural difference of the intermediate structure of the 3D memory device.

In the cell area CA, etching performed when forming the gate line slit 105 needs to penetrate all the sacrificial layers and all the interlayer insulating layers of the sacrificial stack structure. In the peripheral region SS, since the sacrificial stack structure is formed with the step structure, etching only needs to penetrate a part of the sacrificial layer and a part of the interlayer insulating layer of the sacrificial stack structure. As the distance from the boundary between the cell area CA and the peripheral area SS is increased, the number of sacrificial layers and interlayer insulating layers to be etched through is decreased, and the lateral etching rate of the etching is increased, and thus, the lateral etching characteristic of the gate line slit etching is increased due to the step structure of the peripheral area of the 3D memory device. In this embodiment, the opening width of the resist mask is changed correspondingly with the number of the plurality of sacrificial layers that need to be penetrated by etching. As shown in the figure, as the distance from the boundary between the cell area CA and the peripheral area SS is larger, the opening width of the resist mask is smaller and smaller, so that the lateral etching rate difference of the gate line slit etching can be compensated. Therefore, in this embodiment, the lateral etching rate difference is pre-compensated for by the variation of the opening width of the resist mask, and thus the gate line slits 105 extend from the cell area CA to the peripheral area SS, and the widths of the gate line slits 105 are all substantially equal to the opening width W1 of the resist mask PR 2.

According to the 3D memory device method of the embodiment, the widths of the gate line gaps formed in the cell region and the peripheral region are substantially the same, and therefore, the distances between the gate line gaps and the channel pillars in the cell region CA and the dummy channel pillars in the peripheral region SS are substantially the same, so that leakage current caused by exposure of the channel pillars to the gate line gaps due to excessively large gate line gaps can be prevented, and failure of the memory transistor due to generation of voids when the sacrificial stack is replaced with a metal layer can be prevented, and thus the product yield and reliability of the 3D memory device can be improved.

In the above-described method of manufacturing a 3D memory device using an alternative process for forming a gate stack structure, in the step of forming the gate line slit 105, a resist mask PR3 is used to cover the surface of the insulating layer 102 over the sacrificial stack structure. The portions of the layers of the sacrificial stack structure exposed through the openings of the resist mask PR3 are removed in turn using anisotropic etching, for example dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time so that the etching is stopped near the surface of the semiconductor substrate 101, the gate line slit 105 penetrating the sacrificial stack structure is formed.

The opening of the resist mask PR3 extends from the cell area CA to the peripheral area SS, and has a width W1 in the cell area CA, and in the peripheral area SS, the opening width of the resist mask PR3 continuously changes from W1 to W3 with the distance from the boundary between the cell area CA and the peripheral area SS being larger, and W3 is smaller than W1. The variation in the opening width of the resist mask PR3 is used to pre-compensate for a lateral etch rate difference generated by an internal structural difference of the intermediate structure of the 3D memory device.

In the cell area CA, etching performed when forming the gate line slit 105 needs to penetrate all the sacrificial layers and all the interlayer insulating layers of the sacrificial stack structure. In the peripheral region SS, due to the formation of the stepped structure of the sacrificial stacked structure, etching is only required to penetrate a part of the sacrificial layer and a part of the interlayer insulating layer of the sacrificial stacked structure. As the distance from the boundary between the cell area CA and the peripheral area SS becomes larger, the number of sacrificial layers and interlayer insulating layers that need to be penetrated by etching becomes smaller. The opening width of the resist mask varies correspondingly with the number of the plurality of sacrificial layers that need to be penetrated by the etching. As shown, since the lateral etching rate difference is pre-compensated for by the variation of the opening width of the resist mask, the gate line slits 105 extend from the cell area CA to the peripheral area SS, and the width of the gate line slits 105 is substantially equal to the opening width W1 of the resist mask PR 3.

Fig. 7 to 10 show a top view and a cross-sectional view, respectively, of a main stage of a method of manufacturing a 3D memory device according to an embodiment of the present invention, wherein fig. 7a to 10a show a top view, respectively, and fig. 7b to 10b show a cross-sectional view taken along line AA, respectively. Unlike fig. 2, 3a and 3b, the various insulating layers in the 3D memory device are shown in fig. 7 to 10, however, for the sake of clarity, the bit lines connected to the channel pillars, the word lines connected to the gate conductors and their conductive channels are still not shown.

The manufacturing method starts with a semiconductor structure in which a sacrificial stack structure has been formed, as shown in fig. 7a and 7 b.

A sacrificial stack structure 140 in which interlayer insulating layers 122 and sacrificial layers 124 are alternately stacked is formed on the substrate 101. In this embodiment, the substrate 101 is, for example, a single crystal silicon substrate, the interlayer insulating layer 122 is, for example, composed of silicon oxide, and the sacrificial layer 124 is, for example, composed of silicon nitride.

As described below, multiple levels of sacrificial layer 124 in sacrificial stack 140 will be replaced with multiple levels of gate conductor in the gate stack. Therefore, the shape of the sacrificial layer 124 is substantially the same as the shape of the gate conductor.

In this step, a plurality of levels of the sacrificial layer 124 are patterned into a stepped structure such that a portion of the surface of the sacrificial layer 124 of each level is exposed with respect to the sacrificial layer 124 of an upper level to form a stepped surface. The interlayer insulating layers 122 separate the sacrificial layers 124 of the plurality of levels from each other. A cap insulating layer 102 is formed over the sacrificial stack structure 140. The insulating cover layer 102 fills the region above the step structure in the peripheral region, forming a continuous planar surface in the cell region and the peripheral region.

Further, a plurality of channel pillars 110 and a plurality of dummy channel pillars 130 penetrating the sacrificial stack structure are formed in the cell region and the peripheral region, respectively, as shown in fig. 8a and 8 b. For the sake of simplicity, the internal structures of the channel pillars 110 and the dummy channel pillars 130 are not shown in fig. 8a and 8 b.

As shown, a plurality of channel pillars 110 pass through the sacrificial stack structure 140 and make up a first array of pillars. A plurality of dummy channel pillars 130 pass through the sacrificial stack structure 140 and constitute a second pillar array.

Further, referring to fig. 1b, in the middle portion of the channel pillar 110, the channel pillar 110 includes a channel layer 111, a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114, which are sequentially stacked, and at both ends of the channel pillar 110, the channel pillar 110 includes the channel layer 111 and the blocking dielectric layer 114, which are sequentially stacked.

The internal structure of the dummy channel pillar 130 is, for example, the same as that of the channel pillar 110. In an alternative embodiment, the internal structure of the dummy channel pillar 130 is different from the internal structure of the channel pillar 110. For example, the dummy channel pillars 130 are composed of an insulating material or include an insulating surface layer.

In this embodiment, since the pillar arrays are formed in the cell area CA and the peripheral area SS, respectively, it is possible to reduce device failure due to stress caused by pattern unevenness.

Further, a gate line slit 105 is formed in the sacrificial stacked structure 140, as shown in fig. 9a and 9 b.

In this step, a resist mask, such as the resist mask PR2 shown in fig. 5 or the resist mask PR3 shown in fig. 6, is formed on the surface of the semiconductor structure. The openings of the resist masks PR2 and PR3 extend from the cell region CA to the peripheral region SS, and have a width W1 in the cell region CA, and in the peripheral region SS, the opening widths of the resist masks PR2 and PR3 change from W1 to W3 as the distance from the boundary between the cell region CA and the peripheral region SS becomes larger, and W3 is smaller than W1.

Then, anisotropic etching is performed via the resist mask. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time so that the etching stops near the surface of the substrate 101. The resist mask is removed by dissolving or ashing in a solvent after etching.

The gate line slit 105 is used to provide an etching path and a deposition path in a subsequent step. In the transverse direction, the gate line slit 105 extends from the cell area CA to the peripheral area SS. In the vertical direction, the gate line slit 105 extends from the surface of the sacrificial stack structure 140 down to the surface of the substrate 101, i.e., the gate line slit 105 penetrates through the sacrificial stack structure 140.

Further, the sacrificial layer 124 is removed using the gate line slit 105 as an etching path, and the gate conductor 121 is formed using the gate line slit 105 as a deposition path, as shown in fig. 10a and 10 b. This step is an alternative process, i.e. replacing the sacrificial layer 124 with the gate conductor 121.

In the etching process, the cavity is formed by removing the sacrificial layer 124 in the sacrificial stack structure 140 using isotropic etching.

The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. Etching gases are used as etchants in vapor phase etching, wherein the semiconductor structure is exposed to the etching gas. In the case where the interlayer insulating layer 122 and the sacrificial layer 124 in the sacrificial stacked structure 140 are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and C may be used in vapor phase etching₄F₈、C₄F₆、CH₂F₂And O₂One or more of (a). In the etching step, the gate line slit 105 is filled with an etchant. The end portion of the sacrificial layer 124 in the sacrificial stack structure 140 is exposed in the opening of the gate line slit 105, and thus, the sacrificial layer 124 is contacted to the etchant. The etchant gradually etches the sacrificial layer 124 from the opening of the gate line slit 105 toward the inside of the sacrificial stack structure 140. Due to the selectivity of the etchant, the etch is relative to the sacrificial stack 14The interlayer insulating layer 122 in 0 removes the sacrificial layer 124.

In the deposition process, a metal layer is filled in the gate line slit 105 and the cavity 104 using Atomic Layer Deposition (ALD).

In this embodiment, the metal layer is composed of tungsten, for example. The precursor gas used in atomic layer deposition is, for example, tungsten hexafluoride WF₆The reducing gas used is, for example, silane SiH₄Or diborane B₂H₆. In the step of atomic layer deposition, tungsten hexafluoride (WF) is used₆With silane SiH₄The chemical adsorption of the reaction product to obtain the tungsten material to realize the deposition process.

A metal layer may be formed on the surface of the nucleation layer to improve chemisorption characteristics of precursor gases on the surface during atomic layer deposition and may improve adhesion strength of the metal layer on the interlayer insulating layer 122.

Further, a resist mask is formed on the surface of the semiconductor structure, and then an etch back (etch back) is performed to newly form the gate line slit 105 in the metal layer.

The etch back uses sulfur fluoride, nitrogen and chlorine as etchants to remove the tungsten material of the gate line gap 105. Further, the gate line slit 105 not only separates the metal layer into different layers to form the gate conductor layers 121, 122, and 123, but also separates the gate conductor of each layer into a plurality of gate lines.

The gate conductors 121 formed in this step are alternately stacked with interlayer insulating layers 122, thereby forming a gate stack structure 120. The gate conductor layer 121 in the gate stack structure 120 replaces the sacrificial layer 124 in the sacrificial stack structure 140, as compared to the sacrificial stack structure 140. The step edge of the gate conductor 121 of the topmost level among the gate conductors 121 corresponds to the boundary between the cell area CA and the peripheral area SS.

Preferably, ion implantation is performed using the gate line slit 105 to form doped regions of N-type (using an N-type dopant, e.g., P, As) or P-type (using a P-type dopant, e.g., B) in the substrate 101. The doped region serves as a contact region for the common source region. The source lines SL are connected to the common source region via the doped regions.

Preferably, the gate line slits 105 are filled with an insulating material, and then a plurality of bit lines (not shown) are formed in the cell area CA of the 3D memory device 100 and a plurality of word lines (not shown) are formed in the peripheral area SS of the 3D memory device 100. The plurality of bit lines are electrically connected to a first end of at least one of the channel pillars 110, respectively, and the plurality of word lines are electrically connected to at least one gate line of the gate conductor of a corresponding one of the layers via a conductive channel, respectively.

One memory cell string of the 3D memory device 100 includes at least one channel pillar 110 connected to the same bit line.

According to the 3D memory device method of this embodiment, in the step of forming the gate line slit, a lateral etching rate difference generated by an internal structural difference of the 3D memory device intermediate structure is pre-compensated using a variation in the opening width of the resist mask. Therefore, the gate line slit 105 extends from the cell area CA to the peripheral area SS, and the gate line slits formed in the cell area CA and the peripheral area SS have substantially the same width. Therefore, the distance between the channel pillar in the cell area CA and the dummy channel pillar in the peripheral area SS is kept approximately the same as the distance between the gate line gaps, so that the phenomenon that the channel pillar is exposed in the gate line gap to cause electric leakage due to overlarge gate line gap can be avoided, the phenomenon that the storage transistor fails due to the generation of a hollow hole when the sacrificial laminate is replaced by the metal layer can be avoided, and the product yield and the reliability of the 3D memory device can be improved.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A method of manufacturing a 3D memory device, comprising:

forming a sacrificial stacked structure on a substrate, the sacrificial stacked structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers which are alternately stacked;

forming a plurality of channel pillars and a plurality of dummy channel pillars penetrating the sacrificial stacked structure, the plurality of channel pillars and the plurality of dummy channel pillars being located in a cell region and a peripheral region adjacent to each other, respectively;

etching the sacrificial stack structure through an opening of a resist mask to form a plurality of gate line slits extending from the cell region to the peripheral region and separating the plurality of sacrificial layers into a plurality of parts spaced apart from each other;

replacing the plurality of sacrificial layers with a plurality of gate conductors using the plurality of gate line slits as an etch path and a deposition path to form a gate stack structure,

wherein the sacrificial stacked structure is formed with a step structure in the peripheral region, the number of the plurality of sacrificial layers penetrated by the plurality of gate line slits is gradually reduced to cause the lateral etching speed of the plurality of gate line slits to be gradually increased, and the opening width of the resist mask is varied with the distance from the boundary between the cell region and the peripheral region to pre-compensate the lateral etching speed difference of the plurality of gate line slits.

2. The manufacturing method according to claim 1, wherein in the peripheral region, an opening width of the resist mask decreases as a distance from a boundary between the cell region and the peripheral region increases.

3. The manufacturing method according to claim 2, wherein an opening width of the resist mask changes stepwise or continuously.

4. The manufacturing method according to claim 1, wherein the plurality of sacrificial layers extend from the cell region to the peripheral region and are stepped in the peripheral region.

5. The manufacturing method according to claim 1, wherein the plurality of gate conductors extend from the cell region to the peripheral region and are stepped in the peripheral region.

6. The manufacturing method according to claim 5, wherein at least a part of the plurality of gate conductors forms a stepped surface, and a stepped edge of a topmost level gate conductor among the plurality of gate conductors corresponds to a boundary between the cell region and the peripheral region.

7. The method of manufacturing of claim 1, wherein the plurality of gate line slits separate the plurality of gate conductors into a plurality of gate lines corresponding to a plurality of finger storage regions, respectively.

8. The method of manufacturing of claim 7, wherein the plurality of channel pillars are arranged in a first pillar array in the plurality of gate lines, respectively, and the plurality of dummy channel pillars are arranged in a second pillar array in the plurality of gate lines, respectively.

9. The manufacturing method according to claim 1, further comprising: forming a common source region in the substrate, the plurality of channel pillars reaching the common source region.