CN109148453B - Method of manufacturing semiconductor device and 3D memory device - Google Patents

Method of manufacturing semiconductor device and 3D memory device Download PDF

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Publication number
CN109148453B
CN109148453B CN201811095237.7A CN201811095237A CN109148453B CN 109148453 B CN109148453 B CN 109148453B CN 201811095237 A CN201811095237 A CN 201811095237A CN 109148453 B CN109148453 B CN 109148453B
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gate
stack structure
interlayer insulating
gate stack
insulating layer
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CN109148453A (en
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胡斌
肖莉红
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

The application discloses a method of manufacturing a semiconductor device and a 3D memory device. The method comprises the following steps: forming an insulating laminated structure including first and second interlayer insulating layers alternately stacked on a semiconductor substrate; forming an isolation structure through the insulating stack structure; replacing the first interlayer insulating layer on one side of the isolation structure with a gate conductor to form a first gate stack structure; and replacing the second interlayer insulating layer on the other side of the isolation structure with a gate conductor to form a second gate stack structure, wherein the first isolation structure separates the first gate stack structure from the second gate stack structure, and the gate conductor of the first gate stack structure and the gate conductor of the second gate stack structure are arranged in a staggered manner in a direction perpendicular to the surface of the semiconductor substrate. The gate conductor of the first gate stack structure and the gate conductor of the second gate stack structure are arranged in a staggered mode, so that the storage density of the semiconductor device is increased, and the space utilization rate of the semiconductor device is improved.

Description

Method of manufacturing semiconductor device and 3D memory device
Technical Field
The present invention relates to a memory technology, and more particularly, to a method of manufacturing a semiconductor device and a 3D memory device.
Background
The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As feature sizes of semiconductor manufacturing processes become smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a 3D memory device) has been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can increase integration density by a multiple on a unit area of a wafer, and can reduce cost.
The existing 3D memory device is mainly used as a nonvolatile flash memory. Two major non-volatile flash memory technologies employ NAND and NOR architectures, respectively. The read speed is slightly slower in the NAND memory device compared to the NOR memory device, but the write speed is fast, the erase operation is simple, and a smaller memory cell can be realized, thereby achieving higher memory density. Therefore, the 3D memory device adopting the NAND structure is widely used.
In the 3D memory device with the NAND structure, the 3D memory device mainly comprises a gate stack structure, a channel column penetrating through the gate stack structure and a conductive channel, wherein the gate stack structure is used for providing gate conductors of a selection transistor and a storage transistor, the channel column is used for providing channel layers and gate dielectric stacks of the selection transistor and the storage transistor, and the conductive channel is used for realizing interconnection of memory cell strings. However, as the number of layers of the gate stack structure increases, the number of gate conductors and the number of insulating layers for separating the gate conductors in the gate stack structure increase at the same time, and the insulating layers occupy a large amount of space in the 3D memory device, thereby not only increasing the size of the 3D memory device, but also reducing the space utilization.
It is desirable to further improve the method of manufacturing the semiconductor device and the structure of the 3D memory device so as to increase the memory density of the 3D memory device and to reduce the size of the 3D memory device.
Disclosure of Invention
In view of the above, it is an object of the present invention to provide an improved method of manufacturing a semiconductor device and a 3D memory device.
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: forming an insulating laminated structure including first and second interlayer insulating layers alternately stacked on a semiconductor substrate; forming an isolation structure through the insulating stack structure; replacing the first interlayer insulating layer on one side of the isolation structure with a gate conductor to form a first gate stack structure; and replacing the second interlayer insulating layer on the other side of the isolation structure with a gate conductor to form a second gate stack structure, wherein the first isolation structure separates the first gate stack structure from the second gate stack structure, and the gate conductor of the first gate stack structure and the gate conductor of the second gate stack structure are arranged in a staggered manner in a direction perpendicular to the surface of the semiconductor substrate.
Preferably, the step of forming the gate conductor in place of the first interlayer insulating layer includes: removing the first interlayer insulating layer on one side of the first isolation structure through the gate line gap by adopting an etching process to form a cavity; and filling a gate conductor material into the cavity through the gate line gap.
Preferably, the step of forming the gate conductor in place of the second interlayer insulating layer includes: removing the second interlayer insulating layer on one side of the first isolation structure through the gate line gap by adopting an etching process to form a cavity; and filling a gate conductor material into the cavity through the gate line gap.
Preferably, the material of the first interlayer insulating layer is selected from one of an oxide and a nitride, and the material of the second interlayer insulating layer is selected from the other of an oxide and a nitride.
Preferably, the material of the first isolation structure comprises silicon carbide.
According to another aspect of the present invention, there is provided a 3D memory device formed using the above method of manufacturing a semiconductor device.
Preferably, a plurality of channel pillars are included, penetrating the gate stack structure, wherein a gate conductor at one side of the channel pillar corresponds to a position of an interlayer insulating layer at the other side of the channel pillar.
According to the method for manufacturing the semiconductor device, the first isolation structure is arranged through the first interlayer insulating layers and the second interlayer insulating layers which are alternately stacked, the first interlayer insulating layers on one sides of the first isolation structures are respectively replaced by the gate conductors, the second interlayer insulating layers on the other sides of the first isolation structures are replaced by the gate conductors, the purpose of staggering the gate conductors of the first gate stack structures and the gate conductors of the second gate stack structures is achieved, therefore, under the condition that the size of the semiconductor device is not changed, the space in the semiconductor device can be fully utilized to form more structures, and the space utilization rate is improved.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1a and 1b show an equivalent circuit diagram and a structural schematic diagram of a memory cell string of a 3D memory device, respectively.
Fig. 2a illustrates a perspective view of a 3D memory device according to a first embodiment of the present invention.
Fig. 2b illustrates a perspective view of a 3D memory device according to a second embodiment of the present invention.
Fig. 3, 4, 6, 7, 9, 10, 12 to 14 are sectional views illustrating stages of a method of manufacturing a 3D memory device according to a second embodiment of the present invention.
Fig. 5, 8, 11 show top views of various stages of a method of manufacturing a 3D memory device according to a second embodiment of the present invention.
Fig. 15a to 16c are schematic diagrams illustrating an effect analysis of a 3D memory device according to an embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not drawn to scale. Moreover, certain well-known elements may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, one layer or region may be "under" or "beneath" another layer or region.
If the description is directed to the case of being directly on another layer or another region, the description will be given by the expression "directly on 8230; \8230; above or" on 8230; \8230; above and adjacent to it ".
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 1a and 1b show a circuit diagram and a structural schematic diagram, respectively, of a memory cell string of a 3D memory device. The case where the memory cell string includes 4 memory cells is shown in this embodiment. It is understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.
As shown in fig. 1a, a first terminal of the memory cell string 100 is connected to a Bit Line (BL), and a second terminal is connected to a Source Line (SL). The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first selection transistor Q1, memory transistors M1 to M4, and a second selection transistor Q2. The Gate of the first select transistor Q1 is connected to a string select line (SGD), and the Gate of the second select transistor Q2 is connected to a Source select line (SGS). Gates of the memory transistors M1 to M4 are connected to corresponding ones of Word lines (Word-Line) WL1 to WL4, respectively.
As shown in fig. 1b, select transistors Q1 and Q2 of memory cell string 100 include gate conductors 122 and 123, respectively, and memory transistors M1 through M4 include gate conductor 121, respectively. The gate conductors 121, 122, and 123 correspond to a stacking order of transistors in the memory cell string 100, and adjacent gate conductors are spaced apart from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 is adjacent to or through the gate stack structure. In the middle portion of the channel pillar 110, a tunnel dielectric layer 112, a charge storage layer 113, and a gate dielectric layer 114 are interposed between the gate conductor 121 and the channel layer 111, thereby forming memory transistors M1 to M4. A gate dielectric layer 114 is sandwiched between the gate conductors 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming selection transistors Q1 and Q2.
In this embodiment, channel layer 111 is composed of, for example, polysilicon, tunnel dielectric layer 112 and gate dielectric layer 114 are composed of, respectively, an oxide such as silicon oxide, charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals such as silicon nitride containing particles of a metal or semiconductor, and gate conductors 121, 122, and 123 are composed of a metal such as tungsten. The channel layer 111 is used to provide channel regions of the control select transistor and the control transistor, and the doping type of the channel layer 111 is the same as the type of the select transistor and the control transistor. For example, for an N-type select transistor and control transistor, the channel layer 111 may be N-type doped polysilicon.
In this embodiment, the core of channel pillar 110 is channel layer 111, and tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure surrounding the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunnel dielectric layer 112, charge storage layer 113, and gate dielectric layer 114 form a stacked structure surrounding the semiconductor layers.
In this embodiment, the selection transistors Q1 and Q2, and the memory transistors M1 to M4 use the common channel layer 111 and gate dielectric layer 114. In the channel pillar 110, the channel layer 111 provides source-drain regions and a channel layer of a plurality of transistors. In an alternative embodiment, the semiconductor layers and the gate dielectric layers of the selection transistors Q1 and Q2 and the semiconductor layers and the gate dielectric layers of the memory transistors M1 to M4 may be formed separately in steps independent of each other. In the channel column 110, the semiconductor layers of the selection transistors Q1 and Q2 and the semiconductor layers of the memory transistors M1 to M4 are electrically connected to each other.
In a write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 to M4 using FN tunneling. Taking the memory transistor M2 as an example, while the source line SL is grounded, the source select line SGS is biased to a voltage of about zero volts so that the select transistor Q2 corresponding to the source select line SGS is turned off, and the string select line SGD is biased to a high voltage VDD so that the select transistor Q1 corresponding to the string select line SGD is turned on. Further, bit line BL2 is grounded, word line WL2 is biased at a programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons of the channel region of the memory transistor M2 reach the charge storage layer 113 through the tunneling dielectric layer 112, thereby converting data into charges to be stored in the charge storage layer 113 of the memory transistor M2.
In a read operation, the memory cell string 100 determines the amount of charge in the charge storage layer according to the on-state of a selected one of the memory transistors M1 to M4, thereby obtaining data indicative of the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS2. The conduction state of the memory transistor M2 is related to its threshold voltage, i.e., the amount of charge in the charge storage layer, so that the data value can be judged according to the conduction state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in a conductive state, and therefore, the conductive state of the memory cell string 100 depends on the conductive state of the memory transistor M2. The control circuit judges the on state of the memory transistor M2 based on the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.
Fig. 2a illustrates a perspective view of a 3D memory device according to a first embodiment of the present invention. For clarity, only a portion of the first isolation structure 102 is shown in fig. 2a, and other insulating layers in the 3D memory device of the first embodiment of the present invention are not shown.
As shown in fig. 2a, the 3D memory device shown in the present embodiment includes: the semiconductor device includes a semiconductor substrate 101, a plurality of channel pillars 110 located above the semiconductor substrate 101, a first gate stack structure 120a and a second gate stack structure 120b located above the semiconductor substrate 101 and adjacent to the channel pillars 110, and a first isolation structure 102 penetrating the channel pillars 110, wherein the first gate stack structure 120a includes a plurality of gate conductors 121a, 122a, 123a and a plurality of interlayer insulating layers which are alternately stacked, and the second gate stack structure 120b includes a plurality of gate conductors 121b, 122b, 123b and a plurality of interlayer insulating layers which are alternately stacked.
The plurality of channel pillars 110 are arranged in an array, each column of channel pillars 110 is staggered with the adjacent columns of channel pillars 110, the channel pillars 110 in the same column are separated and equally divided by the same first isolation structure 102, and meanwhile, the first isolation structure 102 also separates the first gate stack structure 120a from the second gate stack structure 120b.
The gate conductors 121a, 122a, 123a of the first gate stack structure 120a and the gate conductors 121b, 122b, 123b of the second gate stack structure 120b are arranged to be staggered in a direction perpendicular to the surface of the semiconductor substrate 101, so that the 3D memory device shown in the present embodiment includes 2 × n memory cell strings in total, where n is the number of the channel pillars 110.
Fig. 2b illustrates a perspective view of a 3D memory device according to a second embodiment of the present invention. For clarity, the various insulating layers in the 3D memory device are not shown in fig. 2 b.
As shown in fig. 2b, the 3D memory device shown in the present embodiment includes: the semiconductor device includes a semiconductor substrate 101, a plurality of channel pillars 110 located above the semiconductor substrate 101, a first gate stack structure 120a and a second gate stack structure 120b located above the semiconductor substrate 101 and adjacent to the channel pillars 110, a first isolation structure 102 penetrating the channel pillars 110, and a gate line slit 103 penetrating the gate stack structures, wherein the first gate stack structure 120a includes a plurality of gate conductors 121a, 122a, 123a and a plurality of interlayer insulating layers which are alternately stacked, and the second gate stack structure 120b includes a plurality of gate conductors 121b, 122b, 123b and a plurality of interlayer insulating layers which are alternately stacked.
The plurality of channel pillars 110 are arranged in an array, and are located between the gate line gaps 103, each column of channel pillars 110 is arranged in a staggered manner with the adjacent columns of channel pillars 110, the gate stack structures on both sides of the channel pillars 110 are separated by the first isolation structures penetrating through the channel pillars 110, the gate conductors on one side of the channel pillars 110 are opposite to the interlayer insulating layers on the other side, so that the staggered arrangement of the gate conductors is realized, and in addition, the gate conductors on both sides of the channel pillars 110 are respectively separated into at least two parts by the second isolation structures, so that the 3D memory device shown in the embodiment includes 4n memory cell strings in total of 2 × n, wherein n is the number of the channel pillars 110.
In the 3D memory device of the present embodiment, each channel pillar 110 is divided into 4 parts by the isolation structure, and the memory cell strings respectively include the parts corresponding to the respective channel pillars 110 and the gate conductors. The gate conductors correspond to a stacking sequence of transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure.
Preferably, CMOS circuitry is included in the substrate semiconductor substrate 101, for example. Conductive vias are used to provide electrical connections between the CMOS circuitry and external circuitry.
Preferably, the 3D memory device shown in the present embodiment further includes dummy channel pillars 140 for providing a mechanical supporting function.
Fig. 3, 4, 6, 7, 9, 10, 12 to 14 show cross-sectional views of stages of a method of manufacturing a 3D memory device according to a second embodiment of the present invention, and fig. 5, 8 and 11 show top views of stages of the method of manufacturing a 3D memory device according to the second embodiment of the present invention. The following describes the method for manufacturing the memory structure of the invention in detail with reference to fig. 3 to 14.
The method of fabricating the 3D memory device of the present embodiment starts with a semiconductor substrate 101, and forms an insulating stack structure 130 on the semiconductor substrate 101, as shown in fig. 3.
In this step, a first interlayer insulating layer 131 and a second interlayer insulating layer 132 may be stacked on the semiconductor substrate 101 using a deposition process, wherein the material of the first interlayer insulating layer 131 is selected from one of an oxide and a nitride, and the material of the second interlayer insulating layer 132 is selected from the other of an oxide and a nitride. In this embodiment, the material of the first interlayer insulating layer 131 is an oxide, and the material of the second interlayer insulating layer 132 is a nitride.
Further, a plurality of first isolation structures 102 are formed through the insulating stack structure 130, the first isolation structures 102 extending into the semiconductor substrate 101, as shown in figure 4,
in this step, the insulating stacked structure 130 and a portion of the semiconductor substrate 101 may be patterned by using an etching process to form a plurality of gaps, and the gaps are filled with a material for forming the first isolation structure 102, wherein the material of the first isolation structure 102 includes silicon carbide.
further,base:Sub>A plurality of channel pillars 110 are formed through the insulation stack structure 130, as shown in fig. 5 to 7, wherein fig. 6 isbase:Sub>A cross-sectional view taken alongbase:Sub>A-base:Sub>A line or B-B line in fig. 5, and fig. 7 isbase:Sub>A cross-sectional view taken along C-C line in fig. 5.
In this step, the insulating stacked layer structure 130 may be patterned by using an etching process to form a plurality of channel holes, and then a gate dielectric layer 114, a charge storage layer 113, a tunneling dielectric layer 112, and a channel layer 111 are sequentially formed on the inner wall of the channel holes, and finally a contact region 115 is formed so that the channel pillar 110 forms a source contact through the semiconductor substrate 101. Wherein the first isolation structure 102 separates the insulating stack 130 on both sides of the channel pillar 110.
Preferably, the first isolation structures 102 equally divide the channel pillars 110 in the first direction.
Preferably, in this step, a dummy channel pillar penetrating the insulation stack structure 130 may also be formed, which may be the same as or different from the inner structure of the channel pillar 110, and which penetrates at least a portion of the gate conductor in the gate stack structure. In the final 3D memory device, the dummy channel pillars are not connected to bit lines, and are not used to form a selection transistor and a memory transistor. Therefore, the dummy channel pillar does not form an effective memory cell.
Further, a gate line slit 103 is formed through the insulating stack structure 130 and around the plurality of channel pillars 110, as shown in fig. 5 and 6, wherein the plurality of channel pillars 110 are located between the gate line slits 103.
Further, the second isolation structure 104 is formed through the insulation stack structure 130 and the plurality of channel pillars 110, as shown in fig. 5 and 6.
In this step, the insulating stacked structure 130 may be patterned by using an etching process to form a plurality of gaps, and the gaps are filled with a material for forming the second isolation structure 104, and the insulating stacked structure 130 on both sides of the trench pillar 110 is separated into two parts by the second isolation structure 104, respectively, wherein the material of the second isolation structure 104 includes an oxide.
Preferably, the second isolation structures 104 equally divide the channel pillars 110 in a second direction, the first direction being 90 degrees from the second direction.
Further, the second interlayer insulating layer 132 on the first isolation structure 102 side is removed by isotropic etching using the gate line slit 103 as an etchant channel to form the cavity 105, as shown in fig. 8 and 9, and fig. 9 isbase:Sub>A cross-sectional view taken alongbase:Sub>A-base:Sub>A line in fig. 8.
In this step, the isotropic etching may employ selective wet etching or vapor phase etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. Etching gases are used as etchants in vapor phase etching, wherein the semiconductor structure is exposed to the etching gas. In the case where the first interlayer insulating layer 131 and the second interlayer insulating layer 132 in the insulating stacked layer structure 130 are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and C may be used in vapor phase etching 4 F 8 、C 4 F 6 、CH 2 F 2 And O 2 One or more of (a). In the etching step, the gate line slit 103 is filled with an etchant. An end portion of the second interlayer insulating layer 132 in the insulating stack structure 130 is exposed in the opening of the gate line slit 103, and thus, the second interlayer insulating layer 132 is contacted to the etchant. The etchant gradually etches the second interlayer insulating layer 132 from the opening of the gate line slit 103 toward the inside of the insulating laminated structure 130. The etching removes the second interlayer insulating layer 132 with respect to the first interlayer insulating layer 131 in the insulating stack structure 130 due to the selectivity of the etchant. And the second interlayer insulating layer 132 at the other side of the channel pillar 110 is not etched by the etchant due to the blocking of the first isolation structure 102.
Further, the first interlayer insulating layer 131 on the other side of the first isolation structure 102 is removed by isotropic etching using the gate line slit 103 as an etchant channel to form a cavity 105, as shown in fig. 8 and 10, wherein fig. 10 is a cross-sectional view taken along line B-B of fig. 8.
In this step, the method of removing the first interlayer insulating layer 131 is similar to the method of removing the second interlayer insulating layer 132, and is not described herein again.
further,base:Sub>A gate conductor is formed by fillingbase:Sub>A metal layer in the gate line slit 103 and the cavity 105 using Atomic Layer Deposition (ALD) using the gate line slit 103 asbase:Sub>A deposition channel, and then an etch back (etch back) is performed to re-form the gate line slit 103, as shown in fig. 11 to 14, in which fig. 12 isbase:Sub>A cross-sectional view taken alongbase:Sub>A-base:Sub>A line in fig. 11, fig. 13 isbase:Sub>A cross-sectional view taken alongbase:Sub>A B-B line in fig. 11, and fig. 14 isbase:Sub>A cross-sectional view taken alongbase:Sub>A C-C line in fig. 11.
In this embodiment, the metal layer is composed of tungsten, for example. The gate conductors (121 a, 122a, 123 a) on the first isolation structure 102 side replace the first interlayer insulating layer 131 in the insulating stack structure 130 to form a first gate stack structure 120a. The gate conductors (121 b, 122b, 123 b) on the other side of the first isolation structure 102 replace the second interlayer insulating layer 132 in the insulating stack structure 130 to form a second gate stack structure 120b.
Fig. 15a to 16c are diagrams illustrating an effect analysis of a 3D memory device according to an embodiment of the present invention.
As shown in fig. 15a to 15c, fig. 15b is a cross-sectional view of the nth layer and the corresponding portion of the channel pillar in the gate stack structure of fig. 15a along the XY plane, and fig. 15c is a cross-sectional view of the N +1 th layer and the corresponding portion of the channel pillar in the gate stack structure of fig. 15a along the XY plane.
In an ideal process, if the memory cell of the 3D memory device is to be added, the number of stacked layers of the gate stack structure needs to be increased, and specifically, the number of layers of the gate conductor 121' needs to be increased, so as to increase the memory cell formed by the channel pillar 110' and the gate conductor 121', and in order to achieve electrical isolation between the gate conductors 121', an interlayer insulating layer 130' needs to be formed between the added gate conductors 121', so that the size of the 3D memory device is also increased, and in practical applications, the gate stack structure has more than 40% of space in the Z direction occupied by the interlayer insulating layer 130', which results in a large amount of resources wasted in the Z direction, for example, for a 64-layer 3D memory device, there are actually 64 layers of gate line metal (gate conductor 121 ') and 64 layers of dielectric (interlayer insulating layer 130 '), which wastes nearly half of space in the Z direction of the 3D memory device.
As shown in fig. 16a to 16c, fig. 16b is a cross-sectional view of the nth layer and the corresponding portion of the channel pillar in the gate stack structure of fig. 16a taken along the XY plane, and fig. 16c is a cross-sectional view of the N +1 th layer and the corresponding portion of the channel pillar in the gate stack structure of fig. 16a taken along the XY plane.
In the embodiment of the present invention, if a memory cell of the 3D memory device is to be added, it is only necessary to stagger the gate conductor 121a on one side of the channel pillar 110 from the gate conductor 121b on the other side of the channel pillar 110, so that staggered layers of the gate conductors 121a and 121b are realized in the Z direction, and the memory cell is continuously present in each layer in the Z direction, that is, in the gate stack structure, the portion of the channel pillar 110 corresponding to each layer including the interlayer insulating layer is fully utilized to form a memory cell with the gate conductors 121a and 121b, thereby increasing the memory density by at least 1 time in the Z direction.
In addition, by forming the second isolation structure 103 penetrating the channel pillar 110 and the gate stack structure, the staggered gate conductors 121a and 121b on both sides of the channel pillar 110 are respectively divided into two, and in each layer, the number of memory cells on each side of the channel pillar 110 is two.
In combination with the improvement in the three directions of XYZ, the memory density of the 3D memory device is increased to at least 4 times of the original density, and the size of the 3D memory device is not increased, so that the effect of reducing the size of the 3D memory device is achieved compared with an ideal process.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.

Claims (7)

1. A method of manufacturing a semiconductor device including a 3D memory device, the method comprising:
forming an insulating laminated structure including first and second interlayer insulating layers alternately stacked on a semiconductor substrate;
forming a first isolation structure penetrating through the insulation stack structure;
forming a channel pillar penetrating the insulating stacked structure, the channel pillar including a charge storage layer, the first isolation structure dividing the channel pillar into a first portion and a second portion along a first direction, the first direction being perpendicular to a thickness direction of the insulating stacked structure;
replacing the first interlayer insulating layer adjacent to the first portion of the channel pillar with a gate conductor to form a first gate stack structure; and
replacing the second interlayer insulating layer adjacent to the second portion of the channel pillar with a gate conductor to form a second gate stack structure,
the first isolation structure separates the first gate stack structure from the second gate stack structure, and the gate conductors of the first gate stack structure and the second gate stack structure are arranged in a staggered mode in a direction perpendicular to the surface of the semiconductor substrate.
2. The method of claim 1, wherein the step of forming the gate conductor in place of the first interlayer insulating layer comprises:
removing the first interlayer insulating layer on one side of the first isolation structure through a gate line gap penetrating through the insulation laminated structure by adopting an etching process to form a cavity; and
and filling a grid conductor material into the cavity through the grid line gap.
3. The method of claim 1, wherein the step of forming the gate conductor in place of the second interlayer insulating layer comprises:
removing the second interlayer insulating layer on one side of the first isolation structure through a gate line gap penetrating through the insulation laminated structure by adopting an etching process to form a cavity; and
and filling a grid conductor material into the cavity through the grid line gap.
4. The method according to claim 1, wherein the material of the first interlayer insulating layer is selected from one of an oxide and a nitride, and the material of the second interlayer insulating layer is selected from the other of an oxide and a nitride.
5. The method of claim 1, wherein the material of the first isolation structure comprises silicon carbide.
6. A 3D memory device, wherein the 3D memory device is formed using the method of manufacturing a semiconductor device according to any one of claims 1 to 5.
7. The 3D memory device of claim 6, comprising a plurality of channel pillars located above the semiconductor substrate,
wherein the first gate stack structure surrounds a portion of sidewalls of the plurality of channel pillars, and the second gate stack structure surrounds another portion of sidewalls of the plurality of channel pillars.
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