KR20170054855A

KR20170054855A - Three-dimention semiconductor memory device and Method for fabricating the same

Info

Publication number: KR20170054855A
Application number: KR1020150157520A
Authority: KR
Inventors: 박세준; 윤장근; 황성민; 문안식; 즈리앙 샤
Original assignee: 삼성전자주식회사
Priority date: 2015-11-10
Filing date: 2015-11-10
Publication date: 2017-05-18

Abstract

A three-dimensional semiconductor memory device and a method of forming the same are provided. The three-dimensional semiconductor memory device includes a first gate pattern located on a substrate; A second gate pattern located on an upper surface of the first gate pattern; A first barrier pattern located on a side of the first gate pattern and extending between a top surface of the first gate pattern and a bottom surface of the second gate pattern; A first dielectric pattern positioned on a side of the first barrier pattern; A second barrier pattern located on a side of the second gate pattern and extending between a top surface of the first barrier pattern and a bottom surface of the second gate pattern; And a second dielectric pattern located on a side of the second barrier pattern and extending between a top surface of the first barrier pattern and a bottom surface of the second barrier pattern. The second dielectric pattern extends on the top surface of the first dielectric pattern.

Description

[0001] The present invention relates to a three-dimensional semiconductor memory device and a method of forming the same,

The present invention relates to a three-dimensional semiconductor memory device in which memory cells are three-dimensionally arranged, and a method of forming the same.

A three-dimensional semiconductor memory device in which memory cells are three-dimensionally arranged for high integration is proposed. For example, the three-dimensional semiconductor memory device may include vertical active patterns extending in the vertical direction and gate patterns vertically stacked on the vertical active patterns. Various studies have been conducted to improve the degree of integration of the three-dimensional semiconductor memory device without deteriorating reliability.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a three-dimensional semiconductor memory device capable of reducing the vertical distance between vertically stacked gate patterns without deteriorating reliability and a method of forming the same.

Another object of the present invention is to provide a three-dimensional semiconductor memory device capable of improving the degree of integration without damaging dielectric patterns located between gate patterns and vertical active patterns, and a method of forming the same.

The problems to be solved by the present invention are not limited to the above-mentioned problems. Tasks not mentioned here will be apparent to the ordinarily skilled artisan from the description below.

According to an aspect of the present invention, there is provided a three-dimensional semiconductor memory device including: a vertical active pattern extending in a vertical direction; A first gate pattern located on a side of the vertical active pattern; A first barrier pattern positioned between the first gate pattern and the vertical active pattern and extending on top and bottom surfaces of the first gate pattern; A first dielectric pattern positioned between the first barrier pattern and the vertical active pattern; A second gate pattern located on an upper surface of the first gate pattern and spaced apart from the first barrier pattern; A second barrier pattern positioned between the second gate pattern and the vertical active pattern and extending over the top and bottom surfaces of the second gate pattern; And a second dielectric pattern positioned between the second barrier pattern and the vertical active pattern and extending over the top and bottom surfaces of the second barrier pattern. The lower surface of the second dielectric pattern between the first gate pattern and the second gate pattern directly contacts the upper surface of the first barrier pattern.

The uppermost level of the first dielectric pattern may be the same as the level of the upper surface of the first barrier pattern.

The maximum vertical length of the first dielectric pattern may be equal to the maximum vertical length of the first barrier pattern.

The first dielectric pattern may include a charge storage layer located proximate to the first barrier pattern. The first barrier pattern may have an etch selectivity with the charge storage layer.

The maximum vertical length of the second dielectric pattern may be greater than the maximum vertical length of the first dielectric pattern.

The maximum vertical length of the second barrier pattern may be the same as the vertical length of the first barrier pattern.

The horizontal length of the first dielectric pattern between the first gate pattern and the vertical active pattern may be the same as the horizontal length of the second dielectric pattern between the second gate pattern and the vertical active pattern.

The first dielectric pattern and the second dielectric pattern may have a multi-layer structure. The total number of layers constituting the second dielectric pattern may be equal to the total number of layers constituting the first dielectric pattern.

According to another aspect of the present invention, there is provided a three-dimensional semiconductor memory device including first and second gate patterns alternately stacked on a substrate; A vertical active structure vertically penetrating the first gate patterns and the second gate patterns; First dielectric patterns located between the vertical active structure and the first gate patterns; First barrier patterns located between the first dielectric patterns and the vertical active structure and extending between adjacent first gate patterns and second gate patterns; Second dielectric patterns located between the vertical active structure and the second gate patterns and extending between the adjacent first barrier pattern and the second gate pattern; And second barrier patterns located between the second dielectric patterns and the second gate patterns. And the upper surface of each of the first dielectric patterns is coplanar with the upper surface of the first barrier pattern. And the lower surface of each of the first dielectric patterns is a surface of the lower surface of the first barrier pattern.

Wherein the three-dimensional semiconductor memory device includes first metal dielectric films positioned between the first gate patterns and the first barrier patterns; And second metal dielectric layers positioned between the second gate patterns and the second barrier patterns.

A three-dimensional semiconductor memory device and a method of forming the same according to the technical idea of the present invention include a vertical active pattern and a vertical active pattern, The vertical distance can be reduced. Therefore, in the three-dimensional semiconductor memory device and the forming method thereof according to the technical idea of the present invention, the degree of integration can be improved without lowering the reliability.

1 is a circuit diagram of a three-dimensional semiconductor memory device according to an embodiment of the present invention.
2A is a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the present invention.
FIG. 2B is an enlarged view of the P region of FIG. 2A.
FIGS. 3 to 7 and 8A to 12A are views sequentially illustrating a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention.
Figs. 8B to 12B are enlarged views of the P region of Figs. 8A to 12A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

In the drawings, the same reference numerals denote the same components throughout the specification. In the drawings, the lengths and the thicknesses of layers or regions may be exaggerated for convenience. In addition, when the first component is described as being on the second component, it is preferable that the first component is located on the upper side in direct contact with the second component, And the third component is located between the second components.

Here, the terms first, second, etc. are used for describing various components and are used for the purpose of distinguishing one component from another component. However, the first component and the second component may be arbitrarily named according to the convenience of the person skilled in the art without departing from the technical idea of the present invention.

It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. For example, an element represented in singular form includes a plurality of elements unless the context clearly dictates a singular number. Also, in the specification of the present invention, the terms such as " comprises "or" having ", and the like, designate the presence of stated features, integers, steps, operations, elements, But do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

In addition, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning in the context of the related art and, unless expressly defined in the specification of the present invention, are intended to mean either an ideal or an overly formal meaning It is not interpreted.

(Example)

1 is a circuit diagram of a three-dimensional semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a three-dimensional semiconductor memory device according to an embodiment of the present invention may include cell strings (CTSR) located between common source lines CSL and bit lines BL.

The common source lines CSL may be connected to each other. The bit lines BL may be two-dimensionally arranged. For example, each of the cell strings CSTR may be located between one of the bit lines BL and a common source line CSL connected to each other. The cell strings CSTR may be connected in parallel.

Each cell string CSTR includes a ground selection transistor GST located close to the common source line CSL, a string selection transistor SST located close to the bit line BL, And the memory cell transistors MCT located between the memory cell transistors MC and the string selection transistor SST. The ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The ground selection transistor GST can be controlled by a signal transmitted by the ground selection line GSL. For example, the gate pattern of the ground selection transistor GST may be connected to the ground selection line GSL.

The string selection transistor (SST) may be controlled by a signal transmitted by a string selection line (SSL). For example, the gate pattern of the string selection transistor SST may be connected to the string selection line SSL.

The memory cell transistors MCT may be controlled by a signal transferred by word lines WL1-WL3. For example, each memory cell transistor MCT may include a gate pattern coupled to one of the word lines WL1-WL3.

2A is a cross-sectional view of a three-dimensional semiconductor memory device according to an embodiment of the present invention. FIG. 2B is an enlarged view of the P region of FIG. 2A

Referring to FIGS. 1, 2A and 2B, a three-dimensional semiconductor memory device according to an embodiment of the present invention includes a ground selection transistor GST, memory cell transistors MCT, and a string selection transistor SST, As shown in FIG.

The substrate 100 may include a semiconductor substrate. For example, the substrate 100 may include a single crystal silicon substrate or a silicon on insulator (SOI) substrate.

The ground selection transistor GST may be located near the substrate 100. A buffer insulating layer 110 may be disposed between the substrate 100 and the ground selection transistor GST. The buffer insulating layer 110 may include an insulating material. For example, the buffer insulating layer 110 may include oxidized silicon.

The three-dimensional semiconductor memory device according to the embodiment of the present invention includes a first ground selection transistor GST1 and a second ground selection transistor GST2 in which the ground selection transistor GST is stacked on the substrate 100 . However, the three-dimensional semiconductor memory device according to another embodiment of the present invention may include a single ground selection transistor (GST).

The memory cell transistors MCT may be located on the ground selection transistor GST. The memory cell transistors MCT may include first memory cell transistors MCT1 and second memory cell transistors MCT2 which are alternately stacked.

Each first memory cell transistor MCT1 may include a first gate pattern 211, a first barrier pattern 221, and a first dielectric pattern 231.

The first gate pattern 211 may include a conductive material. For example, the first gate pattern 211 may include a metal such as tungsten (W).

The first barrier pattern 221 may be located on one side of the first gate pattern 211. The first barrier pattern 221 may extend on the upper and lower surfaces of the first gate pattern 211. The first barrier pattern 221 may include an insulating material. For example, the first barrier pattern 221 may include silicon oxide.

The first dielectric pattern 231 may be located on one side of the first barrier pattern 221. The uppermost level of the first dielectric pattern 231 may be the same as the level of the upper surface of the first barrier pattern 221. The maximum vertical length of the first dielectric pattern 231 may be equal to the maximum vertical length of the first barrier pattern 221. The lowest level of the first dielectric pattern 231 may be the same as the level of the lower surface of the first barrier pattern 221.

The first dielectric pattern 231 may have a multi-layer structure. For example, the first dielectric pattern 231 may include a first tunnel insulating layer 231a and a first charge storage layer 231b. The first charge storage film 231b may be positioned between the first barrier pattern 221 and the first tunnel insulating film 231a. For example, the first charge storage layer 231b may be in direct contact with one side of the first barrier pattern 221.

The first tunnel insulating film 231a and the first charge storage film 231b may include an insulating material. The first charge storage film 231b may have an etch selectivity with the first barrier pattern 221. [ For example, the first tunnel insulating layer 231a may include silicon oxide or silicon oxynitride (SiON), and the first charge storage layer 231b may include silicon nitride.

In the three-dimensional semiconductor memory device according to the embodiment of the present invention, each first memory cell transistor MCT1 may further include a first metal dielectric layer 241. [ The first metal dielectric layer 241 may be located between the first gate pattern 211 and the first barrier pattern 221. The first metal dielectric layer 241 may include a high dielectric constant material. For example, the first metal dielectric layer 241 may include aluminum oxide or hafnium oxide.

Each second memory cell transistor MCT2 may include a second gate pattern 212, a second barrier pattern 222, and a second dielectric pattern 232.

The second gate pattern 212 may vertically overlap the first gate pattern 211. For example, the first gate patterns 211 and the second gate patterns 212 may be alternately stacked on the substrate 100. The second gate pattern 212 may have the same shape as the first gate pattern 211. For example, the vertical length of the second gate pattern 212 may be the same as the vertical length of the first gate pattern 211.

The second gate pattern 212 may include a conductive material. The second gate pattern 212 may include the same material as the first gate pattern 211. For example, the second gate pattern 212 may include a metal such as tungsten (W).

The second barrier pattern 222 may be located on one side of the second gate pattern 212. The second barrier pattern 222 may extend on the top and bottom surfaces of the second gate pattern 212. The maximum vertical length of the second barrier pattern 222 may be equal to the maximum vertical length of the first barrier pattern 212.

The second barrier pattern 222 may include an insulating material. The second barrier pattern 222 may include the same material as the first barrier pattern 212. For example, the second barrier pattern 222 may comprise silicon oxide.

The second dielectric pattern 232 may be located on one side of the second barrier pattern 222. The second dielectric pattern 232 may extend on the upper and lower surfaces of the second barrier pattern 222. The maximum vertical length of the second dielectric pattern 232 may be greater than the maximum vertical length of the first dielectric pattern 231.

The second dielectric pattern 232 may be in direct contact with the upper or lower surface of the first barrier pattern 211 between the adjacent first gate pattern 211 and the second gate pattern 212. The second dielectric pattern 232 may be in direct contact with the upper surface or the lower surface of the first dielectric pattern 231 between the adjacent first gate pattern 211 and the second gate pattern 212.

The second dielectric pattern 232 may have a multi-layer structure. The total number of layers constituting the second dielectric pattern 232 may be equal to the total number of layers constituting the first dielectric pattern 231. For example, the second dielectric pattern 232 may include a second tunnel insulating layer 232a and a second charge storage layer 232b. The horizontal length of the second dielectric pattern 232 on one side of the second barrier pattern 222 is equal to the horizontal length of the first dielectric pattern 231 on one side of the first barrier pattern 221 .

The second charge storage layer 232b may be positioned between the second barrier pattern 222 and the second tunnel insulating layer 232a. For example, the second charge storage layer 232b may be in direct contact with the upper surface, the lower surface, and the one side surface of the second barrier pattern 222.

The second tunnel insulating film 232a and the second charge storage film 232b may include an insulating material. The second tunnel insulating layer 232a and the second charge storage layer 232b may include the same material as the first tunnel insulating layer 231a and the first charge storage layer 231b, respectively. For example, the second tunnel insulating layer 232a may include silicon oxide or silicon oxynitride (SiON), and the second charge storage layer 232b may include silicon nitride.

In the three-dimensional semiconductor memory device according to the embodiment of the present invention, only the first barrier pattern, the second barrier pattern, and the second dielectric pattern may be positioned between adjacent first gate patterns and second gate patterns. That is, in the three-dimensional semiconductor memory device according to the embodiment of the present invention, the first dielectric pattern is not extended between the adjacent first gate pattern and the second gate pattern. Accordingly, in the three-dimensional semiconductor memory device according to the embodiment of the present invention, the vertical distance between the adjacent first gate pattern and the second gate pattern can be reduced. Therefore, the degree of integration can be improved in the three-dimensional semiconductor memory device according to the embodiment of the present invention.

The three-dimensional semiconductor memory device according to the embodiment of the present invention may further include a second metal dielectric layer 242 in each second memory cell transistor MCT2. The second metal dielectric layer 242 may be positioned between the second gate pattern 212 and the second barrier pattern 222. The second metal dielectric layer 242 may include a high dielectric constant material. The second metal dielectric layer 242 may include the same material as the first metal dielectric layer 241. For example, the second metal dielectric layer 242 may comprise aluminum oxide or hafnium oxide.

The string selection transistor SST may be located on the memory cell transistors MCT. The memory cell transistors MCT may be located between the ground selection transistor GST and the string selection transistor SST.

The three-dimensional semiconductor memory device according to the embodiment of the present invention is described in which the string selection transistor SST includes a first string selection transistor SST1 and a second string selection transistor SST2. However, the three-dimensional semiconductor memory device according to another embodiment of the present invention may include a single string selection transistor (SST).

The first interlayer insulating layer 310 may be located on the string select transistor SST. The first interlayer insulating layer 310 may include an insulating material.

The ground selection transistor GST, the string selection transistor SST and the memory cell transistors MCT may be located on the side of the vertical active structure 400 extending in the vertical direction. For example, the vertical active structure 400 may vertically penetrate the first gate patterns 211 and the second gate patterns 212, which are alternately stacked on the substrate 100.

The vertical active structure 400 may vertically penetrate the first interlayer insulating layer 310. The highest level of the vertical active structure 400 may be the same as the level of the upper surface of the first interlayer insulating film 310. The vertical active structure 400 may be in direct contact with the substrate 100. For example, the lowest level of the vertical active structure 400 may be lower than the level of the upper surface of the substrate 100.

The vertical active structure 400 may include a vertical active pattern 410, an active buried insulating layer 420, and a bit line pad 430.

The vertical activation pattern 410 may be located close to the ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT. For example, the vertical activation pattern 410 may extend along the sides of the ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT. The first dielectric patterns 231 may be positioned between the first barrier patterns 221 and the vertical active pattern 410. A portion of the second dielectric patterns 232 may be located between the second barrier patterns 222 and the vertical active pattern 410. The first dielectric patterns 231 and the second dielectric patterns 232 may be in direct contact with the vertical active pattern 410. [

The three-dimensional semiconductor memory device according to the embodiment of the present invention may have a top surface and a bottom surface of each of the first gate patterns located between a highest level and a lowest level of the first dielectric pattern. Accordingly, in the three-dimensional semiconductor memory device according to the embodiment of the present invention, the first dielectric patterns located between the first gate patterns and the vertical active pattern in the process of forming the first dielectric patterns may not be damaged. Therefore, the reliability of the three-dimensional semiconductor memory device according to the embodiment of the present invention can be prevented from deteriorating.

The vertical active pattern 410 may comprise a semiconductor material. For example, the vertical active pattern 410 may comprise polycrystalline silicon.

The active buried insulating layer 420 may be located between the vertical active patterns 410. The space between the vertical active patterns 410 may be completely filled with the active buried insulating layer 420. The active buried insulating film 420 may include an insulating material.

The bit line pad 430 may be positioned on the upper surface of the active buried insulating layer 420. For example, the upper surface of the bit line pad 430 may be coplanar with the upper surface of the first interlayer insulating film 310. The lower surface of the bit line pad 430 may be higher than the lower surface of the first interlayer insulating layer 310.

The bit line pad 430 may include a conductive material. For example, the bit line pad 430 may include polycrystalline silicon doped with an impurity.

A second interlayer insulating layer 320 may be disposed on the first interlayer insulating layer 310 and the vertical active structure 400. The second interlayer insulating layer 320 may include an insulating material. For example, the second interlayer insulating layer 320 may include the same material as the first interlayer insulating layer 310.

The common source line CSL spaced apart from the vertical active structure 400 may vertically penetrate the first interlayer insulating layer 310 and the second interlayer insulating layer 320. The common source line CSL may be connected to the substrate 100. For example, the lowest level of the common source line CSL may be lower than the level of the upper surface of the substrate 100. For example, the lowest level of the common source line (CSL) may be lower than the lowest level of the vertical active structure (400).

The common source line CSL may include a common source region 510, a separation insulating film 520, and a common source plug 530.

The common source region 510 may be located within the substrate 100. The common source region 510 may include impurities. For example, the common source region 510 may be a region doped with impurities in the substrate 100.

The isolation insulating film 520 and the common source plug 530 may extend in the vertical direction. For example, the isolation insulating film 520 may surround the side surface of the common source plug 530.

The isolation insulating film 520 may include an insulating material, and the common source plug 530 may include a conductive material. For example, the isolation insulating film 520 may include silicon oxide, and the common source plug 530 may include a metal such as tungsten (W).

A third interlayer insulating layer 330 may be disposed on the second interlayer insulating layer 320 and the common source plug 530. The third interlayer insulating film 330 may include an insulating material. For example, the third interlayer insulating layer 330 may include the same material as the second interlayer insulating layer 320.

The vertical active structure 400 is formed on the third interlayer insulating layer 330 by a bit contact plug 600 vertically penetrating the second interlayer insulating layer 320 and the third interlayer insulating layer 330, And may be connected to the line BL. For example, the bit contact plug 600 may connect the bit line pad 430 of the vertical active structure 400 with the bit line BL.

The bit contact plug 600 may include a conductive material. For example, the bit contact plug 600 may comprise a metal or a metal silicide.

As a result, the three-dimensional semiconductor memory device according to the embodiment of the present invention has the vertical length of the dielectric patterns larger than the gate patterns, but only one of the adjacent dielectric patterns can extend between the adjacent gate patterns. Accordingly, in the three-dimensional semiconductor memory device according to the embodiment of the present invention, the vertical distance between adjacent gate patterns can be reduced without damaging the dielectric patterns located between the gate patterns and the vertical active pattern. Therefore, in the three-dimensional semiconductor memory device according to the embodiment of the present invention, the degree of integration can be improved without lowering the reliability.

FIGS. 3 to 7 and 8A to 12A are views sequentially illustrating a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention. Figs. 8B to 12B are enlarged views of the P region of Figs. 8A to 12A.

A method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention will be described with reference to Figs. 2A, 2B, 3 to 7, 8A to 12A and 8B to 12B. 3, a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes forming a buffer insulating layer 110 on a substrate 100, forming a buffer insulating layer 110 on the substrate 100, A step of forming a structure 800 and a step of forming a first interlayer insulating film 310 on the molding structure 800.

The step of forming the buffer insulating layer 110 may include a thermal oxidation process or a CVD (Chemical Vapor Deposition) process. For example, the buffer insulating layer 110 may include oxidized silicon.

The step of forming the molding structure 800 may include a step of alternately laminating the first sacrificial molding films 810 and the second sacrificial molding films 820 on the buffer insulating film 110. The vertical thickness of the second sacrificial molding films 820 may be different from the vertical thickness of the first sacrificial molding films 810. For example, the second sacrificial molding films 820 may be thicker than the first sacrificial molding films 810.

The second sacrificial molding films 820 may have an etch selectivity with the first sacrificial molding films 810. The first sacrificial molding films 810 and the second sacrificial molding films 820 may have an etch selectivity with the buffer insulating film 110. For example, the first sacrificial molding films 810 may include silicon nitride, and the second sacrificial molding films 820 may include silicon germanium (SiGe).

The first interlayer insulating layer 310 may be formed of an insulating material. The first interlayer insulating film 310 may have an etch selectivity with the first sacrificial molding films 810 and the second sacrificial molding films 820.

4, a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes forming a vertical channel hole 710 on the substrate 100 on which the first interlayer insulating film 310 is formed Process.

The vertical channel hole 710 may vertically penetrate the first interlayer insulating layer 310, the molding structure 800, and the buffer insulating layer 110. The level of the bottom surface of the vertical channel hole 710 may be lower than the level of the upper surface of the substrate 100. For example, the step of forming the vertical channel hole 710 may include a step of recessing the substrate 100.

5, a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes forming a vertical active structure 400 in the vertical channel hole 710, And a step of forming a second interlayer insulating film 320 on the vertical active structure 400.

The process of forming the vertical active structure 400 may include forming a vertical active pattern 410 extending along a sidewall and a bottom surface of the vertical channel hole 710, Forming an active buried insulating film 420 partially filling the channel hole 710 and forming a bit line pad 430 on the upper surface of the active buried insulating film 420. [

The vertical active pattern 410 may be formed of a semiconductor material. For example, the vertical activation pattern 410 may be formed of polycrystalline silicon. The active embedded insulating film 420 may be formed of an insulating material. For example, the active buried insulating film 420 may be formed of silicon oxide. The bit line pad 430 may be formed of a conductive material. For example, the bit line pad 430 may be formed of polycrystalline silicon doped with an impurity.

The second interlayer insulating layer 320 may be formed of an insulating material. The second interlayer insulating film 320 may have an etch selectivity with the first sacrificial molding films 810 and the second sacrificial molding films 820. For example, the second interlayer insulating layer 320 may be formed of the same material as the first interlayer insulating layer 310.

6, a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes a step of forming an isolation trench 720 on the substrate 100 on which the vertical active structure 400 is formed .

The isolation trench 720 may be spaced apart from the vertical active structure 400. The isolation trench 720 may vertically penetrate the second interlayer insulating layer 320, the first interlayer insulating layer 310, the molding structure 800, and the buffer insulating layer 110. The level of the bottom surface of the isolation trench 720 may be lower than the level of the top surface of the substrate 100. For example, the process of forming the isolation trench 720 may include a process of recessing the substrate 100. For example, the level of the bottom surface of the isolation trench 720 may be lower than the level of the bottom surface of the vertical channel hole 710.

7, a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes forming first preliminary gate spaces 820n on the substrate 100 on which the isolation trench 720 is formed . &Lt; / RTI >

The process of forming the first preliminary gate spaces 820n may include a process of removing the second sacrificial molding films 820 using the isolation trench 720. [ For example, the process of forming the first preliminary gate spaces 820n may include a wet etching process.

The first spare gate spaces 820n may expose the upper and lower surfaces of the first sacrificial molding films 810. [ The sides of the vertical active structure 400 may be partially exposed by the first preliminary gate spaces 820n.

8A and 8B, a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes forming preliminary dielectric patterns 231p, first barrier patterns 231p, The first dummy patterns 221 and the first dummy patterns 910 may be formed.

The process of forming the preliminary dielectric patterns 231p may include an atomic layer deposition (ALD) process. The preliminary dielectric patterns 231p may extend along the surface of the first sacrificial molding films 810 exposed by the first preliminary gate spaces 820n and the surface of the vertical active structure 400 have. For example, the preliminary dielectric patterns 231p may directly contact the upper and lower surfaces of the first sacrificial molding films 810. [ The preliminary dielectric patterns 231p may directly contact the vertical activation pattern 410 exposed by the first preliminary gate spaces 820n.

Each of the preliminary dielectric patterns 231p may have a multi-layer structure. For example, the preliminary dielectric patterns 231p may include a preliminary tunnel insulating film 231ap and a preliminary charge storage film 231bp. The preliminary charge storage film 231bp may be formed on the preliminary tunnel insulating film 231ap. The preliminary tunnel insulating film 231ap may be formed between the first sacrificial molding films 810 and the vertical active structure 400 and the preliminary charge storage film 231bp.

The preliminary tunnel insulating film 231ap and the preliminary charge storage film 231bp may be formed of an insulating material. The preliminary charge storage film 231bp may be formed of a material different from the preliminary tunnel insulating film 231ap. For example, the preliminary tunnel insulating film 231ap may be formed of silicon oxide or silicon oxynitride (SiON), and the preliminary charge storage film 231bp may be formed of silicon nitride.

The first barrier patterns 221 may be formed on the preliminary dielectric patterns 231p. The first barrier patterns 221 may extend along the preliminary dielectric patterns 231p. The first barrier patterns 221 may directly contact the corresponding preliminary dielectric pattern 231p. For example, each first barrier pattern 221 may directly contact the preliminary charge storage film 231bp of the preliminary dielectric pattern 231p.

The first barrier patterns 221 may have an etch selectivity with a direct contact layer of the layers constituting the preliminary dielectric patterns 231p. For example, the first barrier patterns 221 may have an etch selectivity with the preliminary charge storage layers 231bp. For example, the first barrier patterns 221 may be formed of silicon nitride.

The first dummy patterns 910 may be formed on the first barrier patterns 221. Each first spare gate space 820n may be completely filled with the corresponding preliminary dielectric pattern 231p, the first barrier pattern 221 and the corresponding first dummy pattern 910. [

The first dummy patterns 910 may have an etch selectivity with the first dielectric patterns 231 p and the first barrier patterns 221. The first dummy patterns 910 may have an etch selectivity with the first sacrificial molding film 810, the first interlayer insulating film 310, and the second interlayer insulating film 320. For example, the first dummy patterns 910 may be formed of polycrystalline silicon.

9A and 9B, a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes forming a second preliminary gate space (not shown) on the substrate 100 on which the first dummy patterns 910 are formed, (810n). &Lt; / RTI >

The process of forming the second preliminary gate spaces 810n may include a step of removing the first sacrificial molding films 810 using the isolation trench 720. [ For example, the process of forming the second preliminary gate spaces 810n may include a wet etching process.

The process of forming the second preliminary gate spaces 810n may further include forming the first dielectric patterns 231 using the preliminary dielectric patterns 231p. The step of forming the first dielectric patterns 231 may include a step of removing the preliminary dielectric patterns 231p located on the upper and lower surfaces of the first barrier patterns 221 . For example, the first dielectric patterns 231 may be formed between the first barrier patterns 221 and the vertical active pattern 410. Each of the first dielectric patterns 231 may include a first tunnel insulating layer 231a and a first charge storage layer 231b.

The highest level of each of the first dielectric patterns 231 may be the same as the level of the upper surface of the first barrier pattern 221. For example, the upper surface of the first dielectric patterns 231 may be coplanar with the upper surface of the first barrier pattern 221. The lowest level of each of the first dielectric patterns 231 may be the same as the level of the lower surface of the first barrier pattern 221. For example, the lower surface of the first dielectric patterns 231 may be coplanar with the lower surface of the first barrier pattern 221.

The method of forming the three-dimensional semiconductor memory device according to the embodiment of the present invention may be such that the first dielectric patterns 231 have the same vertical length as the first barrier patterns 221. Accordingly, in the method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention, the first dielectric patterns 231 located between the first dummy patterns 910 and the vertical active patterns 410 due to over- Damage can be prevented.

The sides of the vertical active structure 400 may be partially exposed by the second preliminary gate spaces 810n. The second preliminary gate spaces 810n may expose upper and lower surfaces of the first barrier patterns 221. [

The vertical length of each of the second spare gate spaces 810n may be equal to the vertical length of each of the first spare gate spaces 820n. For example, the second sacrificial molding films 820 are formed on the upper surface of the first dummy patterns 910 with respect to the vertical thickness of the preliminary dielectric patterns 231p, Lt; / RTI >

In the method of forming a three-dimensional semiconductor memory device according to the embodiment of the present invention, the process of removing the first sacrificial molding film 810 and the process of forming the first dielectric patterns 231 are independently performed. However, in the method of forming a three-dimensional semiconductor memory device according to another embodiment of the present invention, the step of removing the first sacrificial molding film 810 and the step of forming the first dielectric patterns 231 are simultaneously performed . For example, in the method of forming a three-dimensional semiconductor memory device according to another embodiment of the present invention, the preliminary dielectric patterns 231p may be removed by a wet etching process at a material that can be removed simultaneously with the first sacrificial molding film 810 As shown in FIG.

As shown in FIGS. 10A and 10B, a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes forming second dielectric patterns 232 in the second preliminary gate spaces 810n, The first dummy patterns 222 and the second dummy patterns 920 may be formed.

The second dielectric patterns 232 may extend along the surface of the first barrier patterns 221 exposed by the second preliminary gate spaces 810n and the surface of the vertical active structure 400 have. For example, the second dielectric patterns 232 may be in direct contact with the upper and lower surfaces of the first barrier patterns 221. The upper and lower surfaces of the first dielectric patterns 231 may be in direct contact with the second dielectric patterns 232. The second dielectric patterns 232 may be in direct contact with the vertical activation pattern 410 exposed by the second preliminary gate spaces 810n.

Each of the second dielectric patterns 232 may have a multi-layer structure. The second dielectric patterns 232 may be formed in the same manner as the preliminary dielectric patterns 231p. For example, the second dielectric patterns 232 may include a second tunnel insulating layer 232a and a second charge storage layer 232b. The second charge storage layer 232b may be formed on the second tunnel insulating layer 232a. The second tunnel insulating layer 232a is formed between the first barrier patterns 221 and the first dielectric patterns 231 and between the vertical active structure 400 and the second charge storage layer 232b .

The second tunnel insulating layer 232a and the second charge storage layer 232b may be formed of an insulating material. The second tunnel insulating layer 232a and the second charge storage layer 232b may be formed of the same material as the first tunnel insulating layer 231a and the first charge storage layer 231b. For example, the second tunnel insulating layer 232a may be formed of silicon oxide or silicon oxynitride (SiON), and the second charge storage layer 232b may be formed of silicon nitride.

The second barrier patterns 222 may be formed on the second dielectric patterns 232. The second barrier patterns 222 may extend along the second dielectric patterns 232. The second dielectric patterns 232 may extend between the first barrier pattern 221 and the second barrier pattern 222 adjacent to each other on the upper and lower surfaces of the first dummy patterns 910.

The maximum vertical length of each of the second barrier patterns 222 may be equal to the maximum vertical length of each of the first barrier patterns 221. The maximum vertical length of each of the second barrier patterns 222 may be smaller than the maximum vertical length of each of the second dielectric patterns 232. The maximum vertical length of each of the second dielectric patterns 232 may be greater than the maximum vertical length of each of the first dielectric patterns 231.

The second barrier patterns 222 may be formed of the same material as the first barrier patterns 221. For example, the second barrier patterns 222 may be formed of silicon nitride.

The second dummy patterns 920 may be formed on the second barrier patterns 222. Each second spare gate space 810n may be completely filled by the corresponding second dielectric pattern 232, the corresponding second barrier pattern 222 and the corresponding second dummy pattern 920. [ For example, the maximum vertical length of each of the second dummy patterns 920 may be equal to the maximum vertical length of each of the first dummy patterns 910.

The second dummy patterns 920 may have an etch selectivity with the second dielectric patterns 232 and the second barrier patterns 222. The second dummy patterns 920 may have an etch selectivity with the first dielectric patterns 231 and the first barrier patterns 221. The second dummy patterns 920 may have an etch selectivity with the first interlayer insulating layer 310 and the second interlayer insulating layer 320. The second dummy patterns 920 may be formed of the same material as the first dummy patterns 910. For example, the second dummy patterns 920 may be formed of polycrystalline silicon.

11A and 11B, a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes a step of removing the first dummy patterns 910 and the second dummy patterns 920 .

The process of removing the first dummy patterns 910 and the second dummy patterns 920 may include a wet etching process.

12A and 12B, a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes forming a first dummy pattern 910 and a second dummy pattern 920, (GST), memory cell transistors (MCT), and string selection transistor (SST) on the memory cell array (100).

The ground selection transistor GST may include a first ground selection transistor GST1 and a second ground selection transistor GST2 stacked on the substrate 100 in a vertical direction. The memory cell transistors MCT may include first memory cell transistors MCT1 and second memory cell transistors MCT2 which are alternately stacked on the ground selection transistor GST. The string selection transistor SST may include a first string selection transistor SST1 and a second string selection transistor SST2 stacked in the vertical direction on the memory cell transistors MCT.

The process of forming the ground selection transistor GST, the memory cell transistors MCT and the string selection transistor SST may be performed by forming first gate patterns 910 located in a space in which the first dummy patterns 910 are removed, And forming the second gate patterns 212 located in the space where the second dummy patterns 920 are removed. For example, the first ground selection transistor GST1, the first memory cell transistors MCT1, and the first string selection transistor SST1 may have a first gate pattern 211, a first barrier pattern 221 And a first dielectric pattern 231. For example, the second ground selection transistor GST2, the second memory cell transistors MCT2, and the second string selection transistor SST2 may include a second gate pattern 212, a second barrier pattern 222 And a second dielectric pattern 232. In this case,

The first dielectric patterns 231 may be positioned between the vertical activation pattern 410 and the first gate patterns 211. Each of the first gate patterns 211 may be located between an uppermost end and a lowermost end of the first dielectric pattern 231. The second dielectric patterns 232 may be positioned between the vertical activation pattern 410 and the second gate patterns 212. Each second gate pattern 212 may be positioned between the top and bottom surfaces of the second dielectric pattern 232. The horizontal length of the first dielectric patterns 231 between the first gate patterns 211 and the vertical active pattern 410 is greater than the horizontal length between the second gate patterns 212 and the vertical active pattern 410. [ The length of the second dielectric patterns 232 may be equal to the horizontal length of the second dielectric patterns 232.

The first gate patterns 211 and the second gate patterns 212 may be formed of a conductive material. For example, the first gate patterns 211 and the second gate patterns 212 may be formed of a metal such as tungsten (W).

The method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention may further include forming the first metal dielectric layers 241 and the second metal dielectric layers 242. The first metal dielectric layers 241 may be formed between the first gate patterns 211 and the first barrier patterns 221. The second metal dielectric layers 242 may be formed between the second gate patterns 212 and the second barrier patterns 222.

The first metal dielectric layers 241 and the second metal dielectric layers 242 may be formed of a material having a high dielectric constant. For example, the first metal dielectric layers 241 and the second metal dielectric layers 242 may be formed of aluminum oxide or hafnium oxide.

2A and 2B, a method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention includes forming the ground selection transistor GST, the memory cell transistors MCT, and the string selection transistor SST, Forming a common source line (CSL) on the substrate (100) on which the first interlayer insulating film (320) and the common source line (CSL) are formed; forming a third interlayer insulating film (330) Forming a bit contact plug 600 connected to the vertical active structure 400 on the third interlayer insulating film 330 and forming a bit contact plug 600 connected to the bit contact plug 600 on the third interlayer insulating film 330, And forming a bit line BL.

The common source line CSL may be formed in the isolation trench 720. The process of forming the common source line CSL includes forming a common source region 510 in the substrate 100 exposed by the isolation trench 720 and extending along the sidewalls of the isolation trench 720. [ And forming a common source plug 530 filling the isolation trenches 720. The process for forming the isolation trenches 720 may include forming the isolation trenches 520,

The step of forming the common source region 510 may include a step of doping an impurity. The isolation trench 720 may be formed of an insulating material. The common source plug 530 may be formed of a conductive material.

The third interlayer insulating layer 330 may be formed of an insulating material. For example, the third interlayer insulating layer 330 may be formed of the same material as the second interlayer insulating layer 320.

The step of forming the bit contact plug 600 may include a step of exposing the upper surface of the vertical active structure 400 by etching the third interlayer insulating layer 330 and the second interlayer insulating layer 320 have. The bit contact plug 600 may be formed of a conductive material.

As a result, the method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention can remove one of the dielectric patterns between adjacent gate patterns. Accordingly, in the method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention, the vertical distance between adjacent gate patterns can be reduced. Also, in the method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention, the dielectric patterns may form a vertical length larger than the gate patterns. Accordingly, in the method of forming a three-dimensional semiconductor memory device according to an embodiment of the present invention, even when the upper and lower surfaces of the dielectric patterns are recessed by an overexposure angle, the dielectric patterns positioned between the gate patterns and the vertical active structure It may not be damaged. Therefore, in the method of forming a three-dimensional semiconductor memory device according to the embodiment of the present invention, the degree of integration can be improved without lowering the reliability.

100: substrate MCT: memory cell transistor
211: first gate pattern 212: second gate pattern
221: first barrier pattern 222: second barrier pattern
231: first dielectric pattern 232: second dielectric pattern
400: vertical active structure

Claims

A vertical active pattern extending in a vertical direction;
A first gate pattern located on a side of the vertical active pattern;
A first barrier pattern positioned between the first gate pattern and the vertical active pattern and extending on top and bottom surfaces of the first gate pattern;
A first dielectric pattern positioned between the first barrier pattern and the vertical active pattern;
A second gate pattern located on an upper surface of the first gate pattern and spaced apart from the first barrier pattern;
A second barrier pattern positioned between the second gate pattern and the vertical active pattern and extending over the top and bottom surfaces of the second gate pattern; And
And a second dielectric pattern positioned between the second barrier pattern and the vertical active pattern and extending over the top and bottom surfaces of the second barrier pattern,
Wherein the lower surface of the second dielectric pattern is in direct contact with the upper surface of the first barrier pattern between the first gate pattern and the second gate pattern.

The method according to claim 1,
Wherein the uppermost level of the first dielectric pattern is the same as the level of the upper surface of the first barrier pattern.

3. The method of claim 2,
Wherein the maximum vertical length of the first dielectric pattern is equal to the maximum vertical length of the first barrier pattern.

The method according to claim 1,
Wherein the first dielectric pattern comprises a charge storage film located near the first barrier pattern, wherein the first barrier pattern has an etch selectivity with the charge storage film.

The method according to claim 1,
Wherein a maximum vertical length of the second dielectric pattern is larger than a maximum vertical length of the first dielectric pattern.

6. The method of claim 5,
Wherein the maximum vertical length of the second barrier pattern is equal to the vertical length of the first barrier pattern.

The method according to claim 1,
Wherein a horizontal length of the first dielectric pattern between the first gate pattern and the vertical active pattern is equal to a horizontal length of the second dielectric pattern between the second gate pattern and the vertical active pattern.

8. The method of claim 7,
Wherein the first dielectric pattern and the second dielectric pattern are multilayered structures, and the total number of layers constituting the second dielectric pattern is equal to the total number of layers constituting the first dielectric pattern.

First and second gate patterns alternately stacked on a substrate;
A vertical active structure vertically penetrating the first gate patterns and the second gate patterns;
First dielectric patterns located between the vertical active structure and the first gate patterns;
First barrier patterns located between the first dielectric patterns and the vertical active structure and extending between adjacent first gate patterns and second gate patterns;
Second dielectric patterns located between the vertical active structure and the second gate patterns and extending between the adjacent first barrier pattern and the second gate pattern; And
And second barrier patterns located between the second dielectric patterns and the second gate patterns,
Wherein a top surface of each of the first dielectric patterns is a plane surface with a top surface of the first barrier pattern, and a bottom surface of each of the first dielectric patterns is a surface of the three- .

10. The method of claim 9,
First metal dielectric layers positioned between the first gate patterns and the first barrier patterns; And
And second metal dielectric layers located between the second gate patterns and the second barrier patterns.