SG10202009367XA - Memory device including interface circuit and method of operating the same - Google Patents

Memory device including interface circuit and method of operating the same

Info

Publication number
SG10202009367XA
SG10202009367XA SG10202009367XA SG10202009367XA SG10202009367XA SG 10202009367X A SG10202009367X A SG 10202009367XA SG 10202009367X A SG10202009367X A SG 10202009367XA SG 10202009367X A SG10202009367X A SG 10202009367XA SG 10202009367X A SG10202009367X A SG 10202009367XA
Authority
SG
Singapore
Prior art keywords
operating
same
memory device
device including
interface circuit
Prior art date
Application number
SG10202009367XA
Inventor
Na Daehoon
Ihm Jeongdon
Lee Jangwoo
Jeong Byunghoon
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10202009367XA publication Critical patent/SG10202009367XA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
SG10202009367XA 2019-10-07 2020-09-23 Memory device including interface circuit and method of operating the same SG10202009367XA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190123961A KR20210041357A (en) 2019-10-07 2019-10-07 Memory device including interface circuit and operating method thereof

Publications (1)

Publication Number Publication Date
SG10202009367XA true SG10202009367XA (en) 2021-05-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
SG10202009367XA SG10202009367XA (en) 2019-10-07 2020-09-23 Memory device including interface circuit and method of operating the same

Country Status (5)

Country Link
US (2) US11392324B2 (en)
EP (1) EP3805937B1 (en)
KR (1) KR20210041357A (en)
CN (1) CN112634954A (en)
SG (1) SG10202009367XA (en)

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US11404097B2 (en) 2018-12-11 2022-08-02 SK Hynix Inc. Memory system and operating method of the memory system
JP2021174565A (en) * 2020-04-24 2021-11-01 キオクシア株式会社 Semiconductor storage device
US11636055B2 (en) 2021-07-14 2023-04-25 Silicon Motion, Inc. Method and apparatus for performing access management of memory device in predetermined communications architecture with aid of flexible delay time control
US11594265B1 (en) * 2021-09-03 2023-02-28 Micron Technology, Inc. Apparatus including parallel pipeline control and methods of manufacturing the same

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KR100570632B1 (en) 2004-07-06 2006-04-12 삼성전자주식회사 Circuits and Method for Recovering Channel Clock, and High Speed Data Transceiver Circuits
KR100826975B1 (en) * 2006-06-30 2008-05-02 주식회사 하이닉스반도체 A circuit of clock generator and the method of clock Generating
US7975082B2 (en) 2007-07-12 2011-07-05 Oracle America, Inc. System and method to facilitate deterministic testing of data transfers between independent clock domains on a chip
KR101430166B1 (en) 2007-08-06 2014-08-13 삼성전자주식회사 Multi-stacked memory device
US7864084B2 (en) 2008-04-14 2011-01-04 Seiko Epson Corporation Serializer architecture for serial communications
US8447908B2 (en) 2009-09-07 2013-05-21 Bitmicro Networks, Inc. Multilevel memory bus system for solid-state mass storage
JP5347955B2 (en) * 2009-12-28 2013-11-20 日本電気株式会社 Interphase skew detection circuit between multiphase clocks, interphase skew adjustment circuit, and semiconductor integrated circuit
KR102248279B1 (en) * 2014-06-13 2021-05-07 삼성전자주식회사 Storage device including nonvolatile memory and memory controller and operating method of retiming circuit interfacing communication between nonvolatile memory and memory controller
US9570182B1 (en) 2015-09-02 2017-02-14 Kabushiki Kaisha Toshiba Semiconductor memory device and memory system
KR102641515B1 (en) 2016-09-19 2024-02-28 삼성전자주식회사 Memory device and clock distribution method thereof
KR20180034738A (en) 2016-09-26 2018-04-05 삼성전자주식회사 Memory device and divided clock compensation method thereof
KR20180033676A (en) * 2016-09-26 2018-04-04 에스케이하이닉스 주식회사 Memory module and memory system including the same
KR20180092476A (en) 2017-02-09 2018-08-20 에스케이하이닉스 주식회사 Storage device and operating method thereof
KR20180093648A (en) * 2017-02-14 2018-08-22 에스케이하이닉스 주식회사 Storage device and operating method thereof
US10164817B2 (en) * 2017-03-21 2018-12-25 Micron Technology, Inc. Methods and apparatuses for signal translation in a buffered memory
KR102340446B1 (en) 2017-09-08 2021-12-21 삼성전자주식회사 Storage device and data training method thereof
KR20200124045A (en) * 2019-04-23 2020-11-02 에스케이하이닉스 주식회사 Memory system and operating method thereof

Also Published As

Publication number Publication date
US11392324B2 (en) 2022-07-19
US20220350541A1 (en) 2022-11-03
CN112634954A (en) 2021-04-09
US20210103407A1 (en) 2021-04-08
EP3805937B1 (en) 2022-07-27
EP3805937A1 (en) 2021-04-14
KR20210041357A (en) 2021-04-15

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