SG10202004110TA - Nonvolatile memory device, storage device, and operating method of nonvolatile memory device - Google Patents

Nonvolatile memory device, storage device, and operating method of nonvolatile memory device

Info

Publication number
SG10202004110TA
SG10202004110TA SG10202004110TA SG10202004110TA SG10202004110TA SG 10202004110T A SG10202004110T A SG 10202004110TA SG 10202004110T A SG10202004110T A SG 10202004110TA SG 10202004110T A SG10202004110T A SG 10202004110TA SG 10202004110T A SG10202004110T A SG 10202004110TA
Authority
SG
Singapore
Prior art keywords
nonvolatile memory
memory device
operating method
storage device
storage
Prior art date
Application number
SG10202004110TA
Inventor
Choi Yonghyuk
Yu Jae-Duk
Lee Kang-Bin
Shim Sang-Won
Lim Bongsoon
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10202004110TA publication Critical patent/SG10202004110TA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Engineering & Computer Science (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
SG10202004110TA 2019-08-26 2020-05-05 Nonvolatile memory device, storage device, and operating method of nonvolatile memory device SG10202004110TA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020190104615A KR20210025162A (en) 2019-08-26 2019-08-26 Nonvolatile memory device, storage device, and operating method of nonvolatile memory device

Publications (1)

Publication Number Publication Date
SG10202004110TA true SG10202004110TA (en) 2021-03-30

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
SG10202004110TA SG10202004110TA (en) 2019-08-26 2020-05-05 Nonvolatile memory device, storage device, and operating method of nonvolatile memory device

Country Status (4)

Country Link
US (1) US11043274B2 (en)
KR (1) KR20210025162A (en)
CN (1) CN112435701A (en)
SG (1) SG10202004110TA (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10714166B2 (en) * 2018-08-13 2020-07-14 Micron Technology, Inc. Apparatus and methods for decoding memory access addresses for access operations
US11069415B2 (en) * 2018-10-05 2021-07-20 Samsung Electronics Co., Ltd. Memory device including charge pump circuit
US11158379B2 (en) * 2019-08-26 2021-10-26 Samsung Electronics Co., Ltd. Nonvolatile memory device, storage device, and operating method of nonvolatile memory device
US11985825B2 (en) 2020-06-25 2024-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. 3D memory array contact structures
US11532343B2 (en) * 2020-06-26 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Memory array including dummy regions
US11716856B2 (en) 2021-03-05 2023-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Three-dimensional memory device and method

Family Cites Families (16)

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Publication number Priority date Publication date Assignee Title
JP5376789B2 (en) 2007-10-03 2013-12-25 株式会社東芝 Nonvolatile semiconductor memory device and control method of nonvolatile semiconductor memory device
KR101226685B1 (en) 2007-11-08 2013-01-25 삼성전자주식회사 Vertical type semiconductor device and Method of manufacturing the same
KR101691092B1 (en) 2010-08-26 2016-12-30 삼성전자주식회사 Nonvolatile memory device, operating method thereof and memory system including the same
US8553466B2 (en) 2010-03-04 2013-10-08 Samsung Electronics Co., Ltd. Non-volatile memory device, erasing method thereof, and memory system including the same
US9536970B2 (en) 2010-03-26 2017-01-03 Samsung Electronics Co., Ltd. Three-dimensional semiconductor memory devices and methods of fabricating the same
KR101682666B1 (en) 2010-08-11 2016-12-07 삼성전자주식회사 Nonvolatile memory devicwe, channel boosting method thereof, programming method thereof, and memory system having the same
KR20120133232A (en) 2011-05-31 2012-12-10 에스케이하이닉스 주식회사 Flash memory device
KR101891164B1 (en) 2012-04-17 2018-08-23 삼성전자주식회사 Flash memory device including program scheduler
US9524773B2 (en) * 2013-09-14 2016-12-20 Peter Wung Lee Multi-task concurrent/pipeline NAND operations on all planes
JP2015176620A (en) 2014-03-14 2015-10-05 株式会社東芝 semiconductor memory device
KR102179270B1 (en) * 2014-07-23 2020-11-18 삼성전자주식회사 Nonvolatile memory device and operating method thereof
US9449987B1 (en) 2015-08-21 2016-09-20 Sandisk Technologies Llc Three dimensional memory device with epitaxial semiconductor pedestal for peripheral transistors
KR102435524B1 (en) * 2015-10-21 2022-08-23 삼성전자주식회사 Semiconductor memory device
KR102289598B1 (en) 2017-06-26 2021-08-18 삼성전자주식회사 Non-volatile memory device and memory system including the same and program method thereof
KR102462503B1 (en) * 2017-11-27 2022-11-02 삼성전자주식회사 Nonvolatile memory device having vertical structure and memory system including the same
KR102261816B1 (en) 2017-12-05 2021-06-07 삼성전자주식회사 Non-volatile memory device improving data reliability and Operating method thereof

Also Published As

Publication number Publication date
US20210065805A1 (en) 2021-03-04
KR20210025162A (en) 2021-03-09
US11043274B2 (en) 2021-06-22
CN112435701A (en) 2021-03-02

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