CN103873031A - Non-clock trigger register - Google Patents
Non-clock trigger register Download PDFInfo
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- CN103873031A CN103873031A CN201410080642.7A CN201410080642A CN103873031A CN 103873031 A CN103873031 A CN 103873031A CN 201410080642 A CN201410080642 A CN 201410080642A CN 103873031 A CN103873031 A CN 103873031A
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Abstract
The invention discloses a non-clock trigger register which comprises a latch and a trigger circuit, wherein the latch comprises an input end, an output end and a control end; when the control end is in a first logic level, a data signal of the input end is transmitted to the output end; when the control end is in a second logic level, a data signal which is output by the output end of the latch keeps unchanged; the trigger circuit comprises a request input end used for receiving a request signal, a response input end used for receiving a response signal and an output end which is connected with the control end of the latch; when the request signal is effective and the response signal is invalid, the trigger circuit outputs the first logic level; when the request signal is invalid and the response signal is effective, the trigger circuit outputs the second logic level. According to the non-clock trigger register, a group of handshaking signals are used for replacing a clock signal, the non-clock trigger register based on the handshaking signals is designed on the basis, and a series of defects of a sequential circuit are eliminated.
Description
[technical field]
The present invention relates to electronic applications, particularly a kind of non-clock trigger register.
[background technology]
Design of Digital Circuit is the constructed sequence circuit of register (being D Flip-Flop) triggering based on clock the most widely at present, and its conventional occupation mode as shown in Figure 1, is made up of a series of registers by clock control and combinational logic.Clock trigger register logic is fairly simple directly, also be combined better with industrial quarters standard, even if but register value does not change, due to the upset of clock, still can cause power consumption, simultaneously, the operating rate of the sequence circuit building with clock trigger register is determined by clock completely, when the operating rate of logical circuit is far above clock speed, be equivalent to reduce the speed of processing of circuit signal, if the operating rate of logical circuit is slower than clock speed, cause sequential mistake (timing violation).
Be necessary to propose a kind of improved technical scheme and overcome the problems referred to above.
[summary of the invention]
The object of the present invention is to provide a kind of non-clock trigger register, it has abandoned clock signal completely, it uses one group of handshake to replace clock signal, and has designed on this basis the non-clock trigger register based on handshake, to eliminate a series of shortcomings of sequence circuit.
To achieve these goals, the invention discloses a kind of non-clock trigger register, it comprises: latch, it includes input, output and control end, in the time that control end is the first logic level, the data-signal of described input is transferred to described output, and in the time that described control end is the second logic level, the data-signal of the output output of described latch remains unchanged, circuits for triggering, it comprises the request input that receives request signal, receive the response input and the output being connected with the control end of described latch of response signal, be that effective and described response signal is while being invalid at described request signal, described circuits for triggering are exported the first logic level, be that invalid and described response signal is while being effective at described request signal, described circuits for triggering are exported the second logic level, wherein become after effective a period of time at described request signal, described response signal becomes effectively, become after invalid a period of time at described request signal, it is invalid that described response signal becomes.
Further, described request signal become invalid after, described response signal just becomes effectively, described request signal and described response signal are pulse signal.
Further, to be high level effective for described request signal and described response signal; Or described request signal and described response signal are Low level effective, the first logic level is in high level and low level, and the second logic level is another in high level and low level.
Further, in the time that the logic level of described request signal is different with the logic level of described response signal, the output output logic level identical with described request signal of described circuits for triggering, in the time that the logic level of described request signal is identical with the logic level of described response signal, the state of the logic level of the output output of described circuits for triggering is constant, described request signal is pulse signal, and described response signal is the pulse signal based on described request signal formation.
Further, described circuits for triggering comprise logic module and latch module, described latch module comprises the input that receives described request signal, control end and the output being connected with the control end of described latch, described logic module includes the first input end that receives described request signal, receive the second input of described response signal and the output being connected with the control end of described latch module, in the time that the logic level of described request signal is different with the logic level of described response signal, the signal of a logic level of described logic module output is to make the output output of described latch module and the signal of its input identity logic level, in the time that the logic level of described request signal is identical with the logic level of described response signal, the signal that described logic module is exported another logic level is to make the state of logic level of output output of described latch module constant.
Further, described logic module comprises not gate and XOR gate, the input of described not gate receives described response signal as the second input of logic module, the output of described not gate connects an input of described XOR gate, another input of described XOR gate receives described request signal as the first input end of logic module, the output of described XOR gate connects the control end of described latch module as the output of logic module, described latch module is the first MUX, the first input end of the first MUX receives described request signal as the input of latch module, the second input of the first MUX connects its output, the output of the first MUX connects the control end of described latch as the output of described latch module, the selecting side of the first MUX is the control end of described latch module, described latch is the second MUX, the second input of the second MUX receives described request signal, the first input end of the second MUX connects its output, the output of the second MUX is as the output of described latch, the selecting side of the second MUX is the control end of described latch, in the time that the selecting side of the first and second MUX is the first logic level, the first and second MUX can select the data-signal of the second input as the output signal of its output, in the time that the selecting side of the first and second MUX is the second logic level, the first and second MUX can select the data-signal of first input end as the output signal of its output.
Compared with prior art, the present invention has abandoned clock signal completely, it uses one group of handshake (request signal and response signal) to replace clock signal, and has designed on this basis the non-clock trigger register based on handshake, to eliminate a series of shortcomings of sequence circuit.
[accompanying drawing explanation]
Below in conjunction with accompanying drawing and example, the present invention is further described.
Fig. 1 is the sequence circuit of the register based on clock triggering in prior art;
Fig. 2 is non-clock trigger register in the present invention structured flowchart in one embodiment;
Fig. 3 is non-clock trigger register in the present invention at a structured flowchart in embodiment more specifically;
Fig. 4 is the timing waveform schematic diagram of the non-clock trigger register in Fig. 3.
Embodiment
Below in conjunction with accompanying drawing and example, the present invention will be further described.
This time illustrated accompanying drawing is to be used to provide a further understanding of the present invention, forms a part of the present invention, and schematic example of the present invention and explanation thereof are used for explaining the present invention, do not form inappropriate limitation of the present invention.
Fig. 2 is non-clock trigger register 200 in the present invention structured flowchart in one embodiment.As shown in Figure 2, described non-clock trigger register 200 comprises latch 210 and circuits for triggering 220.
Described latch 210 includes input, output and control end.In the time that control end is the first logic level, the data-signal of described input is transferred to described output, and this state also can be called as data input state.In the time that described control end is the second logic level, the data-signal of the output output of described latch remains unchanged, the data-signal of the output of latch output described in when remaining on control end and being the first logic level, this state also can be called as data latch mode.The first logic level is in high level and low level, and the second logic level is another in high level and low level, and such as the first logic level is high level, the second logic level is low level.
Circuits for triggering 220 comprise receive request signal request input, receive the response input and the output being connected with the control end of described latch 210 of response signal.Be effective and described response signal while being invalid at described request signal, described circuits for triggering 220 are exported the first logic level, are invalid and described response signal while being effective at described request signal, and described circuits for triggering 220 are exported the second logic level.Become after effective a period of time at described request signal, described response signal becomes effectively, becomes after invalid a period of time at described request signal, and it is invalid that described response signal becomes.It is effective that described request signal and described response signal are high level; Or described request signal and described response signal are Low level effective.
In a preferred embodiment, described request signal become invalid after, described response signal just becomes effectively, described request signal and described response signal are pulse signal (such as positive pulse signal).Concrete, described request signal is that data sending terminal sends, it represents that data sending terminal has data to need to transmit, described response signal is that data receiver sends, its expression data receiver is got ready, and described request signal and described response signal are equivalent to the handshake of data sending terminal and data receiver.Conventionally, described request signal is a positive pulse signal, and described response signal is a positive pulse signal of delaying.
Sum up, be that effectively (the pulse period is for effective at described request signal, all the other are for invalid) and described response signal while being invalid, described circuits for triggering 200 are exported the first logic level, described latch 210 enters data input state, be invalid and described response signal while being effective at described request signal, described circuits for triggering 220 are exported the second logic level, and described latch 210 enters data latch mode.Like this, it has abandoned clock signal completely, and it uses one group of handshake to replace clock signal, and has designed on this basis the non-clock trigger register based on handshake, it can substitute the register that existing clock triggers completely, thereby can eliminate a series of shortcomings of sequence circuit.
Fig. 3 is non-clock trigger register in the present invention at a structured flowchart in embodiment more specifically, the demonstration that it is detailed the concrete structure of latch 210 and circuits for triggering 220.
Described circuits for triggering 220 can be achieved as follows logic: in the time that the logic level of described request signal is different with the logic level of described response signal, the output output logic level identical with described request signal of described circuits for triggering 220, in the time that the logic level of described request signal is identical with the logic level of described response signal, the state of the logic level of the output output of described circuits for triggering 220 is constant.
As shown in Figure 3, described circuits for triggering 220 comprise logic module 221 and latch module 222.Described latch module 220 comprises the input, control end and the output being connected with the control end of described latch 210 that receive described request signal REQ_IN.Described logic module 221 include receive described request signal first input end, receive the second input of described response signal ACK_IN and the output being connected with the control end of described latch module 222.In the time that the logic level of described request signal is different with the logic level of described response signal, described logic module 221 is exported the signal of a logic level to make the output output of described latch module 222 and the signal of its input (being request signal) identity logic level.In the time that the logic level of described request signal is identical with the logic level of described response signal, the signal of described logic module 221 another logic levels of output is to make the state of logic level of output output of described latch module 222 constant.
Again referring to shown in Fig. 3, described logic module 221 comprises not gate INV and XOR gate XOR, the input of described not gate receives described response signal as the second input of logic module 221, the output of described not gate connects an input of described XOR gate, another input of described XOR gate receives described request signal as the first input end of logic module 221, and the output of described XOR gate connects the control end of described latch module 222 as the output of logic module 221.
Described latch module 222 is the first MUX MUX1, the first input end S0 of the first MUX MUX1 receives described request signal as the input of latch module 222, the second input of the first MUX MUX1 connects its output, the output of the first MUX MUX1 connects the control end of described latch 210 as the output of described latch module 222, the selecting side SEL of the first MUX MUX1 is the control end of described latch module 221.
Described latch 210 is the second MUX MUX2, the second input S1 of the second MUX MUX2 receives described request signal, the first input end S0 of the second MUX MUX2 connects its output OUT, the output of the second MUX MUX2 is as the output of described latch 210, and the selecting side of the second MUX MUX2 is the control end of described latch 210.
There is identical logic in the first MUX with the second MUX, in the time that the selecting side of MUX is the first logic level, MUX can select the data-signal of the second input S1 as the output signal of its output, in the time that the selecting side of MUX is the second logic level, MUX can select the data-signal of first input end S0 as the output signal of its output.
At one, more specifically in embodiment, request signal REQ_IN is positive pulse, and response signal ACK_IN is the positive pulse after request signal postpones, and the first logic level is high level.Fig. 4 is the timing waveform schematic diagram of the non-clock trigger register in Fig. 3, and it has illustrated request signal REQ_IN, response signal ACK_IN, the timing waveform schematic diagram of the output XOR_OUT of logic module 221, the output MUX1_OUT of latch module 22.As shown in Figure 4, in the time of the T1 time period, REQ_IN and ACK_IN are all low level, and XOR_OUT is high, and MUX1_OUT is low, and now latch 210 is data latch mode; In the T2 time period, REQ_IN is high (effectively high), and ACK_IN is low, and XOR_OUT becomes low, and MUX1_OUT becomes height (identical with REQ_IN now), and now latch 210 is data input state; In the T3 time period, REQ_IN and ACK_IN are all low level, and XOR_OUT is high, and MUX1_OUT still continues high, and latch 210 is continuously data input state; In the T4 time period, REQ_IN is low, and ACK_IN is high (effectively high), and XOR_OUT becomes low again, and MUX1_OUT becomes low (identical with REQ_IN now), and now latch 210 is got back to data latch mode.
Above-mentioned explanation has fully disclosed the specific embodiment of the present invention.It is pointed out that and be familiar with the scope that any change that person skilled in art does the specific embodiment of the present invention does not all depart from claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (6)
1. a non-clock trigger register, is characterized in that: it comprises:
Latch, it includes input, output and control end, and in the time that control end is the first logic level, the data-signal of described input is transferred to described output, in the time that described control end is the second logic level, the data-signal of the output output of described latch remains unchanged;
Circuits for triggering, it comprise receive request signal request input, receive the response input and the output being connected with the control end of described latch of response signal, be that effective and described response signal is while being invalid at described request signal, described circuits for triggering are exported the first logic level, be that invalid and described response signal is while being effective at described request signal, described circuits for triggering are exported the second logic level
Wherein become after effective a period of time at described request signal, described response signal becomes effectively, becomes after invalid a period of time at described request signal, and it is invalid that described response signal becomes.
2. non-clock trigger register as claimed in claim 1, is characterized in that: described request signal become invalid after, described response signal just becomes effectively, described request signal and described response signal are pulse signal.
3. non-clock trigger register as claimed in claim 1, is characterized in that: it is effective that described request signal and described response signal are high level; Or described request signal and described response signal are Low level effective, the first logic level is in high level and low level, and the second logic level is another in high level and low level.
4. non-clock trigger register as claimed in claim 1, it is characterized in that: in the time that the logic level of described request signal is different with the logic level of described response signal, the output output logic level identical with described request signal of described circuits for triggering, in the time that the logic level of described request signal is identical with the logic level of described response signal, the state of the logic level of the output output of described circuits for triggering is constant
Described request signal is pulse signal, and described response signal is the pulse signal based on described request signal formation.
5. non-clock trigger register as claimed in claim 4, is characterized in that: described circuits for triggering comprise logic module and latch module,
Described latch module comprises the input, control end and the output being connected with the control end of described latch that receive described request signal, described logic module include receive described request signal first input end, receive the second input of described response signal and the output being connected with the control end of described latch module
In the time that the logic level of described request signal is different with the logic level of described response signal, described logic module is exported the signal of a logic level to make the output output of described latch module and the signal of its input identity logic level,
In the time that the logic level of described request signal is identical with the logic level of described response signal, the signal that described logic module is exported another logic level is to make the state of logic level of output output of described latch module constant.
6. non-clock trigger register as claimed in claim 5, is characterized in that:
Described logic module comprises not gate and XOR gate, the input of described not gate receives described response signal as the second input of logic module, the output of described not gate connects an input of described XOR gate, another input of described XOR gate receives described request signal as the first input end of logic module, the output of described XOR gate connects the control end of described latch module as the output of logic module
Described latch module is the first MUX, the first input end of the first MUX receives described request signal as the input of latch module, the second input of the first MUX connects its output, the output of the first MUX connects the control end of described latch as the output of described latch module, the selecting side of the first MUX is the control end of described latch module
Described latch is the second MUX, the second input of the second MUX receives described request signal, the first input end of the second MUX connects its output, the output of the second MUX is as the output of described latch, the selecting side of the second MUX is the control end of described latch
In the time that the selecting side of the first and second MUX is the first logic level, the first and second MUX can select the data-signal of the second input as the output signal of its output, in the time that the selecting side of the first and second MUX is the second logic level, the first and second MUX can select the data-signal of first input end as the output signal of its output.
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| CN201410080642.7A CN103873031B (en) | 2014-03-06 | 2014-03-06 | Non-clock-activated register |
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| CN201410080642.7A CN103873031B (en) | 2014-03-06 | 2014-03-06 | Non-clock-activated register |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108512533A (en) * | 2017-02-28 | 2018-09-07 | 爱思开海力士有限公司 | Semiconductor devices |
| CN113407467A (en) * | 2021-07-19 | 2021-09-17 | 北京中科芯蕊科技有限公司 | Synchronous and asynchronous conversion interface and device based on Mousetrap |
| WO2023179325A1 (en) * | 2022-03-24 | 2023-09-28 | 华为技术有限公司 | Chip, signal processing method, and electronic device |
| WO2024066522A1 (en) * | 2022-09-26 | 2024-04-04 | 华为技术有限公司 | Circuit structure and processor |
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| US4839604A (en) * | 1987-03-17 | 1989-06-13 | Nec Corporation | Integrated circuit with clock distribution means for supplying clock signals |
| CN1471668A (en) * | 2000-10-23 | 2004-01-28 | ŦԼ�и��ױ��Ǵ�ѧ�йܻ� | Asynchronous pipeline with latch controllers |
| CN101055479A (en) * | 2007-05-29 | 2007-10-17 | 北京中星微电子有限公司 | System and method for realizing data update of non-clock-control register |
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2014
- 2014-03-06 CN CN201410080642.7A patent/CN103873031B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US4839604A (en) * | 1987-03-17 | 1989-06-13 | Nec Corporation | Integrated circuit with clock distribution means for supplying clock signals |
| US4839604B1 (en) * | 1987-03-17 | 1992-12-01 | Nippon Electric Co | |
| CN1471668A (en) * | 2000-10-23 | 2004-01-28 | ŦԼ�и��ױ��Ǵ�ѧ�йܻ� | Asynchronous pipeline with latch controllers |
| CN101055479A (en) * | 2007-05-29 | 2007-10-17 | 北京中星微电子有限公司 | System and method for realizing data update of non-clock-control register |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108512533A (en) * | 2017-02-28 | 2018-09-07 | 爱思开海力士有限公司 | Semiconductor devices |
| CN113407467A (en) * | 2021-07-19 | 2021-09-17 | 北京中科芯蕊科技有限公司 | Synchronous and asynchronous conversion interface and device based on Mousetrap |
| CN113407467B (en) * | 2021-07-19 | 2023-05-30 | 北京中科芯蕊科技有限公司 | Synchronous-asynchronous conversion interface and device based on Mouserap |
| WO2023179325A1 (en) * | 2022-03-24 | 2023-09-28 | 华为技术有限公司 | Chip, signal processing method, and electronic device |
| WO2024066522A1 (en) * | 2022-09-26 | 2024-04-04 | 华为技术有限公司 | Circuit structure and processor |
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| CN103873031B (en) | 2016-06-01 |
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Effective date of registration: 20240523 Address after: Room 1501, Block C, Cygnus, Software Park, No. 111, Linghu Avenue, Xinwu District, Wuxi City, Jiangsu Province, 214000 Patentee after: Wuxi Saimi Kentuo Microelectronics Co.,Ltd. Country or region after: China Address before: 214000 No.8 Xinhui Ring Road, Wuxi New District, Jiangsu Province Patentee before: WUXI ETEK MICROELECTRONICS CO.,LTD. Country or region before: China |