CN110008155B - Electronic device and operation method thereof - Google Patents
Electronic device and operation method thereof Download PDFInfo
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- CN110008155B CN110008155B CN201810006999.9A CN201810006999A CN110008155B CN 110008155 B CN110008155 B CN 110008155B CN 201810006999 A CN201810006999 A CN 201810006999A CN 110008155 B CN110008155 B CN 110008155B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Abstract
An electronic device is provided. The electronic device includes a first integrated circuit and a second integrated circuit. The direction pin of the first integrated circuit outputs a direction control signal to the direction pin of the second integrated circuit. When the direction control signal is in the first logic state, the first integrated circuit obtains the control right. When the first integrated circuit obtains the control right, the frequency pin of the first integrated circuit outputs a first frequency signal to the frequency pin of the second integrated circuit. When the direction control signal is in the second logic state, the second integrated circuit obtains the control right. When the second IC obtains the control right, the frequency pin of the second IC outputs the second frequency signal to the frequency pin of the first IC.
Description
Technical Field
The invention relates to an electronic device and an operation method thereof.
Background
In addition to the data transmission pins, additional control pins are required to transmit specific control signals during the cooperative operation between the two integrated circuits. Generally, the greater the number of pins, the higher the manufacturing cost of the integrated circuit. In addition, during the cooperative operation between two integrated circuits, one of the integrated circuits plays the role of "master" and the other integrated circuit plays the role of "slave". In the prior art, the master and slave are fixed. For example, in a master-slave architecture, integrated circuit a assumes the "master" role (master) and integrated circuit B assumes the "slave" role (slave). The frequency signal required for synchronous operation is provided by IC A, and IC B receives the frequency signal of IC A for cooperation. The integrated circuit B cannot change from slave to master.
Disclosure of Invention
The invention provides an electronic device and an operation method thereof, which are used for dynamically switching control right to one of a first integrated circuit and a second integrated circuit according to operation requirements.
The embodiment of the invention provides an electronic device. The electronic device includes a first integrated circuit and a second integrated circuit. The first integrated circuit at least has a direction pin and a frequency pin, wherein the direction pin of the first integrated circuit outputs a direction control signal. The second integrated circuit at least has a direction pin and a frequency pin. The direction pin of the second integrated circuit is coupled with the direction pin of the first integrated circuit to receive the direction control signal. The frequency pin of the second integrated circuit is coupled with the frequency pin of the first integrated circuit. When the direction control signal is in the first logic state, the first integrated circuit obtains the control right. When the first IC obtains the control right, the frequency pin of the first IC outputs a first frequency signal to the frequency pin of the second IC. When the direction control signal is in the second logic state, the second integrated circuit obtains the control right. When the second IC obtains the control right, the frequency pin of the second IC outputs the second frequency signal to the frequency pin of the first IC.
The embodiment of the invention provides an operation method of an electronic device. The electronic device includes a first integrated circuit and a second integrated circuit. The operation method comprises the following steps: outputting a direction control signal to a direction pin of a second integrated circuit by the direction pin of the first integrated circuit; when the direction control signal is in the first logic state, the first integrated circuit obtains the control right; when the first IC obtains the control right, the frequency pin of the first IC outputs the first frequency signal to the frequency pin of the second IC; when the direction control signal is in a second logic state, the second integrated circuit obtains the control right; and when the second integrated circuit obtains the control right, the frequency pin of the second integrated circuit outputs a second frequency signal to the frequency pin of the first integrated circuit.
Based on the above, the electronic device and the operating method thereof according to the embodiments of the invention can dynamically switch the control right to one of the first integrated circuit and the second integrated circuit through the direction control signal. When the first integrated circuit obtains the control right, the first integrated circuit can output a first frequency signal to the second integrated circuit. When the second integrated circuit obtains the control right, the second integrated circuit can output a second frequency signal to the first integrated circuit.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic block diagram of an electronic device according to an embodiment of the invention.
Fig. 2 is a flowchart illustrating an operation method of an electronic device according to an embodiment of the invention.
FIG. 3 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to an embodiment of the invention.
FIG. 4 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to another embodiment of the present invention.
FIG. 5 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to another embodiment of the present invention.
FIG. 6 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to yet another embodiment of the present invention.
Detailed Description
The term "coupled" as used throughout this specification, including the claims, may refer to any direct or indirect connection means. For example, if a first device couples (or connects) to a second device, it should be construed that the first device may be directly connected to the second device or the first device may be indirectly connected to the second device through some other device or some connection means. Further, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. Components/parts/steps in different embodiments using the same reference numerals or using the same terms may be referred to one another in relation to the description.
Fig. 1 is a schematic block diagram of an electronic device 100 according to an embodiment of the invention. The electronic device 100 includes a first integrated circuit 110 and a second integrated circuit 120. The first integrated circuit 110 at least has a direction pin DR, a clock pin CK, a first data pin D1 and a second data pin D2. The second integrated circuit 120 at least has a direction pin DR, a clock pin CK, a first data pin D1 and a second data pin D2. The first integrated circuit 110 may be configured with other pins and the second integrated circuit 120 may be configured with other pins according to design requirements.
The direction pin DR of the first integrated circuit 110 outputs a direction control signal DIR. The direction pin DR of the second IC 120 is coupled to the direction pin DR of the first IC 110 for receiving the direction control signal DIR. The clock pin CK of the second IC 120 is coupled to the clock pin CK of the first IC 110. The first data pin D1 of the second integrated circuit 120 is coupled to the first data pin D1 of the first integrated circuit 110. The second data pin D2 of the second integrated circuit 120 is coupled to the second data pin D2 of the first integrated circuit 110.
Fig. 2 is a flowchart illustrating an operation method of an electronic device according to an embodiment of the invention. Please refer to fig. 1 and fig. 2. In step S210, the direction pin DR of the first ic 110 outputs the direction control signal DIR to the direction pin DR of the second ic 120. Step S220 determines the logic state of the direction control signal DIR. When the determination result in step S220 indicates that the direction control signal DIR is in the first logic state, step S230 is performed. When the determination result in step S220 indicates that the direction control signal DIR is in the second logic state, step S250 is performed.
The first logic state and the second logic state may be determined according to design requirements. For example, in one embodiment, the first logic state may be a logic state "1" (e.g., a high logic level) and the second logic state may be a logic state "0" (e.g., a low logic level). In another embodiment, the first logic state may be a logic state "0" and the second logic state may be a logic state "1".
The initial state of the direction control signal DIR may be determined according to design requirements. For example, in one embodiment, the initial state of the direction control signal DIR may be a second logic state. In another embodiment, the initial state of the direction control signal DIR may be a first logic state.
When the direction control signal DIR is in the first logic state, the first integrated circuit 110 obtains control in step S230. When the first integrated circuit 110 obtains the control right, the clock pin CK of the first integrated circuit 110 outputs the clock signal SCL to the clock pin CK of the second integrated circuit 120 in step S240. When the direction control signal DIR is in the second logic state, the second integrated circuit 120 obtains control in step S250. When the second ic 120 obtains the control right, the clock pin CK of the second ic 120 outputs the clock signal SCL to the clock pin CK of the first ic 110 in step S260.
Therefore, the present embodiment can dynamically switch the control right to one of the first integrated circuit 110 and the second integrated circuit 120 through the direction control signal DIR. For example, in the master-slave architecture, the first ic 110 taking control can take the role of master, while the second ic 120 takes the role of slave. When the first integrated circuit 110 takes control, the first integrated circuit 110 can output the clock signal SCL to the second integrated circuit 120. After control is dynamically switched from the first integrated circuit 110 to the second integrated circuit 120, the second integrated circuit 120 taking control can assume the "master" role (master) and the first integrated circuit 110 assumes the "slave" role (slave). When the second ic 120 takes control, the second ic 120 may output the second clock signal SCL to the first ic 110. Based on the frequency signal SCL, the first integrated circuit 110 and the second integrated circuit 120 may operate cooperatively.
When the first integrated circuit 110 obtains control, the first data pin D1 of the first integrated circuit 110 is used as the data output pin of the first integrated circuit 110, and the first data pin D1 of the second integrated circuit 120 is used as the data input pin of the second integrated circuit 120. Therefore, the first integrated circuit 110 taking control can output the main data signal MOSI to the second integrated circuit 120. When the first integrated circuit 110 obtains the control right, the second data pin D2 of the first integrated circuit 110 is used as the data input pin of the first integrated circuit 110, and the second data pin D2 of the second integrated circuit 120 is used as the data output pin of the second integrated circuit 120. Therefore, the second integrated circuit 120 can output the slave data signal MISO to the first integrated circuit 110 based on the control of the first integrated circuit 110.
When the second integrated circuit 120 obtains the control right, the first data pin D1 of the second integrated circuit 120 is used as the data output pin of the second integrated circuit 120, and the first data pin D1 of the first integrated circuit 110 is used as the data input pin of the first integrated circuit 110. Therefore, the second integrated circuit 120 taking control can output the main data signal MOSI to the first integrated circuit 110. When the second integrated circuit 120 obtains the control right, the second data pin D2 of the second integrated circuit 120 is used as the data input pin of the second integrated circuit 120, and the second data pin D2 of the first integrated circuit 110 is used as the data output pin of the first integrated circuit 110. Therefore, based on the control of the second integrated circuit 120, the first integrated circuit 110 can output the slave data signal MISO to the second integrated circuit 120.
In the present embodiment, the transition of the signal of the first data pin D1 from the fourth logic state to the fifth logic state when the signal of the clock pin CK is at the third logic state is defined as an initial signal. The start signal indicates the start of a data transmission period. "when the signal on the clock pin CK is at the third logic state, the signal on the first data pin D1 transits from the fifth logic state to the fourth logic state" is defined as an end signal. The end signal indicates the end of the data transmission period. The third logic state, the fourth logic state and the fifth logic state can be set according to design requirements. For example, in the present embodiment, the third logic state may be a logic state "1" (e.g., a high logic level), the fourth logic state may be a logic state "1", and the fifth logic state may be a logic state "0" (e.g., a low logic level). In another embodiment, the third logic state may be a logic state "0", the fourth logic state may be a logic state "0", and the fifth logic state may be a logic state "1".
FIG. 3 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to an embodiment of the invention. Please refer to fig. 1 and fig. 3. In the embodiment shown in fig. 3, the transition of the main data signal MOSI of the first data pin D1 from logic state 1 to logic state 0 (e.g., low) when the clock signal SCL of the clock pin CK is logic state 1 (e.g., high) is defined as a start signal STA, and the transition of the main data signal MOSI from logic state 0 to logic state 1 when the clock signal SCL is logic state 1 is defined as an end signal STP. The start signal STA represents the start of a data transfer period and the end signal STP represents the end of the data transfer period.
In the embodiment shown in FIG. 3, the initial state of the direction control signal DIR is assumed to be a logic state "0" (e.g., a low logic level). When the direction control signal DIR is at logic state "0", the second integrated circuit 120 gains control. When the second ic 120 takes control (i.e. when the direction control signal DIR is at logic state "0"), the second ic 120 may output the clock signal SCL to the first ic 110, and the second ic 120 may output the start signal STA to the first ic 110 to start a data transmission period DP1. In the data transmission period DP1, the pulse width (duration lasting high logic level) or the trough width (duration lasting low logic level) of the clock signal SCL is smaller than the threshold width, which can be determined according to design requirements. During the data transmission period DP1, the second integrated circuit 120 may output the master data signal MOSI to the first integrated circuit 110, and the first integrated circuit 110 may output the slave data signal MISO to the second integrated circuit 120. In the data transmission period DP1, the main data signal MOSI can transition (transition) when the clock signal SCL is at a low logic level, and the main data signal MOSI does not transition when the clock signal SCL is at a high logic level. The operation of the slave data signal MISO can be analogized by referring to the description of the master data signal MOSI. The second integrated circuit 120 may output an end signal STP to the first integrated circuit 110 to end the data transmission period DP1.
The first IC 110 may pull the DIR signal to logic 1 (e.g., high) to retrieve control from the second IC 120. When the first integrated circuit 110 obtains control (i.e. when the direction control signal DIR is in the logic state "1"), the first integrated circuit 110 may output the clock signal SCL to the second integrated circuit 120, and the first integrated circuit 110 may output the start signal STA to the second integrated circuit 120 to start a data transmission period DP2. During the data transmission period DP2, the first integrated circuit 110 may output the master data signal MOSI to the second integrated circuit 120, and the second integrated circuit 120 may output the slave data signal MISO to the first integrated circuit 110. The operations of the clock signal SCL, the master data signal MOSI and the slave data signal MISO in the data transmission period DP2 can be analogized by referring to the related descriptions of the data transmission period DP1. The first integrated circuit 110 may output an end signal STP to the second integrated circuit 120 to end the data transmission period DP2.
It is assumed that the pulse width (or the valley width) of the clock signal SCL during the data transmission period (e.g., the data transmission period DP1 or the data transmission period DP2 shown in fig. 3) is less than a threshold width. The threshold width may be determined according to design requirements. In the embodiment shown in fig. 1, the pulse width (or the trough width) of the clock signal SCL is greater than the threshold width when the first integrated circuit 110 takes control is defined as a reset signal. The first integrated circuit 110 may reset the second integrated circuit 120 by the reset signal. Therefore, the first integrated circuit 110 (the second integrated circuit 120) can omit an additional reset pin.
FIG. 4 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to another embodiment of the present invention. Please refer to fig. 1 and fig. 4. In the embodiment shown in fig. 4, the reset signal RST is defined as the clock signal SCL and/or the main data signal MOSI being pulled down for a duration exceeding the threshold width (e.g., exceeding 1 millisecond) when the first integrated circuit 110 is under control (i.e., when the direction control signal DIR is at logic state "1"). The first integrated circuit 110 may reset the second integrated circuit 120 by the reset signal RST.
FIG. 5 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to another embodiment of the present invention. Please refer to fig. 1 and 5. In the embodiment shown in fig. 5, the "pulse width PW of the direction control signal DIR falls within a width range" is defined as an interrupt (interrupt) signal INT. The width range may be determined according to design requirements. For example, the width may range from 1 microsecond to 10 microseconds. The first integrated circuit 110 may inform the second integrated circuit of an interrupt request via the interrupt signal INT. Therefore, the first integrated circuit 110 (the second integrated circuit 120) can omit an additional interrupt pin.
FIG. 6 is a timing diagram illustrating signals of the circuit shown in FIG. 1 according to yet another embodiment of the present invention. Please refer to fig. 1 and fig. 6. It is assumed that the first IC 110 has an interrupt flag (or interrupt register). In the embodiment shown in FIG. 6, when the second IC 120 obtains control from the first IC 110 (i.e., after the direction control signal DIR changes from logic state "1" to logic state "0"), the second IC 120 reads the interrupt flag (or interrupt register) of the first IC 110 via the main data signal MOSI. Based on the request/control of the second IC 120, the first IC 110 can transmit the contents of the interrupt flag (or interrupt register) back to the second IC 120 via the slave data signal MISO. According to the content of the interrupt flag (or interrupt register), the second IC 120 can know whether the first IC has issued an interrupt request. Therefore, the first integrated circuit 110 (the second integrated circuit 120) can omit an additional interrupt pin.
It is noted that, in different application scenarios, the related functions of the first integrated circuit 110 and/or the second integrated circuit 120 may be implemented as software, firmware or hardware by using a general programming language (e.g., C or C + +), a hardware description language (e.g., verilog HDL or VHDL), or other suitable programming languages. The programming language that can perform the related functions may be arranged as any known computer-accessible media such as magnetic tapes (magnetic tapes), semiconductor (semiconductors) memories, magnetic disks (magnetic disks) or optical disks (compact disks such as CD-ROM or DVD-ROM), or may be transmitted through the Internet (Internet), wired communication, wireless communication or other communication media. The programming language may be stored in an accessible medium of the computer to facilitate the access/execution of programming codes of the software (or firmware) by the processor of the computer. For a hardware implementation, various logic blocks, modules, and circuits within one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital Signal Processors (DSPs), field Programmable Gate Arrays (FPGAs), and/or other processing units may be used to implement or perform the functions described in the embodiments herein. In addition, the apparatus and method of the present invention may be implemented by a combination of hardware and software.
In summary, the electronic device 100 and the operating method thereof according to the above embodiments can dynamically switch the control right to one of the first integrated circuit 110 and the second integrated circuit 120 through the direction control signal DIR. When the first integrated circuit 110 takes control, the first integrated circuit 110 may output the clock signal SCL to the second integrated circuit 120, and the first integrated circuit 110 may output the main data signal MOSI to the second integrated circuit 120. Based on the control of the first integrated circuit 110, which obtains the control right, the second integrated circuit 120 can output the slave data signal MISO to the first integrated circuit 110. When the second integrated circuit 120 takes control, the second integrated circuit 120 may output the clock signal SCL to the first integrated circuit 110, and the second integrated circuit 120 may output the main data signal MOSI to the first integrated circuit 110. Based on the control of the second integrated circuit 120, which obtains the control right, the first integrated circuit 110 can output the slave data signal MISO to the second integrated circuit 120.
Although the present invention has been described with reference to particular embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (14)
1. An electronic device, comprising:
a first integrated circuit having at least a direction pin and a frequency pin, wherein the direction pin of the first integrated circuit outputs a direction control signal; and
a second integrated circuit having at least a direction pin and a frequency pin, wherein the direction pin of the second integrated circuit is coupled to the direction pin of the first integrated circuit to receive the direction control signal, the frequency pin of the second integrated circuit is coupled to the frequency pin of the first integrated circuit,
wherein the first integrated circuit gains control when the direction control signal is in a first logic state, the frequency pin of the first integrated circuit outputs a first frequency signal to the frequency pin of the second integrated circuit when the first integrated circuit gains the control, the second integrated circuit gains the control when the direction control signal is in a second logic state, and the frequency pin of the second integrated circuit outputs a second frequency signal to the frequency pin of the first integrated circuit when the second integrated circuit gains the control.
2. The electronic device of claim 1, wherein the initial state of the direction control signal is the second logic state.
3. The electronic device of claim 1, wherein the first integrated circuit further has a first data pin and a second data pin, the second integrated circuit further has a first data pin and a second data pin, the first data pin of the second integrated circuit is coupled to the first data pin of the first integrated circuit, the second data pin of the second integrated circuit is coupled to the second data pin of the first integrated circuit;
wherein when the first integrated circuit obtains the control right, the first data pin of the first integrated circuit is used as a data output pin of the first integrated circuit, the first data pin of the second integrated circuit is used as a data input pin of the second integrated circuit, the second data pin of the first integrated circuit is used as a data input pin of the first integrated circuit, and the second data pin of the second integrated circuit is used as a data output pin of the second integrated circuit; and
when the second integrated circuit obtains the control right, the first data pin of the second integrated circuit is used as the data output pin of the second integrated circuit, the first data pin of the first integrated circuit is used as the data input pin of the first integrated circuit, the second data pin of the second integrated circuit is used as the data input pin of the second integrated circuit, and the second data pin of the first integrated circuit is used as the data output pin of the first integrated circuit.
4. The electronic device according to claim 3, wherein "the transition of the signals of the plurality of first data pins from a fourth logic state to a fifth logic state when the signals of the frequency pins of the first and second integrated circuits are in the third logic state" is defined as a start signal indicating the start of a data transfer period, "the transition of the signals of the plurality of first data pins from the fifth logic state to the fourth logic state when the signals of the frequency pins of the first and second integrated circuits are in the third logic state" is defined as an end signal indicating the end of the data transfer period.
5. The electronic device of claim 1, wherein a pulse width of the first clock signal during data transmission is less than a threshold width, and a reset signal is defined as the pulse width of the first clock signal being greater than the threshold width when the first integrated circuit obtains the control right, and the first integrated circuit resets the second integrated circuit through the reset signal.
6. The electronic apparatus according to claim 1, wherein "a pulse width of the direction control signal falls within a width range" is defined as an interrupt signal by which the first integrated circuit notifies the second integrated circuit of an interrupt request.
7. The electronic device as claimed in claim 1, wherein the first IC has an interrupt flag, and when the second IC obtains the control right from the first IC, the second IC reads the interrupt flag of the first IC to know whether the first IC has an interrupt request.
8. A method of operation of an electronic device, wherein the electronic device includes a first integrated circuit and a second integrated circuit, the method of operation comprising:
outputting a direction control signal to a direction pin of the second integrated circuit by the direction pin of the first integrated circuit;
when the direction control signal is in a first logic state, the first integrated circuit obtains control power;
when the first integrated circuit obtains the control right, the frequency pin of the first integrated circuit outputs a first frequency signal to the frequency pin of the second integrated circuit;
when the direction control signal is in a second logic state, the second integrated circuit obtains the control right; and
when the second IC obtains the control right, the frequency pin of the second IC outputs a second frequency signal to the frequency pin of the first IC.
9. The method of operation of claim 8, wherein the initial state of the direction control signal is the second logic state.
10. The method of claim 8, wherein a first data pin of the second integrated circuit is coupled to a first data pin of the first integrated circuit, and a second data pin of the second integrated circuit is coupled to a second data pin of the first integrated circuit;
when the first integrated circuit obtains the control right, a first data pin of the first integrated circuit is used as a data output pin of the first integrated circuit, a first data pin of the second integrated circuit is used as a data input pin of the second integrated circuit, a second data pin of the first integrated circuit is used as a data input pin of the first integrated circuit, and a second data pin of the second integrated circuit is used as a data output pin of the second integrated circuit; and
when the second integrated circuit obtains the control right, the first data pin of the second integrated circuit is used as the data output pin of the second integrated circuit, the first data pin of the first integrated circuit is used as the data input pin of the first integrated circuit, the second data pin of the second integrated circuit is used as the data input pin of the second integrated circuit, and the second data pin of the first integrated circuit is used as the data output pin of the first integrated circuit.
11. The method of operation of claim 10, further comprising:
defining "signals of the plurality of first data pins transition from a fourth logic state to a fifth logic state when signals of the frequency pins of the first and second integrated circuits are in a third logic state" as a start signal, wherein the start signal represents a start of a data transfer period; and
defining "the signals of the plurality of first data pins transition from the fifth logic state to the fourth logic state when the signals of the frequency pins of the first and second integrated circuits are the third logic state" as an end signal, wherein the end signal indicates an end of the data transfer period.
12. The method of operation of claim 8, wherein a pulse width of the first frequency signal during data transmission is less than a threshold width, the method of operation further comprising:
defining the pulse width of the first clock signal greater than the threshold width when the first integrated circuit obtains the control right as a reset signal, wherein the first integrated circuit resets the second integrated circuit through the reset signal.
13. The method of operation of claim 8, further comprising:
defining "the pulse width of the direction control signal falls within a width range" as an interrupt signal, wherein the first integrated circuit informs the second integrated circuit of an interrupt requirement through the interrupt signal.
14. The method of operation of claim 8, wherein the first integrated circuit has an interrupt flag, the method of operation further comprising:
when the second IC obtains the control right from the first IC, the second IC reads the interrupt flag of the first IC to know whether the first IC has proposed an interrupt request.
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