JP2845251B2 - Integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device,
More particularly, the present invention relates to an integrated circuit device having a bus system for connecting different signals in time division from a plurality of output devices to one line and transmitting the signals to one or more input devices.

[0002]

2. Description of the Related Art As a conventional integrated circuit device, there is an integrated circuit device as a bus system as shown in a block diagram of FIG. FIG. 8 is a block diagram showing the internal structure of timing circuit 1 in the integrated circuit device shown in FIG. FIG. 9 is a timing chart showing the operation timing of each part of the integrated circuit device shown in FIG. 7 and the timing circuit 1 shown in FIG. For the sake of explanation, the names of the signals shown in FIG. 9 are the same as the names of the signal lines shown in FIG.
The timing circuit 1 shown in FIG.
It is composed of 3, 44, 45, a three-input NOR gate 41, and three inverters, and inputs a clock signal 50 and outputs timing signals 12, 13, and 14.

In FIG. 7, a three-state output buffer 4
And 7 are activated when the timing signals 12 and 13 output from the timing circuit 1 become high level "1", respectively, and output the data on the signal lines 3 and 6 to the outputs 5 and 8, respectively. When 12 and 13 go to a low level "0", the respective outputs are brought into a high impedance state. Outputs 5 and 8 are connected to bus 9. The data latch 11 takes in the data on the bus 9 via the data input 10 when the timing signal 14 output from the timing circuit 1 is at a high level, and outputs the timing when the timing signal 14 changes from a high level to a low level. Holds the data on data input 10 immediately before signal 14 goes low. Data input or held by the data latch 11 is output from a latch output 15. A common clock signal 50 is input to the timing circuit 1.

In a system which needs to transfer maximum data within a predetermined time and minimize the number of signal lines involved in data transfer, a circuit configuration such as an integrated circuit device shown in FIG. 7 is employed. In this case, the data setup times tDSa and tDSb shown in FIG. 9 are set such that the data on the signal lines 3 and 6 pass through the output buffers 4 and 7 and the data latch 11 The data holding time tDHa and tDHb is designed based on the propagation delay time until the data input 10 is reached, and is determined by the characteristics of the latch 11. In such a case, the timing signal 12 for outputting the data A holds the high level for the data holding time tDHa even after the input timing signal 14 falls at the time A, and transfers the data A on the bus 9. The timing signal 13 for outputting the data B onto the bus 9 must be activated at the same time that the timing signal 12 becomes inactive.

[0005]

However, in the above-mentioned conventional integrated circuit device, the next data such as data B shown in FIG. 9 starts from a period in which certain data such as data A shown in FIG. Due to the dull waveforms of the timing signals 12 and 13 at the end of the output period, the data collide on the bus 9 and there is no problem if the collided data is the same, for example, “1”. When different data such as "0" and "0" collide, a short-circuit current flows between the output buffers 4 and 7 which output the data during the collision, and as a result, a relatively large short-circuit current flows between the power supply and the ground. Flows. Noise caused by the short-circuit current leaks to the outside of the integrated circuit device through the driver circuit when a driver circuit having an external output terminal is connected to a power supply and a ground line through which the short-circuit current flows. Becomes Further, even when the driver circuit having the external output terminal is not connected to the power supply and the ground line through which the short-circuit current flows, the input of the driver circuit having the external output terminal is connected to the power and the ground line through which the short-circuit current flows. When connected to an output buffer, the noise is transmitted through the signal line, and as a result, the noise leaks out of the integrated circuit device through the driver circuit of the external output terminal.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and it is an object of the present invention to prevent a collision between outputs of a plurality of driver circuits that output signals to a bus in an integrated circuit device having a bus system. It is an object of the present invention to provide an integrated circuit device which can eliminate noise caused by collision of outputs of a plurality of driver circuits.

[0007]

Integrated circuit device according to the present invention SUMMARY OF THE INVENTION comprises a signal Route, and signal output means for outputting a signal to said signal lines, output timing control said signal output means controls the timing of activation means a signal input means for inputting said <br/> signal on the signal line in an integrated circuit device in which the signal input means and an input timing control means for controlling the timing of activating the signal line Capacitive
A load on the signal line by the capacitive load.
By holding the signal, the output timing control means
A signal required for the signal input means to input a signal
The signal output is stopped in a time shorter than the holding time . Another integrated circuit device according to the present invention includes a bus.
An output buffer for outputting data to the bus;
An output timer that controls when the output buffer is activated.
Inputting the data on the bus
A data latch, and a timer for activating the data latch.
Having input timing control means for controlling
In the integrated circuit device, the bus has a capacitive load,
Data on the bus by a capacitive load.
The output timing control means causes the data
Than the signal holding time required for the
The signal output is stopped in a short time .

[0008]

In the integrated circuit device according to the present invention, a bus system for connecting different signals in time division from a plurality of signal output means to one signal line and transmitting the signals to one or more signal input means is provided. In the integrated circuit device having a signal line, by connecting a capacitive load to a signal line serving as a bus, a timing for ending the activation of a plurality of signal output units connected to the signal line is connected to the signal line. At the same timing as the end of activation of the signal input means. With these, the integrated circuit device according to the present invention can hold previously input data on the signal line in the capacitive load, so that even if the signal output means for outputting data to the signal line is switched, those signals are output. No collision occurs between the output means, and therefore, noise due to the short-circuit current can be extremely reduced.

[0009]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an integrated circuit device according to a first embodiment of the present invention. In FIG. 1, the same components as those of the conventional integrated circuit device shown in FIG. 7 are denoted by the same reference numerals, and detailed description is omitted. Book 1 shown in FIG.
In the integrated circuit device according to the second embodiment, different components from the conventional integrated circuit device shown in FIG. 7 are an internal configuration of the timing circuit 21 and a portion in which the capacitive load 40 is connected to the bus 9. . The timing circuit 21 outputs output timing signals 22 and 23 and an input timing signal 24.

FIG. 2 is a block diagram showing the internal structure of the timing circuit 21 in the integrated circuit device according to the first embodiment shown in FIG. In FIG. 2, the same components as those of the conventional timing circuit shown in FIG. 9 are denoted by the same reference numerals to clarify their correspondence. 2 includes data latches 42, 43, 44, 5
4, 55, 3-input NOR gate 41, 2-input NOR
It is composed of a gate 51, AND gates 52 and 53 and four inverters, and inputs a clock signal 50 to output output timing signals 22, 23 and an input timing signal 24.

Next, the operation of the integrated circuit device according to the first embodiment configured as described above will be described. FIG.
4 is a timing chart showing operation timings of respective parts in the integrated circuit device according to the first embodiment shown in FIG. 1 and the timing circuit shown in FIG. As shown in FIG. 3, the falling edge of the output timing signal 22 has exactly the same timing as the falling edge of the input timing signal 24. In the conventional integrated circuit device as shown in FIG. 7, the data holding time in the latch 11 is not satisfied, but in the configuration of the integrated circuit device according to the present embodiment shown in FIG. 1, the capacitive load 40 is connected to the bus 9. Therefore, the data immediately before the falling of the output timing signal 22 is held by the capacitive load 40 as charges corresponding to the data. The capacity of the capacitive load 40 is determined by the time at which the capacity should hold data. That is, in the integrated circuit device according to the present embodiment shown in FIG. 1, only the output buffers 4 and 7 charge and discharge the capacitive load 40, and if the line itself of the bus 9 is completely insulated. If
Data can be held sufficiently even with an extremely small capacity. Actually, since there is a leakage current at the line and the buffer output, the capacitance of the capacitive load 40 is determined by the leakage current and the time to be held. When the integrated circuit device according to the present embodiment is configured using a metal oxide film type semiconductor, since the leakage current thereof is extremely small, the capacitance of the capacitive load 40 may be extremely small.

When the output timing signal 22 falls,
When the next output timing signal 23 is activated, the current flowing into or out of the output buffer 7 is equal to the amount of charge stored in the capacitive load 40. The current is usually much smaller than the current flowing when the outputs of the output buffers 4 and 7 in the conventional integrated circuit device shown in FIG. 7 collide due to dull waveforms of the timing signals 12 and 13.

That is, in the integrated circuit device according to the first embodiment, the noise component appearing between the power supply and the ground when the buffers 4 and 7 are activated is smaller than the noise component generated in the conventional integrated circuit device. Extremely small.

FIG. 4 is a block diagram showing an integrated circuit device according to a second embodiment of the present invention. In the integrated circuit device according to the second embodiment shown in FIG. 4, different components from the integrated circuit device according to the first embodiment shown in FIG.
This is an internal configuration of a timing circuit 71 and a data latch 81 which is a D-type flip-flop. The timing circuit 71 receives the common clock signal 50 and outputs output timing signals 82 and 83 and an input timing signal 84. The data latch 81 reads the data of the input 10 during the low level period of the timing signal 84, holds the content at the rising edge of the timing signal 84, and outputs the content to the output 85.

FIG. 5 is a block diagram showing the internal structure of the timing circuit 71 in the integrated circuit device according to the second embodiment shown in FIG. In FIG. 5, the same components as those of the timing circuit according to the first embodiment shown in FIG. 2 are denoted by the same reference numerals to clarify their correspondence. FIG.
The timing circuit 71 shown in FIG.
3, 44, 45, a three-input NOR gate 41, an OR gate 74, AND gates 72, 73, and three inverters. The clock signal 50 is input to output timing signals 82, 83 and the input. The timing signal 84 is output.

FIG. 6 shows the integrated circuit device shown in FIG.
6 is a timing chart showing operation timings of respective units of the timing circuit 71 shown in FIG. As shown in FIG. 6, the rising edge of the output timing signal 82 has exactly the same timing as the falling edge of the input timing signal 84. In the conventional integrated circuit device, the data holding time in the latch 81 is not satisfied, but in the integrated circuit device shown in FIG. 4, since the capacitive load 40 is connected to the bus 9,
The data immediately before the rise of the output timing signal 82 is
The data is held as a charge corresponding to the data by the capacitive load 40.

As a result, the integrated circuit device according to the second embodiment has a noise component that appears between the power supply and the ground when the buffers 4 and 7 are activated as in the first embodiment. It is extremely small compared to the noise component generated in the device.

[0019]

As described above, according to the integrated circuit device of the present invention, the timing of ending the activation of the output buffer connected to the bus by connecting the capacitive load to the bus. At the same timing as the end of the activation of the input timing signal of the signal input circuit connected to the bus, and the data holding time (tDH) which must be activated in the output buffer conventionally connected to the bus. During the period of, the previous data can be held by the charged charges in the capacitive load connected to the bus, so that even if the output buffers for outputting data to the bus are switched, collision between the output buffers may occur. This does not occur, so that noise due to short-circuit current can be extremely reduced.

When the integrated circuit device according to the present invention is constructed using a metal oxide semiconductor as a circuit element, the capacitance associated with the source and drain of the output buffer and the capacitance of the input buffer are used as the capacitive load connected to the bus. It goes without saying that a capacitance associated with the gate, a stray capacitance existing between the bus wiring and the substrate, and the like can be used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an internal structure of a timing circuit 21 in the integrated circuit device shown in FIG.

FIG. 3 is a timing chart showing operation timings of respective units in the integrated circuit device according to the present embodiment shown in FIG. 1 and the timing circuit shown in FIG. 2;

FIG. 4 is a block diagram showing an integrated circuit device according to a second embodiment of the present invention.

5 is a block diagram showing an internal structure of a timing circuit 71 in the integrated circuit device shown in FIG.

6 is a timing chart showing operation timings of respective parts of the integrated circuit device shown in FIG. 4 and the timing circuit shown in FIG.

FIG. 7 is a block diagram illustrating an example of a conventional integrated circuit device.

8 is a block diagram showing an internal structure of a timing circuit 1 in the integrated circuit device shown in FIG.

9 is a timing chart showing operation timings of respective parts of the integrated circuit device shown in FIG. 7 and the timing circuit shown in FIG.

[Explanation of symbols]

 4, 7; output buffer circuit 9; bus 11; data latch 21; timing circuit 40; capacitive load

Claims (3)

(57) [Claims] And 1. A signal Line, and <br/> signal output means for outputting a signal to said signal line, and an output timing control means for said signal output means controls the timing for activating the signal line
A signal input means for inputting the signal of the above, in the integrated circuit device in which the signal input means and an input timing control means for controlling the timing of activating the signal lines
Has a capacitive load, and the capacitive load causes the signal
The output timing control is performed by holding the signal on the line.
The control means is necessary for the signal input means to input a signal.
The signal output is stopped in a time shorter than the signal holding time . 2. The integrated circuit according to claim 1, wherein said output timing control means terminates activation of said output means simultaneously with termination of activation of said input means by said input timing control means. apparatus. 3. A bus and an output for outputting data to the bus.
Buffer and timing when the output buffer is activated
Output timing control means for controlling
A data latch for inputting data, and the data latch
Timing control to control the timing of activation
Means, wherein the bus is a capacitor.
A capacitive load, and the capacitive load causes data on the bus to be
The output timing control means.
Is the signal required for the data latch to input a signal.
It is that current product circuit device, characterized in that stops the signal output in a shorter time than No. retention time.