JP3129243B2 - Interface circuit in bus line data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface (hereinafter, referred to as an interface) in a bus line data transfer device for processing an interface when data is transferred through a bus line.
I / F circuit).

[0002]

2. Description of the Related Art FIG. 12 is a circuit diagram showing a configuration of a conventional I / F circuit. In FIG. 12, the bus master 1 comprises a peripheral unit 2 which is a slave, and a pull-up resistor R3 for raising the potential of the bus line to a high level. The bus master 1 comprises a three-state output buffer 4 and an input buffer 11. It is configured. The same applies to the peripheral portion 2. FIG. 13 is a timing chart of the operation of the I / F circuit shown in FIG. 12 and 13, the bus master 1
At the time of data transfer (write access) from the
First, data 1 (high level) is transferred, then data 0
(Low level) is being transferred.

In FIG. 13, SA1 is an output EN signal (1) for controlling enable of the 3-state output buffer 4 in the bus master 1, and SB2 is an input signal of the 3-state output buffer 4 and is internal data. Also, SF1
Is the data on the bus line that performs data transfer between the bus master 1 and the peripheral unit 2, and SA2 is 3
Output EN controlling enable of state output buffer
Signal 2.

The three-state output buffer 4 outputs the input signal value as it is when the output EN signal 1 (SA1) is at a low level, and outputs a write access end (Hi-z) output when it is at a high level. . After outputting the low-level data for the second time thereafter, the processing through the bus line ends.

In this case, since the bus line is pulled up by the resistor R3, its potential is set to a high level. Here, when the bus line is open and the resistor R
When the potential is raised from the low level to the high level by 3, it takes some time, so that the potential may be an intermediate potential. In this case, a through current flows in the CMOS and a large amount of power is consumed. Further, in an actual device, the bus line performs multi-bit transmission, and consumes large power as the number of bits of the bus line increases.

FIG. 14 is a timing chart when the bus master 1 in the I / F circuit shown in FIG. In FIG. 14, SA2 is an output enable (EN) signal (2) of the 3-state output buffer in the peripheral section 2, SB2 is an input signal (internal data) to the 3-state output buffer, SF is data on the bus master, and SA1 is This is an output enable (EN) signal (1) of the three-state output buffer 4 in the bus master 1.

In this case, first, a high level signal is output from the peripheral section 2 and then a low level signal is output. At this time, the output enable (EN) signal (1) SA1 of the three-state output buffer 4 in the bus master 1 is
The state output buffer 4 ends the write access,
The input state is as the bus master.

In FIG. 14, at the end of the second bus master access, the three-state output buffer in the peripheral unit 2 ends the write access and releases the bus line.
At this time, the bus line rises from a low level to a high level potential by the resistor R3. However, raising the potential by the resistor R3 requires a certain period of time, so that the potential may become an intermediate potential. In this case, a large amount of power is consumed as described above.

FIG. 15 is a timing chart when the I / F circuit shown in FIG. 12 is reset. In FIG.
The reset in the I / F circuit is an asynchronous process with respect to the operation of the device. Therefore, an intermediate potential may be generated during access to the bus line. Here, the bus master 1 is reset during the low-level data output.
In the figure, SA1 is an output EN signal 1 for controlling enable of the three-state output buffer 4 of the bus master 1, and SB1
1 is an input signal of the 3-state output buffer 4 and is internal data. SF1 is data on the bus line, and further indicates a reset (low-level active) signal of the device itself.

First, the output EN signal (1) SA1 is at a high level and then at a low level. It is reset at the time of this low level output. The write access to the three-state output buffer 4 for releasing the bus line from the reset is completed. Therefore, the data signal SF on the bus line is opened, and the potential of the bus line rises from a low level to a high level by the resistor R3. However, to raise the potential by the resistor R3,
Since a certain period of time is required, the potential becomes the intermediate potential as described above, and a large current flows.

FIG. 16 is a circuit diagram showing a configuration of another I / F circuit. In FIG. 16, the I / F circuit has a signal transition detection circuit 20 and a signal holding circuit 21. The signal transition detection circuit 20 detects a transition of a signal applied to the bus line 24 and outputs a control signal CNT. The signal holding circuit 21 holds the signal given to the bus line 24 under the control of the control signal CNT. The signal transition detection circuit 20 includes a delay element 2 for inputting a signal on the bus line 24.
3 and the input of the signal of the bus line 24 and the output
An input EX-OR (exclusive OR) gate 22 is provided. The two-input EX-OR gate 22 controls the control signal CNT.
Is output. Signal holding circuit 21
Is composed of inverting gates 26 and 27 and a P-type MOSFET 25. The signal of the bus line 24 is input to the inverting gate 26, and the output signal of the inverting gate 26 is input to the inverting gate 27. The source electrode of the P-type MOSFET 25 is connected to the bus line 24, the drain electrode is connected to the output of the inverting gate 27, and the control signal CNT is input to the gate electrode.

FIG. 17 is a timing chart of the operation of another I / F circuit shown in FIG. In FIGS. 16 and 17,
At this timing, the signal on the bus line 24, the delay element 2
Output of 3 (node A), output of 2-input EX-OR gate 22 (node B), output of inverting gate 27 (node C)
Indicates the potential at each time. Before the time t1, the potential of the bus line 24 is at the low level, and the potential of the node A is at the low level. Therefore, the potential of the node B (the control signal CNT) is also at the low level.

The potential of the bus line 24 is inverted twice by the inverting gates 26 and 27 and returns to the first signal.
In addition, the potential of the node C also becomes low level. On the other hand, the P-type MOSFET 25 is on, and the potential of the node C does not collide with the potential of the bus line 24. Therefore, the inversion gates 26 and 27 hold the potential of the bus line 24. Here, when the three-state output buffer 37 starts outputting the high level at time t1, the output of the delay element 23 is at the low level for a while, and the two-input EX-OR gate 22
, A different value is input to, so that the output from this transitions from low level to high level.

In this case, the two-input EX-OR gate 22
Has a delay time d2 in its processing, and at time t2 which is delayed from the time t1 by the delay time d2, the control signal CN
T transitions from low level to high level. This time t
Up to 2, the P-type MOSFET 25 is on and the node C
Is also equal to the potential of the bus line 24. Therefore, a potential collision occurs, and a leak current flows from the high-potential-side power supply of the three-state output buffer 37 to the low- and high-potential-side power supply of the inverting gate 27 between times t1 and t2. Time t2
, When the control signal CNT goes high, the P-type
OSFET 25 is turned off.

Therefore, no leak current flows from the three-state output buffer 37 to the inversion gate 27. That is, the potential collision on the bus line 24 ends, and the potential on the bus line 24 becomes high at time t2. When the potential of the bus line 24 goes high, the potential of the node C goes high. However, from time t2 to time t3 when the sum of the delay times (d6 + d7) in the inverting gates 26 and 27 has elapsed, the potential of the node C can be low or high depending on the potential of the bus line 24 at time t2. The uncertainty is shown by a broken line in FIG.

That is, at the time t3, the potential of the node C is set to the high level. On the other hand, the potential of the node A transitions to the high level at time t4, which is delayed from the time t1 by the delay time d3 of the delay element 23. Therefore,
At time t5, which is delayed from the time t4 by the delay time d2, the control signal CNT changes from the high level to the low level, and the P-type MOSFET 25 is turned on again.

At this time, since the potential of the bus line 24 is already at a high level, no potential collision occurs even if the bus line 24 is connected to the node C by the P-type MOSFET 25.
As a result, a potential collision occurs at the beginning of the transition of the bus line 24 and a leak current flows, but the time is a delay time d2 of only the two-input EX-OR gate 22.

FIG. 18 is another timing chart of the operation of the other I / F circuit of FIG. In FIG. 18, this timing corresponds to bus line 2 which was at a high level before time t1.
4 or a low-level transition, and shows P-type M at a time when potential collision may occur.
Since the OSFET 25 is off, the leak current can be suppressed.

FIG. 19 is a circuit diagram showing a configuration of another I / F circuit. In FIG. 19, this I / F circuit
It has a signal transition detection circuit 20a and a signal holding circuit 21a. The signal transition detection circuit 20a has the same configuration as the signal transition detection circuit 20 shown in FIG.
It has an R gate 22 and a delay element 23. The signal holding circuit 21a has an inverting gate 26 connected to the bus line 24 and a P-type MOSFET 25. Further, it has an inverting gate 27a for outputting the output of the inverting gate 26 to the P-type MOSFET 25, and an inverting gate 27b for transmitting the output of the inverting gate 26.

The I / F circuit of this configuration is a P-type MOSFET
25 is on, it holds the data of the inversion gates 26 and 27a bus line 24,
Above, the control signal CNT becomes active at the time when the potential collision may occur, and the P-type MOSFET 25
Is turned off, so that there is an advantage similar to that of the I / F circuit shown in FIG.

FIG. 20 is a circuit diagram showing the configuration of another I / F circuit. In FIG. 20, this I / F circuit
It has a signal transition detection circuit 20b and a signal holding circuit 21d. The signal transition detection circuit 20b has the same configuration as the signal transition detection circuit 20 shown in FIG.
It has an R gate 22 and a delay element 23.

The signal holding circuit 21d has an inverting gate 26 connected to the bus line 24 and an inverting gate 27b to which an output signal is input. FIG.
Signal cutoff circuit 2 in place of the P-type MOSFET 25 shown in FIG.
5a, and a logic inversion circuit 27c in place of the inversion gate 26a. The signal cutoff circuit 25a is a P-type M
It comprises an OSFET 51, an N-type MOSFET 52, and an inverting gate 53.

P-type MOSFET 51 and N-type MOSFET
In T52, each of the source electrodes is connected to a high potential power supply and ground. The high potential power supply and the ground correspond to a high level and a low level, respectively. P-type MOSFET5
The control signal CNT and its inverted signal are input to the gate electrodes of the 1-type and N-type MOSFETs 52, respectively. The logic inversion circuit 27c includes a P-type MOSFET 71 and an N-type
An output from the inverting gate 26 is commonly input to this gate electrode.

Further, a P-type MOSFET 71 and an N-type MO
The inversion gate 26 is commonly used as the gate electrode of the SFET 72.
And the drain line is connected to the bus line 24. The source electrodes of the P-type MOSFET 71 and the N-type MOSFET 72 are
It is connected to the drain electrodes of the FET 51 and the N-type MOSFET 52.

That is, the signal cutoff circuit 25a and the logic inversion circuit 27c form a clocked inverter.
The I / F circuit shown in FIG. 20 corresponds to the I / F shown in FIG.
Same as the circuit. That is, when a signal transition occurs in the bus line 24, the control signal CNT becomes active and goes high, turning off both the P-type MOSFET 51 and the N-type MOSFET 52. Therefore, the potentials of the drain electrodes of the P-type MOSFET 71 and the N-type MOSFET 72 are determined by the three-state output buffer 37 or the three-state output buffer 38 that drives the bus line 24. Therefore, collision of signals in the bus line 24 is avoided, and leakage current is suppressed.

FIG. 21 is a circuit diagram showing a configuration of still another I / F circuit. In FIG. 21, this I / F circuit is
It has a signal transition detection circuit 20c and a signal holding circuit 21. In the signal transition detection circuit 20c, one of the input terminals of the two-input EX-OR gate 22 is connected by a capacitor C1 provided between itself and a bus line 24, and is grounded by a resistor R11 (to a low level of 0). Corresponding).
The other input terminal of the two-input EX-OR gate 22 is connected by a capacitor C2 provided between the two-input EX-OR gate 22 and the bus line 24,
Further, it is connected to a high potential point (voltage VDD, corresponding to a high level) by a resistor R12. The signal holding circuit 21 has the same configuration as that shown in FIG. FIG. 22 shows FIG.
FIG. 13 is a timing chart of the operation of another I / F circuit shown in FIG. 21 and 22, the timing is as follows: first, the data of the bus line 24, SF is the data (node F) at one input terminal of the two-input EX-OR gate 22, and SG is the data of the two-input EX-OR gate 22. The other input terminal data (node G), SB is the control signal CNT (node B) of the output of the two-input EX-OR gate 22, and SC is the inverting gate 2
7 shows the potential of the output (node C) at each time.

In the figure, before time t1, the potential of the bus line 24 is at a low level, the capacitor C2 is charged with the voltage VDD, and the capacitor C1 is in a discharged state.
As a result, the potential of the node F is at a low level, the potential of the node G is at a high level, and is at a low level with the control signal CNT. Further, the potential of the bus line 24 returns to the original signal after being inverted twice by the inverting gates 26 and 27, and the potential of the node C becomes low level. On the other hand, P-type MOSF
ET25 is on, and the potential of the node C and the bus line 2
No collision with the potential of 4. As a result, the inversion gates 26 and 2
7 holds the potential of the bus line 24.

Here, at time t1, the output of the three-state output buffer 37 goes high, and when the potential of the bus line 24 changes from the ground low level to the potential VDD, the potentials of the nodes F and G also rise. Here, before the time t1, the potential of the node G is at the voltage VDD, and the potential of the node G is at a high level regardless of this transition. When the node F exceeds the threshold value (about VDD / 2) of the two-input EX-OR gate 22 at time t2, the control signal CNT goes high. The difference between time t2 and time t1 is substantially detected as delay time d14 of signal transition detection circuit 20c.

Until time t2, the P-type MOSFET 25 is on, and the potential of the node C becomes equal to the potential of the bus line 24. As a result, the potential collides and a leak current flows from the high-potential power supply of the three-state output buffer 37 to the low-potential power supply of the inverting gates 26 and 27 from time t1 to t2. Needs to be shortened similarly to the delay time d2 in the configuration shown in FIG.

When the control signal CNT goes high, P
The type MOSFET 25 is turned off. Although the potential of the node C becomes uncertain depending on the potential of the bus line 24 and the threshold value of the inverting gate 26, the potential collision on the bus line 24 ends, and the leakage current stops flowing. However, FIG.
Unlike the configuration shown in FIG. 5, the potential of the bus line 24 does not rise sharply even after the time t2 due to the charging of the capacitors C1 and C2. The potential of the bus line 24 is at time t1
, And at time t10 delayed by time d4, the potential becomes VDD. On the other hand, the potential of the node C is a P-type MOSF
After the ET 25 is turned off (after time t2), the inversion gate 26,
Time t when the sum (d6 + d7) of the 27 delay times has elapsed
Up to 3 is uncertain. Then, at time t3, it is set to the high level. In this case, it is desirable to shorten the delay time d14 to make the control signal CNT active earlier.

It is desirable that time t4 at which control signal CNT becomes inactive be delayed from time t3. That is, it is desirable that the pulse width W is longer than the sum (d6 + d7) of the delays of the inverting gates 26 and 27. This pulse width W can be determined by the time constant C1 · R1. The delay times d6 and d7 of one gate are each 1 ns, and the time constant C1
R1 may be set to about 2 ns.

[0032]

The above conventional example has the following disadvantages (1), (2), (3) and (4).

(1) At the end of write access of a bus master using a bidirectional bus line, a large current temporarily flows when switching from low-level output to Hi-z (write access end) output. That is, the bus line temporarily becomes the intermediate potential, and a through current flows in the CMOS. This is because the bus line is pulled up by a resistor in order to prevent an intermediate potential, but when the output from the low level changes to the end of write access (Hi-z), the potential is increased by the pull-up resistor. This takes some time.

(2) At the end of read access of a bus master using a bidirectional bus line, a large current temporarily flows when the peripheral output to be read-accessed changes from low-level output to end of write access. This flow is the same as in (1), the bus line temporarily has an intermediate potential, and a through current flows in CMOS.

(3) A large current flows temporarily when the device is reset. That is, the bus line is temporarily set to the intermediate potential when reset. This is because the reset for the device is performed at an asynchronous timing with respect to the system. Therefore, when reset is performed during bus line access, the output may change from low level to end of write access, and an intermediate potential is generated.

(4) When the bus master using the bidirectional bus line holds the data in the previous access to prevent the potential from becoming the intermediate potential, the bus lines may temporarily compete to become the intermediate potential. There is. That is, the switching of the input / output of the bus master and the switching of the input / output of the peripheral portion cannot be synchronized. This is because the bus master needs to output with write access and switch between input and bus line with read access, but if the same bus master and the peripheral unit try to switch between input and output at the timing, switching occurs due to bus line contention And a large current flows.

The present invention has been made in view of the above points, and has been made in consideration of the above circumstances. When a bus master performs a write access to a peripheral portion, when the bus master executes a write access to a peripheral portion, and when a device is reset, a temporary operation is performed. It is an object of the present invention to provide an I / F circuit in a bus line data transfer device capable of eliminating the generation of an intermediate potential, reducing power consumption due to through current in a CMOS, and preventing the occurrence of element destruction.

[0038]

In order to achieve the above object, the present invention provides an interface circuit in a bus line data transfer device for processing an interface for performing data transfer through a bus line. Alternatively, when the input / output is switched after the write access is completed, the bus line is temporarily driven to stabilize the potential.

Further, the I / F circuit in the bus line data transfer device of the present invention drives the bus line temporarily when the read access or the write access on the bus line is completed and the input / output is switched. A bus master for stabilizing the potential, a bus line controlled by the bus master for data transfer with a peripheral portion, and a voltage source and a bus line for raising and stabilizing the potential when the bus line is at an intermediate potential. And a pull-down resistor connected between the bus line and the ground for stabilizing the potential by lowering the potential.

Further, in the I / F circuit in the bus line data transfer device according to the present invention, the drive drives the bus line to a high level when the bus line is pulled up by connecting a resistor to a voltage source, or When the bus line is pulled down by connecting the resistor to the ground, the bus line is driven to a low level and switched to the end of the write access after a predetermined time.

The I / F circuit in the bus line data transfer device according to the present invention, as the bus master, a three-state output buffer for outputting data to the bus line, and a first delay for delaying an output enable signal of the three-state output buffer. A logic circuit for determining whether the data signal on the bus line is at a low level and whether the output enable signal is inactive, a second delay element for delaying the data signal on the bus line, and a logic circuit And an inversion gate.

The I / F circuit in the bus line data transfer device according to the present invention may further comprise, as the bus master, a three-state output buffer for outputting data to a bus line;
A first delay element for delaying an output enable signal of the state output buffer; a logic circuit for determining whether a data signal on the bus line is at a low level and whether the output enable signal is inactive; A second delay element and a logic inversion gate for delaying the above data signal;
An input buffer for inputting a data signal on the bus line for accessing at the time of output of write access and input of read access to the bus line is provided.

Further, the I / F circuit in the bus line data transfer device according to the present invention comprises, as the bus master, a three-state output buffer for outputting data to a bus line;
A first delay element for delaying the output enable signal of the state output buffer; a logic circuit for determining whether the data signal on the bus line is at a low level and whether the output enable signal is inactive; A second delay element and a logic inversion gate for delaying the data signal, an input buffer for inputting a data signal on the bus line for accessing when a write access is output and a read access to the bus line, and an output enable 3 where the logical sum of the signal and the signal from the first delay element is processed
And an OR gate for outputting an enable signal to the state output buffer.

Further, the I / F circuit in the bus line data transfer device according to the present invention functions as the bus master and delays the three-state output buffer for outputting data to the pull-down bus line grounded by the resistor and the output enable signal. A logic circuit for judging the timing of switching to the high level and the timing of switching the output of the three-state output buffer to the end of the write access, a second delay element for delaying the data signal on the bus line, An input buffer for outputting a data signal.

The I / F circuit in the bus line data transfer device according to the present invention, as the bus master, includes a three-state output buffer that outputs data to a pull-down bus line, and a first delay element that delays an output enable signal. A logic circuit for determining the timing of switching the data signal on the bus line to high level and the timing of switching the output of the three-state output buffer to the end of write access, and a second delay for delaying the data signal on the bus line An element, an input buffer for outputting a data signal on the bus line, and an OR gate for outputting an enable signal to a three-state output buffer obtained by processing an OR of an output enable signal and a signal from the first delay element. It is characterized by having.

Further, the I / F circuit in the bus line data transfer device of the present invention is characterized in that the logic circuit comprises an AND gate and an OR gate.

Further, the I / F circuit in the bus line data transfer device of the present invention is characterized in that the logic circuit comprises a NAND gate and an AND gate.

In the configuration of the present invention, when the read access or the write access on the bus line is completed and the input / output is switched, the bus line is temporarily driven to stabilize the potential. In this case, drive high when the bus line is pulled up by connecting a resistor to the voltage source, or drive low when the bus line is pulled down by connecting the resistor to ground. The drive is switched to the end of the write access after a predetermined time from the drive.

Therefore, by temporarily driving the bus line at the end of the access of the bus line or at the time of resetting, that is, setting the bus line to the high level at the time of pull-up and the low level at the time of pull-down, the bus line is switched from the open state to the resistor. Through which the intermediate potential at the time of pulling or pulling down is extremely reduced.

As a result, at the end of the write access from the bus master to the peripheral portion, when the bus master executes the write access to the peripheral portion, and at the time of resetting the device, the generation of the temporary intermediate potential is eliminated. The power consumption due to the through current is reduced, and the occurrence of the element destruction is prevented.

[0051]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an I / F circuit in a bus line data transfer device according to a first embodiment of the present invention. In FIG. 1, this example is a bus line data transfer device, and includes a bus master 80, a bus line 82 controlled by the bus master 80, a bus line 8
2 and the peripheral portions 83 and 8 where data transfer is performed.
4, 85, and a resistor R that performs a pull-up operation to raise and stabilize the potential when the bus line 82 is at an intermediate potential.
86.

The bus line 82 exchanges data signals, address signals, and control signals through a plurality of signal lines.

FIG. 2 is a circuit diagram showing in detail the structure of the first embodiment shown in FIG. In FIG. 2, the I /
Although the F circuit is represented by 1 bit, the number of a plurality of signal lines (data signals, address signals, control signals) in the bus line 82 in FIG.
A bus master 90 such as a PU or DMA controller (FIG. 1)
A peripheral portion 92 (corresponding to the peripheral portions 83, 84, 85 in FIG. 1) and a pull-up resistor R93 (corresponding to the resistor R86 in FIG. 1). ing.

The bus master 90 outputs a three-state output buffer 94 for outputting data to the bus line, a delay element 95 for delaying an output enable (EN) signal of the three-state output buffer 94, and a data signal on the bus line at a low level. There are logic circuits 96 and 97 for determining whether or not there is a signal, and whether or not the output enable (EN) signal is inactive (high level). Further, it has a delay element 99 for delaying the data signal on the bus line and a logic inversion gate 98.

Next, the operation of the first embodiment shown in FIGS. 1 and 2 will be described.

FIG. 3 is a timing chart of the operation of the first embodiment. In FIG. 3, SA is an output EN signal for controlling an output enable signal of the three-state output buffer 94, SB is a data signal output on a bus line,
SF is the data signal on the bus line, SC is the output EN signal SA, the delay output signal of the delay element 95, SD and SE are the data on the bus line set to low level and the output set to Hi-Z (write access end) output. SG is an output signal of a delay element 99 which is a delay of a data signal on a bus line, and SH is an output signal of a logic inversion gate 98 for judging the case.

In FIG. 1 to FIG. 3, the output EN signal SA
Changes from a high level to a low level first. The data signal SB switches the output signal from a high level to a low level at time t0. At time t1, the output of the three-state output buffer 94 is enabled. However, since the output EN signal SA is delayed by the delay element 95, the data signal SF on the actual bus line changes to low level at time t2. . At time t4, the output EN signal SA goes high so that the output to the bus line ends. Delay element 9 to actual 3-state output buffer 94
The EN signal SC from 5 is delayed.

In this case, the data signal SB on the bus line
Is at a low level and the output EN signal SA is at a high level, so that the input of the 3-state output buffer 94 is at a high level. EN signal S to 3-state output buffer 94
During a time period t4 to t5 when C is delayed, high-level data is output on the bus line. As a result, the data signal SF on the bus line is set from low level to high level. At the subsequent time t5, the output of the three-state output buffer 94 is changed to the end of the write access (Hi).
-Z) Set to output and open the bus line. Recognizing that the data on the bus line has become high level, the input signal SE from the logic circuit 97 to the three-state output buffer 94 becomes low level at time t6.

Note that the delay time of the delay element 99 and the logic inversion gate 98 needs to be longer than the delay time of the delay element 95. That is, “delay time of delay element 95 <delay time of delay element 99 + logic inversion gate 98”.
Note that the delay of the delay element 95 is from time t1 to t2, t4 to t4.
5 and the delay of “the delay time of the delay element 99 + the logic inversion gate 98” is from time t2 to t2, t4 to t
Six hours.

FIG. 4 is a flowchart showing a processing procedure of the operation of the first embodiment shown in FIGS. 1 to 4
, It is determined whether data is "0 or 1" at the time of write access (steps S1 and S2). If the data is "0", the bus master 90 (bus master 80) drives once at the high level after the access is completed, and then releases the bus line as the end of the write access (steps S3 and S4). At the time of read access, the peripheral unit 92 (peripheral units 83 to 85) judges "0 or 1" in the output data (steps S5 and S6). If the data is "0", the bus master 90 (bus master 80) drives at the high level once after the access is completed, and then releases the bus line as the end of the write access (steps S7 and S8).

Next, a second embodiment will be described.

FIG. 5 is a circuit diagram showing the configuration of the second embodiment. In FIG. 5, the bus master 90a of this example is
, That is, the three-state output buffer 9
4, delay elements 95 and 99, logic circuits 96 and 97, and
A logical inversion gate 98; and an input buffer 101 to which the data signal SF on the bus line is input. By replacing this configuration with an input / output buffer conventionally used, a bus master circuit can be configured. Therefore, the bus master 90 (bus master 80) having the configuration of the second embodiment and the peripheral unit 92
By using the (peripheral parts 83 to 85), the bus master 90 can access at the timing of the first embodiment in any case of outputting a write access to a bus line and inputting a read access. Become.

Next, a third embodiment will be described.

FIG. 6 is a circuit diagram showing the configuration of the third embodiment. 6, the bus master 90b of this example is the same as that of FIG.
, A three-state output buffer 94, delay elements 95 and 99, a logic circuit 96,
97, a logical inversion gate 98, and a logical sum (AND) gate 105 added to the input buffer 101. Next, the operation of the third embodiment will be described.

FIG. 7 is a timing chart of the operation of the third embodiment. 7, in the third embodiment, the first embodiment shown in FIG. 3 delays the output EN signal SA by the delay element 95 and outputs the EN signal to the three-state output buffer 94.
While the signal SC is delayed from the time t1 to the time t2, the output is started at the timing of the time t1.

In the figure, SA is a three-state output buffer 94
An output EN signal for controlling the output enable signal of
SB is a data signal output on the bus line, SF is a data signal on the bus line, SC is a signal obtained by delaying the output EN signal SA by the delay element 95, SD and SE are data on the bus line at low level and the output is low. The output signals of the logic circuits 96 and 97 for determining the end of the write access, SG is the output signal of the delay element 99 obtained by delaying the data signal on the bus line, and SH is the output signal of the logic inversion gate 98. .

E to the actual 3-state output buffer 94
Since the N signal SC is an AND process of the output of the output EN signal SA and the output of the delay element 95, the N signal SC coincides with the output start time t1. However, the output end timing is the same as the time t5 in the first embodiment. As a result, it is possible to prevent the data output on the bus line from being delayed. Therefore, reliable and high-speed data transfer is possible even in a short time such as the time from time t1 to time t4.

Next, a fourth embodiment will be described.

FIG. 8 is a circuit diagram showing the configuration of the fourth embodiment. 8, in the bus master 90c of this example, a resistor R93a is grounded in the first to third embodiments. Therefore, if the bus line is open,
The potential on the bus line stabilizes at a low level.

In FIG. 8, this bus master 90c
3-state output buffer 94, delay element 95 for delaying output EN signal SA, high level of the data signal on the bus line, and timing for switching the output of 3-state output buffer 94 to end of write access (Hi-z) And logic circuits 96a and 97a for determining
Further, it has delay elements 98a and 99 for delaying the data signal SF on the bus line, and an input buffer 101 to which the data signal SF on the bus line is input.

FIG. 9 is a timing chart in the processing of the operation of the fourth embodiment. In FIG. 9, SA is an output EN signal for controlling the output enable signal of the three-state output buffer 94, SB is a data signal output on the bus line, SF is a data signal on the bus line, and SC is an output signal. S signal obtained by delaying EN signal SA by delay element 95,
D and SE are output signals of the logic circuits 96a and 97a for determining the case where the data on the bus line is at the low level and the output is set to the end of the write access, and SG is a delay element 99 which delays the data signal on the bus line. Is an output signal of the delay element 98a.

The output EN signal SA is first set to a high level,
Next, it becomes low level. The data signal SB switches the output signal from a high level to a low level at time t0. At time t1, the output of the three-state output buffer 94 is enabled.
In order to delay the N signal SA, the data signal SF on the actual bus line changes to low level at time t2. Time t
4 so that the output to the bus line is terminated at the point of time E4.
Although the N signal SA goes high, the EN signal SC from the delay element 95 to the actual three-state output buffer 94 is delayed. In this case, since the data signal SB on the bus line is at the high level and the output EN signal SA is at the high level, the input of the three-state output buffer 94 is at the low level. During a period from t4 to t5 when the EN signal SC to the three-state output buffer 94 is delayed, low-level data is output on the bus line.

As a result, the data signal SF on the bus line
Is set from high level to low level. At the subsequent time t5, the output of the three-state output buffer 94 is set to the end of the write access, and the bus line is released. Recognizing that the data on the bus line has gone low, the input signal SE from the logic circuit 97a to the three-state output buffer 94 goes high at time t6.

Note that the delay time of the delay elements 98a and 99 needs to be longer than the delay time of the delay element 95. That is, “delay time of delay element 95 <delay time of delay element 98a + delay time of delay element 99”. Note that the delay of the delay element 95 is the time from time t1 to t2 and t4 to t5, and “delay time of delay element 98a + delay element 9”.
The delay of "9" is the time from time t2 to t2 and t4 to t6.

This processing procedure is the same as in FIG.
That is, it is determined whether data is "0 or 1" at the time of write access (steps S1 and S2). If the data is "0", the bus master 90
(Bus master 80) drives once at a high level,
Thereafter, the bus line is released as the end of the write access (steps S3 and S4).

At the time of read access, the peripheral area 92
(Peripheral parts 83 to 85) determine "0 or 1" of the output data (steps S5 and S6). Here, the data is "0"
In the case of (1), the bus master 90 (bus master 80) drives once at the high level after the access is completed, and then releases the bus line as the end of the write access (steps S7 and S8).

Next, a fifth embodiment will be described.

FIG. 10 is a circuit diagram showing the configuration of the fifth embodiment. In FIG. 10, the resistor R93a of the bus master 90d of this example is grounded and pulled down similarly to the fourth embodiment. Therefore, when the bus line is open, the potential on the bus line is stabilized at a low level.

The fifth embodiment has the configuration of the fourth embodiment,
That is, the three-state output buffer 94, the delay element 95 for delaying the output EN signal SA, the data signal on the bus line is at a high level, and the output of the three-state output buffer 94 is changed to a write access end (Hi-z ), A logic circuit 96a for determining the timing of switching to
97a and the data signal SF on the bus line
A logical OR (AND) gate 105 is added to the configuration of delay elements 98a and 99 for delaying the data signal and an input buffer 101 to which the data signal SF on the bus line is input.

FIG. 11 is a timing chart in the processing of the operation of the fifth embodiment. In FIG. 11, SA is an output EN signal for controlling the output enable signal of the three-state output buffer 94, SB is a data signal output on the bus line, SF is a data signal on the bus line, and S
C is an output signal of the OR gate 105, and SD and SE are logic circuits 96 for determining the case where data on the bus line is at a low level and the output is set to the end of write access.
The output signals a and 97a, SG is the output signal of the delay element 99 obtained by delaying the data signal on the bus line, and SH is the output signal of the delay element 98a.

Here, the output EN signal SA is
And the EN signal S of the three-state output buffer 94
The output is started at the same time t1 as the delay from C time t1 to time t2. The EN signal SC of the three-state output buffer 94 is the output EN signal SA
And the output of the delay element 95, which is at the same time as the output start time t1. However, the output end time is the same as the time t5 in the fourth embodiment. As a result, data delay on the bus line is prevented. Therefore, even in the case of higher-speed data transfer and the time from time t1 to t4 is short, reliable data transfer is possible.

[0083]

As described above, according to the present invention,
When input / output switching is performed after read access or write access on the bus line is completed, the bus line is temporarily driven to stabilize the potential. Drive high if the bus line is pulled up by connecting a resistor to the voltage source, or drive low if the bus line is pulled down by connecting a resistor to ground. After a predetermined time, the access is switched to the end of the write access.

That is, the bus line is temporarily set to a high level at the time of pull-up and a low level at the time of pull-down at the time of completion of access of the bus line or at the time of reset, thereby pulling up the bus line from the open state through the resistor. Alternatively, the intermediate potential at the time of lowering is extremely reduced.

As a result, at the end of the write access from the bus master to the peripheral portion, when the bus master executes the write access to the peripheral portion, and at the time of resetting the device, the generation of the temporary intermediate potential is eliminated. The power consumption due to the through current can be reduced. Further, the occurrence of the element destruction can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram of a bus line data transfer device according to the present invention;
FIG. 2 is a block diagram illustrating a configuration of the / F circuit according to the first embodiment.

FIG. 2 is a circuit diagram showing a configuration of a first embodiment shown in FIG. 1 in detail.

FIG. 3 is a timing chart of the operation of the first embodiment.

FIG. 4 is a flowchart showing a processing procedure of an operation of the first embodiment.

FIG. 5 is a circuit diagram showing a configuration of a second embodiment.

FIG. 6 is a circuit diagram showing a configuration of a third embodiment.

FIG. 7 is a timing chart of the operation of the third embodiment.

FIG. 8 is a circuit diagram showing a configuration of a fourth embodiment.

FIG. 9 is a timing chart in the processing of the operation of the fourth embodiment.

FIG. 10 is a circuit diagram showing a configuration of a fifth embodiment.

FIG. 11 is a timing chart in the processing of the operation of the fifth embodiment.

FIG. 12 is a circuit diagram showing a configuration of a conventional I / F circuit.

13 is a timing chart of the operation of the I / F circuit shown in FIG.

14 is a timing chart at the time of read access in the I / F circuit shown in FIG. 12;

FIG. 15 is a timing chart at the time of reset in the I / F circuit shown in FIG. 12;

FIG. 16 is a circuit diagram showing a configuration of another I / F circuit in a conventional example.

FIG. 17 is a timing chart of the operation of another I / F circuit shown in FIG. 16;

FIG. 18 is another timing chart of the operation in the other I / F circuit of FIG. 16;

FIG. 19 is a circuit diagram showing a configuration of still another I / F circuit of the conventional example.

FIG. 20 is a circuit diagram showing a configuration of still another I / F circuit of the conventional example.

FIG. 21 is a circuit diagram showing a configuration of still another I / F circuit of the conventional example.

FIG. 22 is a timing chart of the operation of another I / F circuit shown in FIG. 21;

[Explanation of symbols]

 80, 90 bus master 82 bus line 83, 84, 85, 92 peripheral part R86, R93, R93a resistor 94 three-state output buffer 95, 96a, 97a, 98a, 99 delay element 96, 97 logic circuit 98 logic inversion gate 101 input Buffer 105 OR gate

Claims (7)

(57) [Claims] 1. A read access or line access on a bus line.
When switching between input and output after
To drive the bus line occasionally to stabilize the potential
Bus master, and performs data transfer with the peripherals controlled by the bus master.
Bus line and, when the bus line is at an intermediate potential, raises the potential to
Connected between the voltage source and the bus line to
For pull-up, or stabilize by lowering the potential
Connected between the bus line and ground
Includes a resistor for down, and as the bus master, 3-state output buffer for outputting data to the bus line
When slow the output enable signal of the 3-state output buffer
A first delay element extending and a data signal on the bus line.
Is low and whether the output enable signal is
And a second delay element for delaying a data signal on the bus line
And interface circuitry in the bus line data transfer apparatus characterized by comprising: a logic inverting gate, a. 2. When a read access or a write access on a bus line is completed and an input / output is switched, a bus master for temporarily driving the bus line to stabilize the potential, and being controlled by the bus master. A bus line that performs data transfer with a peripheral portion, and a pull-up connected between a voltage source and the bus line to increase and stabilize a potential when the bus line is at an intermediate potential, or and a resistor for pull-down which is connected between the bus line and ground to stabilize reduce the potential, as the bus master, 3-state output buffer for outputting data to the bus line
When slow the output enable signal of the 3-state output buffer
A first delay element extending and a data signal on the bus line.
Is low and the output enable signal is inactive.
Logic circuit for determining whether the signal is active or not, and a second delay element for delaying a data signal on the bus line
AND LOGICAL INVERTING GATE AND WRITE TO BUS LINE
Access output and read access input.
The data signal on the bus line for performing the
Interface circuit in the bus line data transfer device, characterized in that it comprises an input buffer, a being. 3. A read access or line access on a bus line.
When switching between input and output after
To drive the bus line occasionally to stabilize the potential
Bus master, and performs data transfer with the peripherals controlled by the bus master.
Bus line and, when the bus line is at an intermediate potential, raises the potential to
Connected between the voltage source and the bus line to
For pull-up, or stabilize by lowering the potential
Connected between the bus line and ground
Includes a resistor for down, and as the bus master, 3-state output buffer for outputting data to the bus line
When slow the output enable signal of the 3-state output buffer
A first delay element extending and a data signal on the bus line.
Is low level and the output enable signal is inactive.
And a second delay element for delaying a data signal on the bus line
AND LOGICAL INVERTING GATE AND WRITE TO BUS LINE
Access output and read access input.
The data signal on the bus line for performing the
Input buffer, an output enable signal, and a signal from the first delay element.
OR to the three-state output buffer that processed the logical sum
Interface circuit in the bus line data transfer apparatus characterized by comprising: a logical OR gates, the outputs of the Buru signal. 4. A read access or line access on a bus line.
When switching between input and output after
To drive the bus line occasionally to stabilize the potential
Bus master, and performs data transfer with the peripherals controlled by the bus master.
Bus line and, when the bus line is at an intermediate potential, raises the potential to
Connected between the voltage source and the bus line to
For pull-up, or stabilize by lowering the potential
Connected between the bus line and ground
It includes a resistor for down, and as the bus master, the pull-down of the data to the bus line that is grounded by a resistor
A three-state output buffer for output and a high level for delaying the output enable signal
Timing and output of the three-state output buffer
The timing to switch to the end of write access
Delay circuit for delaying a data signal on the bus line
And an input buffer for outputting a data signal on the bus line
When the interface circuit in the bus line data transfer apparatus comprising: a. 5. A read access or line access on a bus line.
When switching between input and output after
To drive the bus line occasionally to stabilize the potential
Bus master, and performs data transfer with the peripherals controlled by the bus master.
Bus line and, when the bus line is at an intermediate potential, raises the potential to
Connected between the voltage source and the bus line to
For pull-up, or stabilize by lowering the potential
Connected between the bus line and ground
And a resistor for down, and outputs it as the bus master, the data to pull down a bus line 3 state
An output buffer, a first delay element for delaying an output enable signal, and switching a data signal on the bus line to a high level
Timing and the output of the three-state output buffer.
Judgment timing to switch power to end of write access
And a second delay element for delaying a data signal on the bus line
And an input buffer for outputting a data signal on the bus line
Between the output enable signal and the signal from the first delay element.
OR to the 3-state output buffer that processed the OR
An interface circuit in the bus line data transfer device , comprising: an OR gate that outputs a cable signal . 6. The logic circuit according to claim 1, wherein
And an AND gate and an OR gate.
Interface circuit in the bus line data transfer device that. 7. The logic circuit according to claim 4, wherein
And a NAND gate and an AND gate
Interface circuit in the bus line data transfer device to.