KR0182981B1 - Register circuit for sampling the external signal - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION The invention described in the claims relates to a register for sampling an external signal in a semiconductor memory device.

2. The technical problem to be solved by the present invention is to provide a register circuit that can secure a setup margin regardless of the long and short setup time.

3. Summary of the Invention A register circuit for sampling an external signal comprises: a first controller connected between an input terminal and a first line and driven in response to the external signal and an external clock signal; A delay circuit unit for delaying the external clock signal for a predetermined time to secure a setup margin; A second controller connected between the first line and the output terminal and sampling in response to the signal induced in the first line and the delayed external clock signal in response to the external clock signal transitioning to the first level; The external signal may be latched after transmitting to the output terminal.

4. Important uses of the invention: It is suitably used for semiconductor memory devices.

Description

Register circuit for sampling external signals

1 is a register circuit diagram for performing a sampling operation according to the prior art.

2 is a timing diagram for the case where the margin of the setup time is sufficiently secured according to the first embodiment of the prior art.

3 is a timing diagram for a case where the margin of the setup time is not sufficiently secured according to the second embodiment of the prior art.

4 is a register circuit diagram for performing a sampling operation according to an embodiment of the present invention.

5 is a timing diagram relative to FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a gyristor circuit for sampling external signals.

In general, in synchronous memory, a signal input from the outside should be synchronously sampled by an internally generated clock and maintained as a valid signal for a certain period of time. Register circuits that perform these functions must set a margin between setup time and odd time. See the discussion below which focuses on this setup time and hold time.

1 is an input signal sampling circuit diagram mainly used in a register circuit of a semiconductor memory device.

The register circuit is used when the speeds of the internal clocks KH1 and KS1 which are synchronized with the external clock XK are relatively high. Such a register circuit has an external signal input unit 101 which provides a signal A1 to the node N1 as an input of an external signal XA input from the outside, and provides clock signals KH1 and KS1 as an external clock signal XK. A tri-state inverter 109 for providing a signal B1 corresponding to the node N2 in response to the clock signal KH1, and a signal B1 applied to the node N2. A latch circuit 110 for latching, a tri-state inverter 116 for providing a signal C1 corresponding to the node N3 in response to the clock signal KS1, and the signal C1 provided to the node N3. And a latch circuit 117 for latching the circuit. Here, the complementary signal C1 of the signal C1 is provided through an inverter 118 connected to the node N3. The tri state inverters 109 and 116 are circuits for performing a hold operation and a set-up operation, respectively.

2 is a timing diagram for the case where the margin of the setup time is sufficiently secured according to the first embodiment in the prior art.

Referring to FIGS. 1 and 2, when the signal A1 is applied to the node N1 by the external signal input unit 101 synchronized with the external signal XK, the clock signal KH1 is at a logic level high. The tri state inverter 109 transitions to the corresponding signal B1. Subsequently, the tri-state inverter 109 becomes a high impedance state because the clock signal KH1 becomes low level, but the signal B1 is maintained at the same level by the lay circuit 110. This is to no longer accept later invalid external signals. Further, while the clock signal KS1 becomes high level, the signal B1 transitions to the signal C1 by enabling the tri-state inverter 116, and after the predetermined time, the clock signal KS1 becomes low level and the latch circuit By 117, the same level is maintained. At this time, the clock signal KH1 becomes high level and the external signal XA flows into the node N2 as the signal B1 corresponding thereto.

The clock signals KS1 and KH1 are also referred to as edge trigger methods because the transitions are made at almost the same time. The clock signals KS1 and KH1 have an advantage of making setup and hold stable with only a small window.

However, if the setup time of the external signal XA is sufficiently given in the product specification (SPEC) as shown in the timing diagram shown in FIG. 2, the design is easy, but as shown in the timing diagram shown in FIG. In short, the boss is different. That is, as shown in FIG. 2, if the setup time is sufficient and the hold time is short, the setup and hold time margin is increased by increasing the time that the signal A1 is applied to the node N2 by using a delay means for the external signal input unit 101. ) Can be secured. At this time, the use of the delay means does not adversely affect the access time. Since the access time is a speed from the clock signal XK, the delay from the external signal XA to the signal B1 is independent of the access time in the range where the setup time of the external signal XA is guaranteed.

As in the timing diagram shown in FIG. 3, if the setup time is short and the hold time is long, the setup margin is insufficient. In order to solve this problem, if the speed of the external signal input unit 101 cannot be increased, it is inevitable to use a delay means for the clock signal input unit 102 to secure a setup margin. However, since the delay of the clock signal XK is an increase factor of the access time, it will never be a preferable method.

Accordingly, an object of the present invention is to provide a register circuit capable of securing a setup margin regardless of a long and short setup time.

Another object of the present invention is to provide a register circuit capable of securing a setup margin without adding delay means to a clock signal.

According to the technical idea of the present invention for achieving the above objects, a register circuit for sampling an external signal is connected between the input terminal and the first line, the first control unit is driven in response to the external signal and the external clock signal Wow; A delay circuit unit for delaying the external clock signal for a predetermined time to secure a setup margin; A second control unit connected between the first line and the output terminal and configured to sample in response to the signal induced in the first line and the delayed external clock signal in response to the external clock signal transitioning to the first level; The external signal may be latched after transmitting to the output terminal.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

4 is a circuit diagram showing a method for securing a setup margin according to an embodiment of the present invention.

As shown in FIG. 4, in the case of the address buffer, the address signals A2, Are required, but in the case of operating only one signal A1 without a complementary signal, that is, a register circuit such as the data input buffer mentioned in the prior art, reference numerals 410, 411, 424, and 425 are required. I never do that.

Referring to FIG. 4, when the clock signal KS2 is at a low level, the signal B2 applied to the node N5 is maintained at a high level regardless of a change in the level of the input signal A2. However, when the clock signal KS2 is at a high level, the signal B2 changes according to the state of the input signal A2. That is, when the clock signal KS2 is high level, if the input signal A2 is low level, the signal B2 is maintained at a high level by the PMOS transistor 405. If the input signal A2 is high level, the signal B2 is low. The level will be changed.

In the present invention, the hold operation is performed after the setup operation is completed. This will give you more setup margin. This is because the transmission time of the input signal is relatively reduced by setting up the signal A2 rather than the signal B2 by the setup clock KS2.

5 is a timing diagram with respect to FIG.

Referring to FIG. 4 and FIG. 5, the external signal XA is provided to the node N4 through the external signal input unit 101. The signal A2 applied to the node N4 is transferred to the node N5 when the clock signal KS2 transitions to a high level. Since the clock signal KS2 is at the low level before this transfer operation, the signal B2 is released to the node N5 at a high level. Of course, when the clock signal KS2 transitions to the high level, the clock signal KH2 is in the high level state, so that the B2 is immediately transmitted to the node N6. Subsequently, the clock signal KH2 in which the clock signal KS2 is inverted after a predetermined time delay by the delay means 406 becomes low level so that the signal C2 induced at the node N6 remains in the same state by the latch circuit 418. do.

When the clock signal KH2 becomes low level, the signal B2 is reset to high level. When the clock signal KH2 becomes high level, the signal C2 transitions to the low level by the signal B2.

That is, since the signal C2 is activated to a high level as a pulse signal and then reset to a low level by a clock, adding a logic gate to a subsequent circuit is advantageous to shorten the overall chip access time.

As described above, according to the present invention, there is an advantage that a setup margin can be secured regardless of a long and short setup time. In addition, the present invention has the advantage that it is possible to secure a setup margin without the addition of delay means to the clock signal.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (11)

A register circuit for sampling an external signal, comprising: a first control unit connected between an input terminal and a first line and driven in response to the external signal and an external clock signal; A delay circuit unit for delaying the external clock signal for a predetermined time to secure a setup margin; A second controller connected between the first line and the output terminal and sampling in response to the signal induced in the first line and the delayed external clock signal in response to the external clock signal transitioning to the first level; And latching the external signal after transmitting the external signal to the output terminal. The register circuit of claim 1, wherein the first control unit comprises a NAND gate configured to provide the corresponding signal to the first line using the external clock signal and the external signal as two inputs. The register circuit according to claim 1, wherein the second control unit comprises a tri state inverter for providing an inverted signal of the signal induced in the first line to the output terminal in response to the delayed external clock signal. 2. The register circuit according to claim 1, wherein the register circuit further comprises a first transistor for precharging the first line to a voltage of one level. 5. The register circuit according to claim 4, wherein the first transistor is a PMOS transistor having a gate connected to a ground level ground voltage, a source connected to a power supply voltage, and a drain connected to the first line. 5. The register circuit according to claim 4, wherein the first transistor is an NMOS transistor having a gate and a drain respectively connected to a power supply voltage, and a source connected to the first line. 5. The register circuit according to claim 4, wherein the voltage of the first level is a voltage of a high level. The register circuit of claim 1, wherein the external clock signal and the delayed external clock signal are complementary signals, and the register circuit is enabled at the same time during the latch operation. A register circuit for sampling an external signal in response to an external clock signal, the register circuit comprising: a NAND gate configured to provide two signals, the NAND gate being provided to the first line; A delay circuit unit for delaying the external clock signal for a predetermined time to secure a setup margin; A first transistor for precharging the first line to a high level voltage and a tri-state inverter providing an inverted signal of the signal induced in the first line at an output terminal in response to the delayed external clock signal; And a latch after transmitting the external signal to the output terminal in response to the external clock signal transitioning to a first level. 10. The resistor circuit of claim 9, wherein the first transistor is a PMOS transistor having a gate connected to the ground level ground voltage, a source connected to a power supply voltage, and a drain connected to the first line. . 10. The register circuit of claim 9, wherein the first transistor is an NMOS transistor having a gate and a drain respectively connected to a power supply voltage, and a source connected to the first line.