CN110008155A - Electronic device and its operating method - Google Patents
Electronic device and its operating method Download PDFInfo
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- CN110008155A CN110008155A CN201810006999.9A CN201810006999A CN110008155A CN 110008155 A CN110008155 A CN 110008155A CN 201810006999 A CN201810006999 A CN 201810006999A CN 110008155 A CN110008155 A CN 110008155A
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- integrated circuit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Abstract
A kind of electronic device.The electronic device includes the first integrated circuit and the second integrated circuit.The direction pin outbound course control signal of first integrated circuit gives the direction pin of the second integrated circuit.When direction control signal is the first logical states, the first integrated circuit is acquired the right of control.When the first integrated circuit acquires the right of control, the frequency pin of the first integrated circuit exports first frequency signal to the frequency pin of the second integrated circuit.When direction control signal is the second logical states, the second integrated circuit is acquired the right of control.When the second integrated circuit acquires the right of control, the frequency pin of the second integrated circuit exports second frequency signal to the frequency pin of the first integrated circuit.
Description
Invention field
The present invention relates to a kind of electronic device and its operating methods.
Background technique
When carrying out Collaboration between two integrated circuits, other than data transmission connecting-leg, it is also necessary to additional control
Pin specifically controls signal to transmit.In general, the quantity of pin is more, the manufacturing cost of integrated circuit is higher.In addition,
During carrying out Collaboration between two integrated circuits, one of integrated circuit serves as " main (master) " role
(main control end), and another integrated circuit serves as " falling forward (slave) " role's (controlled terminal).In well-known technique, main and servant is solid
Fixed.For example, in master and servant's framework, integrated circuit A is served as " master " role (main control end), and integrated circuit B is served as and " fallen forward
(slave) " role's (controlled terminal).Frequency signal needed for simultaneously operating is to fix to be responsible for offer by integrated circuit A, and integrate electricity
Road B receives the frequency signal of integrated circuit A to carry out Collaboration.Based on integrated circuit B cannot change from servant.
Summary of the invention
The present invention provides a kind of electronic device and its operating method, dynamically to switch control according to operational requirements
To the first integrated circuit and the second integrated circuit one of them.
The embodiment of the present invention provides a kind of electronic device.The electronic device includes the first integrated circuit and the second collection
At circuit.First integrated circuit at least has direction pin and frequency pin, wherein the direction pin of the first integrated circuit exports
Direction control signal.Second integrated circuit at least has direction pin and frequency pin.The direction pin coupling of second integrated circuit
The direction pin of the first integrated circuit is connect, signal is controlled with receiving direction.The first collection of frequency pin coupling of second integrated circuit
At the frequency pin of circuit.When direction control signal is the first logical states, the first integrated circuit is acquired the right of control.When the first collection
When acquiring the right of control at circuit, the frequency pin of the first integrated circuit exports first frequency signal to the frequency of the second integrated circuit
Pin.When direction control signal is the second logical states, the second integrated circuit is acquired the right of control.When the second integrated circuit obtains control
Temporary, the frequency pin of the second integrated circuit exports second frequency signal to the frequency pin of the first integrated circuit to system.
The embodiment of the present invention provides a kind of operating method of electronic device.Electronic device include the first integrated circuit and
Second integrated circuit.The operating method includes: the direction pin outbound course control signal by the first integrated circuit to second
The direction pin of integrated circuit；When direction control signal is the first logical states, acquired the right of control by the first integrated circuit；When
When one integrated circuit acquires the right of control, first frequency signal is exported to the second integrated circuit by the frequency pin of the first integrated circuit
Frequency pin；When direction control signal is the second logical states, acquired the right of control by the second integrated circuit；And when the second collection
When acquiring the right of control at circuit, second frequency signal is exported to the frequency of the first integrated circuit by the frequency pin of the second integrated circuit
Rate pin.
Based on above-mentioned, electronic device described in all embodiments of the present invention and its operating method can pass through direction control signal
Control is dynamically switched to the first integrated circuit and the second integrated circuit one of them.When the first integrated circuit obtains control
Temporary, the first integrated circuit can export first frequency signal to the second integrated circuit to system.When the second integrated circuit obtains control
Temporary, the second integrated circuit can export second frequency signal to the first integrated circuit.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 is circuit box (circuit block) schematic diagram according to a kind of electronic device of the embodiment of the present invention.
Fig. 2 is the flow diagram according to a kind of operating method of electronic device of the embodiment of the present invention.
Fig. 3 is the time diagram according to the signal of circuit shown in the embodiment of the present invention explanatory diagram 1.
Fig. 4 is the time diagram according to the signal of circuit shown in another embodiment of the present invention explanatory diagram 1.
Fig. 5 is the time diagram according to the signal of circuit shown in another embodiment of the present invention explanatory diagram 1.
Fig. 6 is the time diagram according to the signal of circuit shown in one more embodiment of the present invention explanatory diagram 1.
Specific embodiment
" coupling (or connection) " word used in description of the invention full text (including claim) can refer to any
Direct or indirect connection means.For example, if it is described herein that first device coupling (or connection) then should in second device
Be construed as the first device can be directly connected to the second device or the first device can by other devices or certain
It plants connection means and is coupled indirectly to the second device.In addition, all possible places, in the drawings and embodiments using identical
Component/component/step of label represents same or like part.Identical label is used in different embodiments or uses identical term
Component/component/step can be with cross-referenced related description.
Fig. 1 is shown according to a kind of circuit box (circuit block) of electronic device 100 of one embodiment of the invention
It is intended to.The electronic device 100 includes the first integrated circuit 110 and the second integrated circuit 120.First integrated circuit 110 to
There is direction pin DR, frequency pin CK, the first data pins D1 and the second data pins D2 less.Second integrated circuit 120 to
There is direction pin DR, frequency pin CK, the first data pins D1 and the second data pins D2 less.According to design requirement, first
Integrated circuit 110 may be also configured with other pins, and the second integrated circuit 120 may also be also configured with other pins.
The direction pin DR outbound course of first integrated circuit 110 controls signal DIR.The direction of second integrated circuit 120
Pin DR couples the direction pin DR of the first integrated circuit 110, controls signal DIR with receiving direction.Second integrated circuit 120
Frequency pin CK couples the frequency pin CK of the first integrated circuit 110.First data pins D1 of the second integrated circuit 120 is coupled
First data pins D1 of the first integrated circuit 110.The integrated electricity of the second data pins D2 coupling first of second integrated circuit 120
The second data pins D2 on road 110.
Fig. 2 is the flow diagram according to a kind of operating method of electronic device of one embodiment of the invention.It please refers to
Fig. 1 and Fig. 2.In step S210, the direction pin DR outbound course control signal DIR of the first integrated circuit 110 is to the second collection
At the direction pin DR of circuit 120.Step S220 judges the logical states of direction control signal DIR.When the judgement knot of step S220
When fruit indicates that direction control signal DIR is the first logical states, step S230 can be carried out.When the judging result of step S220 indicates
When direction control signal DIR is the second logical states, step S250 can be carried out.
First logical states can be determined with second logical states according to design requirement.For example, real one
It applies in example, first logical states can be logical states " 1 " (such as high logic level), and second logical states can be and patrol
It collects state " 0 " (such as low logic level).In another embodiment, first logical states can be logical states " 0 ", and described
Two logical states can be logical states " 1 ".
The initial state of the direction control signal DIR can be determined according to design requirement.For example, in an embodiment
In, the initial state of the direction control signal DIR can be the second logical states.In another embodiment, the direction controlling letter
The initial state of number DIR can be the first logical states.
When direction control signal DIR is the first logical states, the first integrated circuit 110 obtains control in step S230
Power.When the first integrated circuit 110 acquires the right of control, the frequency pin CK of the first integrated circuit 110 is exported in step S240
Frequency signal SCL gives the frequency pin CK of the second integrated circuit 120.When direction control signal DIR is the second logical states, second
Integrated circuit 120 acquires the right of control in step s 250.When the second integrated circuit 120 acquires the right of control, the second integrated circuit
120 frequency pin CK output frequency signal SCL in step S260 gives the frequency pin CK of the first integrated circuit 110.
Therefore, control can be dynamically switched to the first integrated electricity by the present embodiment by direction control signal DIR
120 one of them of road 110 and the second integrated circuit.For example, in master and servant's framework, the integrated electricity of first acquired the right of control
Road 110 can serve as " main (master) " role's (main control end), and the second integrated circuit 120 then serves as " falling forward (slave) " role
(controlled terminal).When the first integrated circuit 110 acquires the right of control, the first integrated circuit 110 can be with output frequency signal SCL to the
Two integrated circuits 120.After control is dynamically switched from the first integrated circuit 110 to the second integrated circuit 120, control is obtained
Second integrated circuit 120 of system power can change and serve as " master " role (main control end), and the first integrated circuit 110 then changes and serves as " servant "
Role's (controlled terminal).When the second integrated circuit 120 acquires the right of control, the second integrated circuit 120 can export second frequency letter
Number SCL gives the first integrated circuit 110.Based on frequency signal SCL, the first integrated circuit 110 and the second integrated circuit 120 can be into
Row cooperating.
When the first integrated circuit 110 acquires the right of control, the first data pins D1 of the first integrated circuit 110 is as first
The data output connecting pin of integrated circuit 110, and the first data pins D1 of the second integrated circuit 120 is as the second integrated circuit
120 data input pin.Therefore, the first integrated circuit 110 acquired the right of control can export main data signal MOSI to the
Two integrated circuits 120.When the first integrated circuit 110 acquires the right of control, the second data pins D2 of the first integrated circuit 110 makees
Pin is inputted for the data of the first integrated circuit 110, and the second data pins D2 of the second integrated circuit 120 is integrated as second
The data output connecting pin of circuit 120.Therefore, the control based on the first integrated circuit 110, the second integrated circuit 120 can export
Servant's data-signal MISO gives the first integrated circuit 110.
When the second integrated circuit 120 acquires the right of control, the first data pins D1 of the second integrated circuit 120 is as second
The data output connecting pin of integrated circuit 120, and the first data pins D1 of the first integrated circuit 110 is as the first integrated circuit
110 data input pin.Therefore, the second integrated circuit 120 acquired the right of control can export main data signal MOSI to the
One integrated circuit 110.When the second integrated circuit 120 acquires the right of control, the second data pins D2 of the second integrated circuit 120 makees
Pin is inputted for the data of the second integrated circuit 120, and the second data pins D2 of the first integrated circuit 110 is integrated as first
The data output connecting pin of circuit 110.Therefore, the control based on the second integrated circuit 120, the first integrated circuit 110 can export
Servant's data-signal MISO gives the second integrated circuit 120.
In the present embodiment, " when the signal of frequency pin CK is third logical states, the signal of the first data pins D1 from
4th logical states transition to the 5th logical states " is defined as an initial signal.The initial signal indicates between data transfer period
Beginning." when the signal of frequency pin CK is third logical states, the signal of the first data pins D1 is from the 5th logical states transition
To the 4th logical states " it is defined as an end signal.The end signal indicates the end between data transfer period.The third
Logical states, the 4th logical states and the 5th logical states can be set according to design requirement.For example, in the present embodiment, institute
Stating third logical states can be logical states " 1 " (such as high logic level), and the 4th logical states can be logical states " 1 ", and
5th logical states can be logical states " 0 " (such as low logic level).In another embodiment, the third logical states can
To be logical states " 0 ", the 4th logical states can be logical states " 0 ", and the 5th logical states can be logical states " 1 ".
Fig. 3 is the time diagram according to the signal of circuit shown in one embodiment of the invention explanatory diagram 1.Please refer to Fig. 1
With Fig. 3.It in the embodiment shown in fig. 3, " is logical states 1 (such as high logic level) in the frequency signal SCL of frequency pin CK
When, the main data signal MOSI of the first data pins D1 is from 1 transition of logical states to logical states 0 (such as low logic level) " determined
Justice be an initial signal STA, and " frequency signal SCL be logical states 1 when, main data signal MOSI from 0 transition of logical states to
Logical states 1 " are defined as an end signal STP.The initial signal STA indicates the beginning between data transfer period, and described
End signal STP indicates the end between data transfer period.
In the embodiment shown in fig. 3, it is that logical states " 0 " are (such as low that the initial state of the direction control signal DIR, which is assumed,
Logic level).When direction control signal DIR is logical states " 0 ", the second integrated circuit 120 is acquired the right of control.When second integrated
When circuit 120 acquires the right of control (that is, when direction control signal DIR is logical states " 0 "), the second integrated circuit 120 can be defeated
Frequency signal SCL can export initial signal STA to the first collection to the first integrated circuit 110 and the second integrated circuit 120 out
At circuit 110, with DP1 during opening a data transmission.Between data transfer period in DP1, the pulse width of frequency signal SCL
(time for continuing high logic level is long) or trough width (time for continuing low logic level is long) are less than door width, wherein institute
Stating door width can determine according to design requirement.Between data transfer period in DP1, the second integrated circuit 120 can be exported
Main data signal MOSI gives the first integrated circuit 110, and the first integrated circuit 110 can export servant's data-signal MISO to the
Two integrated circuits 120.Between data transfer period in DP1, main data signal MOSI can when frequency signal SCL is low logic level
To carry out transition (transition), and main data signal MOSI frequency signal SCL be high logic level when without turn
State.The operation of servant's data-signal MISO is referred to the related description of main data signal MOSI to analogize.Second integrated circuit 120
The first integrated circuit 110 can be given with end of output signal STP, to terminate DP1 between data transfer period.
Direction control signal DIR can be pulled up to logical states 1 (such as high logic level) by the first integrated circuit 110, with
Just control is fetched from the second integrated circuit 120.When the first integrated circuit 110 acquires the right of control (that is, when direction controlling is believed
When number DIR is logical states " 1 "), the first integrated circuit 110 can give the second integrated circuit 120 with output frequency signal SCL, and
First integrated circuit 110 can export initial signal STA to the second integrated circuit 120, during opening a data transmission
DP2.Between data transfer period in DP2, the first integrated circuit 110 can export main data signal MOSI to the second integrated circuit
120, and the second integrated circuit 120 can export servant's data-signal MISO to the first integrated circuit 110.Between data transfer period
The operation of frequency signal SCL, main data signal MOSI and servant's data-signal MISO in DP2 are referred between data transfer period
The related description of DP1 is analogized.First integrated circuit 110 can give the second integrated circuit 120 with end of output signal STP, with knot
DP2 during beam data transmits.
It is assumed herein that (such as DP1 or data pass frequency signal SCL between data transfer period shown in Fig. 3 between data transfer period
Defeated period DP2) less than one door width of pulse width (or trough width).The door width can be according to design requirement
To determine.In the embodiment shown in fig. 1, " when the first integrated circuit 110 acquires the right of control, the pulse width of frequency signal SCL
(or trough width) is greater than door width " it is defined as a reset signal.First integrated circuit 110 can pass through the resetting
Signal resets the second integrated circuit 120.Therefore, the first integrated circuit 110 (the second integrated circuit 120) can save additional
Reset pin.
Fig. 4 is the time diagram according to the signal of circuit shown in another embodiment of the present invention explanatory diagram 1.Please refer to figure
1 and Fig. 4.In the embodiment shown in fig. 4, " when the first integrated circuit 110 acquires the right of control (that is, work as direction control signal DIR
For logical states " 1 " when), frequency signal SCL and/or main data signal MOSI are pulled down and are continued above the door width (example
Such as more than 1 millisecond) " it is defined as a reset signal RST.First integrated circuit 110 can by the reset signal RST come
Reset the second integrated circuit 120.
Fig. 5 is the time diagram according to the signal of circuit shown in another embodiment of the present invention explanatory diagram 1.Please refer to figure
1 and Fig. 5.In the embodiment shown in fig. 5, " the pulse width PW of direction control signal DIR is fallen in a width range " is determined
Justice is interruption (interrupt) signal INT.The width range can be determined according to design requirement.For example, the width
Degree range can be 1 microsecond to 10 microseconds.First integrated circuit 110 can notify the second integrated circuit by interrupt signal INT
One interrupt request.Therefore, the first integrated circuit 110 (the second integrated circuit 120) can save additional interrupt pins.
Fig. 6 is the time diagram according to the signal of circuit shown in one more embodiment of the present invention explanatory diagram 1.Please refer to figure
1 and Fig. 6.It is assumed herein that the first integrated circuit 110 has an interrupt flag (or interrupting buffer).Implementation shown in Fig. 6
Example in, when the second integrated circuit 120 is acquired the right of control from the first integrated circuit 110 (that is, direction control signal DIR be from
Logical states " 1 " transition to logical states " 0 " afterwards), the second integrated circuit 120 can first pass through main data signal MOSI require read first
The interrupt flag (or interrupting buffer) of integrated circuit 110.Based on requirement/control of the second integrated circuit 120, first
Integrated circuit 110 can be returned to the content of the interrupt flag (or interrupting buffer) by servant's data-signal MISO
Second integrated circuit 120.According to the content of the interrupt flag (or interrupting buffer), the second integrated circuit 120 can be obtained
Knowing the first integrated circuit, whether there is or not propose interrupt request.Therefore, the first integrated circuit 110 (the second integrated circuit 120) can save
Additional interrupt pins.
It is worth noting that, in different application situations, the first integrated circuit 110 and/or the second integrated circuit 120
Correlation function can use general programming language (programming languages, such as C or C++), hardware description language
(hardware description languages, such as Verilog HDL or VHDL) or other suitable programming languages come
It is embodied as software, firmware or hardware.The programming language that the correlation function can be performed can be arranged to any of calculating
Device can access media (computer-accessible medias), such as tape (magnetic tapes), semiconductor
(semiconductors) memory, disk (magnetic disks) or CD (compact disks, for example, CD-ROM or
DVD-ROM), or internet (Internet) can be passed through, wire communication (wired communication), wirelessly communicated
(wireless communication) or other communication medias transmit the programming language.The programming language can be stored
In accessing in media for calculator, in order to which the volume of the software (or firmware) is accessed/executed by the processor of calculator
Journey code (programming codes).For hardware realization, one or more controllers, special are answered at microcontroller, microprocessor
With integrated circuit (Application-specific integrated circuit, ASIC), digital signal processor
(digital signal processor, DSP), field can programmed logic gate array (Field Programmable Gate
Array, FPGA) and/or other processing units in various logic block, module and circuit can be used to realize or execute sheet
Function described in literary embodiment.In addition, apparatus and method of the present invention can be realized by the combination of hardware and software.
In conclusion electronic device 100 and its operating method described in implementations described above can pass through direction control signal
DIR and control is dynamically switched to 120 one of them of the first integrated circuit 110 and the second integrated circuit.When first integrated
When circuit 110 acquires the right of control, the first integrated circuit 110 can give the second integrated circuit 120 with output frequency signal SCL, and
First integrated circuit 110 can export main data signal MOSI to the second integrated circuit 120.Based on the first collection acquired the right of control
At the control of circuit 110, the second integrated circuit 120 can export servant's data-signal MISO to the first integrated circuit 110.When second
When integrated circuit 120 acquires the right of control, the second integrated circuit 120 can give the first integrated circuit 110 with output frequency signal SCL,
And second integrated circuit 120 can export main data signal MOSI to the first integrated circuit 110.Based on acquired the right of control
The control of two integrated circuits 120, the first integrated circuit 110 can export servant's data-signal MISO to the second integrated circuit 120.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any those skilled in the art
Member, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore protection scope of the present invention is when view
Subject to appended claims institute defender.
Claims (14)
1. a kind of electronic device, comprising:
First integrated circuit at least has direction pin and frequency pin, wherein the direction of first integrated circuit connects
Foot outbound course controls signal；And
Second integrated circuit at least has direction pin and frequency pin, wherein the direction of second integrated circuit connects
Foot couples the direction pin of first integrated circuit to receive the direction control signal, second integrated circuit
The frequency pin couples the frequency pin of first integrated circuit,
Wherein when the direction control signal be the first logical states when described in the first integrated circuit acquire the right of control, when described first
The frequency pin of first integrated circuit described in when integrated circuit obtains the control exports first frequency signal to described
The frequency pin of second integrated circuit, when the direction control signal be the second logical states when described in the second integrated circuit take
The control, and when second integrated circuit obtains the control described in the second integrated circuit the frequency
Pin exports second frequency signal to the frequency pin of first integrated circuit.
2. electronic device as described in claim 1, wherein the initial state of the direction control signal is second logical states.
3. electronic device as described in claim 1, wherein first integrated circuit also has the first data pins and second
Data pins, second integrated circuit also have the first data pins and the second data pins, second integrated circuit
First data pins couple first data pins of first integrated circuit, second integrated circuit it is described
Second data pins couple second data pins of first integrated circuit；
Wherein when first integrated circuit obtains the control, first data pins of first integrated circuit
As the data output connecting pin of first integrated circuit, described in first data pins conduct of second integrated circuit
The data of second integrated circuit input pin, and second data pins of first integrated circuit are integrated as described first
The data of circuit input pin, and second data pins of second integrated circuit are as second integrated circuit
Data output connecting pin；And
Wherein when second integrated circuit obtains the control, first data pins of second integrated circuit
As the data output connecting pin of second integrated circuit, described in first data pins conduct of first integrated circuit
The data of first integrated circuit input pin, and second data pins of second integrated circuit are integrated as described second
The data of circuit input pin, and second data pins of first integrated circuit are as first integrated circuit
Data output connecting pin.
4. electronic device as claimed in claim 3, wherein " being third logical states when institute in the signal of the multiple frequency pin
The signals of multiple first data pins is stated from the 4th logical states transition to the 5th logical states " it is defined as initial signal, described
Beginning signal indicates the beginning between data transfer period, " described in when the signal of the multiple frequency pin is the third logical states
The signal of multiple first data pins is from the 5th logical states transition to the 4th logical states " it is defined as end signal,
The end signal indicates the end between the data transfer period.
5. electronic device as described in claim 1, wherein pulse width of the first frequency signal between data transfer period
Less than door width, " when first integrated circuit obtains the control, the pulse of the first frequency signal is wide
Degree is greater than the door width " it is defined as reset signal, first integrated circuit passes through described in reset signal resetting
Second integrated circuit.
6. electronic device as described in claim 1, wherein " pulse width of the direction control signal falls within width range
It is interior " it is defined as interrupt signal, first integrated circuit notifies second integrated circuit to interrupt by the interrupt signal
It is required that.
7. electronic device as described in claim 1, wherein first integrated circuit has interrupt flag, when second collection
When obtaining the control from first integrated circuit at circuit, second integrated circuit reads first integrated circuit
The interrupt flag with learn first integrated circuit whether there is or not propose interrupt request.
8. a kind of operating method of electronic device, wherein the electronic device includes the first integrated circuit and the second integrated electricity
Road, the operating method include:
The direction pin of second integrated circuit is given by the direction pin outbound course control signal of first integrated circuit；
When the direction control signal is the first logical states, acquired the right of control by first integrated circuit；
When first integrated circuit obtains the control, by the first frequency of frequency pin output of first integrated circuit
Rate signal gives the frequency pin of second integrated circuit；
When the direction control signal is the second logical states, the control is obtained by second integrated circuit；And
When second integrated circuit obtains the control, by the frequency pin output the of second integrated circuit
Two frequency signals give the frequency pin of first integrated circuit.
9. operating method as claimed in claim 8, wherein the initial state of the direction control signal is second logical states.
10. operating method as claimed in claim 8, wherein the first data pins coupling of second integrated circuit described the
First data pins of one integrated circuit, the second data pins of second integrated circuit couple first integrated circuit
Second data pins；
When first integrated circuit obtains the control, described in the first data pins conduct of first integrated circuit
First data pins of the data output connecting pin of first integrated circuit, second integrated circuit are integrated as described second
The data of circuit input pin, number of second data pins of first integrated circuit as first integrated circuit
According to input pin, and second data pins of second integrated circuit are exported as the data of second integrated circuit
Pin；And
When second integrated circuit obtains the control, the first data pins conduct of second integrated circuit
The data output connecting pin of second integrated circuit, first data pins of first integrated circuit are as described first
The data of integrated circuit input pin, and second data pins of second integrated circuit are as second integrated circuit
Data input pin, and data of second data pins of first integrated circuit as first integrated circuit
Output connecting pin.
11. operating method as claimed in claim 10, further includes:
It will " when the signal of the multiple frequency pin is third logical states, the signal of the multiple first data pins be from the 4th
Logical states transition is to the 5th logical states " it is defined as initial signal, wherein the initial signal indicates the beginning between data transfer period；
And
Will " when the signal of the multiple frequency pin is the third logical states signal of the multiple first data pins from
The 5th logical states transition is to the 4th logical states " it is defined as end signal, wherein the end signal indicates the number
According to the end during transmission.
12. operating method as claimed in claim 8, wherein pulse width of the first frequency signal between data transfer period
Less than door width, the operating method further include:
By " when first integrated circuit obtains the control, the pulse width of the first frequency signal is greater than
The door width " is defined as reset signal, wherein first integrated circuit passes through reset signal resetting described second
Integrated circuit.
13. operating method as claimed in claim 8, further includes:
" pulse width of the direction control signal is fallen in width range " is defined as interrupt signal, wherein first collection
The second integrated circuit interrupt request is notified by the interrupt signal at circuit.
14. operating method as claimed in claim 8, wherein first integrated circuit has interrupt flag, the operation side
Method further include:
When second integrated circuit obtains the control from first integrated circuit, read by second integrated circuit
Taking the interrupt flag of first integrated circuit, whether there is or not propose interrupt request to learn first integrated circuit.
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| CN201810006999.9A CN110008155B (en) | 2018-01-04 | 2018-01-04 | Electronic device and operation method thereof |
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| US20080201507A1 (en) * | 2007-02-20 | 2008-08-21 | Gerfried Krampl | Bus system and methods of operation thereof |
| CN101727801A (en) * | 2008-10-31 | 2010-06-09 | 扬智科技股份有限公司 | Integrated circuit for controlling operation of displaying module and first circuit module with shared connecting pin |
| WO2011092548A1 (en) * | 2010-01-26 | 2011-08-04 | Freescale Semiconductor, Inc. | Integrated circuit device and method of using combinatorial logic in a data processing circuit |
| CN102237873A (en) * | 2010-05-05 | 2011-11-09 | 立锜科技股份有限公司 | Circuit and method for setting frequency of IC (integrated circuit) |
| CN104808132A (en) * | 2014-01-29 | 2015-07-29 | 新唐科技股份有限公司 | Operation recording circuit applied to integrated circuit and operation method thereof |
| CN106612065A (en) * | 2015-10-17 | 2017-05-03 | 英特希尔美国公司 | Enhanced fault reporting in voltage regulators |
| US20170168978A1 (en) * | 2015-12-10 | 2017-06-15 | Qualcomm Incorporated | Enhanced serial peripheral interface with hardware flow-control |
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