TWI637269B - Electronic apparatus and operation method thereof - Google Patents

Abstract

An electronic device. The electronic device includes a first integrated circuit and a second integrated circuit. The direction pin of the first integrated circuit outputs a direction control signal to the direction pin of the second integrated circuit. When the direction control signal is in the first logic state, the first integrated circuit takes control. When the first integrated circuit obtains the control right, the clock pin of the first integrated circuit outputs the first clock signal to the clock pin of the second integrated circuit. When the direction control signal is in the second logic state, the second integrated circuit takes control. When the second integrated circuit obtains the control right, the clock pin of the second integrated circuit outputs the second clock signal to the clock pin of the first integrated circuit.

Description

Electronic device and method of operating same

The present invention relates to an electronic device and a method of operating the same.

In conjunction with the two integrated circuits, in addition to the data transfer pins, additional control pins are required to deliver specific control signals. In general, the more the number of pins, the higher the manufacturing cost of the integrated circuit. In addition, in the process of cooperative operation between two integrated circuits, one of the integrated circuits functions as the "master" (master), and the other integrated circuit acts as the "slave". (controlled terminal). In the prior art, the master and the servant are fixed. For example, in the master servant architecture, the integrated circuit A assumes the "master" role (the master), and the integrated circuit B acts as the "slave" role (the host). The clock signal required for the synchronous operation is fixedly provided by the integrated circuit A, and the integrated circuit B receives the clock signal of the integrated circuit A for cooperative operation. The integrated circuit B cannot be changed from the servant to the main.

The present invention provides an electronic device and an operating method thereof for dynamically switching control to one of a first integrated circuit and a second integrated circuit in accordance with operational requirements.

Embodiments of the present invention provide an electronic device. The electronic device includes a first integrated circuit and a second integrated circuit. The first integrated circuit has at least a direction pin and a clock pin, wherein the direction pin of the first integrated circuit outputs a direction control signal. The second integrated circuit has at least a directional pin and a clock pin. The direction pin of the second integrated circuit is coupled to the direction pin of the first integrated circuit to receive the direction control signal. The clock pin of the second integrated circuit is coupled to the clock pin of the first integrated circuit. When the direction control signal is in the first logic state, the first integrated circuit takes control. When the first integrated circuit obtains the control right, the clock pin of the first integrated circuit outputs the first clock signal to the clock pin of the second integrated circuit. When the direction control signal is in the second logic state, the second integrated circuit takes control. When the second integrated circuit obtains the control right, the clock pin of the second integrated circuit outputs the second clock signal to the clock pin of the first integrated circuit.

Embodiments of the present invention provide a method of operating an electronic device. The electronic device includes a first integrated circuit and a second integrated circuit. The operation method includes: outputting a direction control signal to a direction pin of the second integrated circuit by a direction pin of the first integrated circuit; and obtaining control by the first integrated circuit when the direction control signal is in a first logic state; When the first integrated circuit obtains the control right, the clock pin of the first integrated circuit outputs the first clock signal to the clock pin of the second integrated circuit; when the direction control signal is the second logic In the state, the control is obtained by the second integrated circuit; and when the second integrated circuit obtains the control right, when the second pulse of the second integrated circuit outputs the second clock signal to the first integrated circuit Pulse pin.

Based on the above, the electronic device and the operating method thereof according to the embodiments of the present invention can dynamically switch the control right to one of the first integrated circuit and the second integrated circuit by using the direction control signal. When the first integrated circuit obtains the control right, the first integrated circuit can output the first clock signal to the second integrated circuit. When the second integrated circuit obtains the control right, the second integrated circuit can output the second clock signal to the first integrated circuit.

The above described features and advantages of the invention will be apparent from the following description.

The term "coupled (or connected)" as used throughout the specification (including the scope of the claims) may be used in any direct or indirect connection. For example, if the first device is described as being coupled (or connected) to the second device, it should be construed that the first device can be directly connected to the second device, or the first device can be A connection means is indirectly connected to the second device. In addition, wherever possible, the elements and/ Elements/components/steps that use the same reference numbers or use the same terms in different embodiments may refer to the related description.

FIG. 1 is a schematic diagram of a circuit block of an electronic device 100 according to an embodiment of the invention. The electronic device 100 includes a first integrated circuit 110 and a second integrated circuit 120. The first integrated circuit 110 has at least a direction pin DR, a clock pin CK, a first data pin D1 and a second data pin D2. The second integrated circuit 120 has at least a direction pin DR, a clock pin CK, a first data pin D1 and a second data pin D2. According to design requirements, the first integrated circuit 110 may also be configured with other pins, and the second integrated circuit 120 may also be configured with other pins.

The direction pin DR of the first integrated circuit 110 outputs a direction control signal DIR. The direction pin DR of the second integrated circuit 120 is coupled to the direction pin DR of the first integrated circuit 110 to receive the direction control signal DIR. The clock pin CK of the second integrated circuit 120 is coupled to the clock pin CK of the first integrated circuit 110. The first data pin D1 of the second integrated circuit 120 is coupled to the first data pin D1 of the first integrated circuit 110. The second data pin D2 of the second integrated circuit 120 is coupled to the second data pin D2 of the first integrated circuit 110.

FIG. 2 is a schematic flow chart of a method of operating an electronic device according to an embodiment of the invention. Please refer to FIG. 1 and FIG. 2 . In step S210, the direction pin DR of the first integrated circuit 110 outputs the direction control signal DIR to the direction pin DR of the second integrated circuit 120. Step S220 determines the logic state of the direction control signal DIR. When the result of the determination in step S220 indicates that the direction control signal DIR is in the first logic state, step S230 is performed. When the result of the determination in step S220 indicates that the direction control signal DIR is in the second logic state, step S250 is performed.

The first logic state and the second logic state may be determined according to design requirements. For example, in an embodiment, the first logic state may be a logic state "1" (eg, a high logic level), and the second logic state may be a logic state "0" (eg, a low logic level) Bit). In another embodiment, the first logic state may be a logic state "0", and the second logic state may be a logic state "1".

The initial state of the direction control signal DIR can be determined according to design requirements. For example, in an embodiment, the initial state of the direction control signal DIR may be the second logic state. In another embodiment, the initial state of the direction control signal DIR may be the first logic state.

When the direction control signal DIR is in the first logic state, the first integrated circuit 110 acquires the control right in step S230. When the first integrated circuit 110 obtains the control right, the clock pin CK of the first integrated circuit 110 outputs the clock signal SCL to the clock pin CK of the second integrated circuit 120 in step S240. When the direction control signal DIR is in the second logic state, the second integrated circuit 120 obtains the control right in step S250. When the second integrated circuit 120 obtains the control right, the clock pin CK of the second integrated circuit 120 outputs the clock signal SCL to the clock pin CK of the first integrated circuit 110 in step S260.

Therefore, in this embodiment, the control right can be dynamically switched to one of the first integrated circuit 110 and the second integrated circuit 120 by the direction control signal DIR. For example, in the master servant architecture, the first integrated circuit 110 that takes control can serve as the "master" role (the master), and the second integrated circuit 120 acts as the "slave". Role (the host). When the first integrated circuit 110 obtains the control right, the first integrated circuit 110 can output the clock signal SCL to the second integrated circuit 120. After the control right is dynamically switched from the first integrated circuit 110 to the second integrated circuit 120, the second integrated circuit 120 that obtains the control right can be changed to the "main" role (the master), and the first product The body circuit 110 is changed to the "servant" role (controlled terminal). When the second integrated circuit 120 obtains the control right, the second integrated circuit 120 can output the second clock signal SCL to the first integrated circuit 110. Based on the clock signal SCL, the first integrated circuit 110 and the second integrated circuit 120 can perform cooperative operation.

When the first integrated circuit 110 obtains the control right, the first data pin D1 of the first integrated circuit 110 serves as the data output pin of the first integrated circuit 110, and the first data of the second integrated circuit 120 is connected. The foot D1 serves as a data input pin of the second integrated circuit 120. Therefore, the first integrated circuit 110 that obtains the control can output the main data signal MOSI to the second integrated circuit 120. When the first integrated circuit 110 obtains the control right, the second data pin D2 of the first integrated circuit 110 serves as the data input pin of the first integrated circuit 110, and the second data of the second integrated circuit 120 is connected. The foot D2 serves as a data output pin of the second integrated circuit 120. Therefore, based on the control of the first integrated circuit 110, the second integrated circuit 120 can output the servant signal MISO to the first integrated circuit 110.

When the second integrated circuit 120 obtains the control right, the first data pin D1 of the second integrated circuit 120 serves as the data output pin of the second integrated circuit 120, and the first data of the first integrated circuit 110 is connected. The foot D1 serves as a data input pin of the first integrated circuit 110. Therefore, the second integrated circuit 120 that obtains the control can output the main data signal MOSI to the first integrated circuit 110. When the second integrated circuit 120 obtains the control right, the second data pin D2 of the second integrated circuit 120 serves as the data input pin of the second integrated circuit 120, and the second data of the first integrated circuit 110 is connected. The foot D2 serves as a data output pin of the first integrated circuit 110. Therefore, based on the control of the second integrated circuit 120, the first integrated circuit 110 can output the servant signal MISO to the second integrated circuit 120.

In this embodiment, "when the signal of the clock pin CK is in the third logic state, the signal of the first data pin D1 transitions from the fourth logic state to the fifth logic state" is defined as a start signal. . The start signal indicates the beginning of the data transmission period. "When the signal of the clock pin CK is in the third logic state, the signal of the first data pin D1 transitions from the fifth logic state to the fourth logic state" is defined as an end signal. The end signal indicates the end of the data transmission period. The third logic state, the fourth logic state, and the fifth logic state may be set according to design requirements. For example, in this embodiment, the third logic state may be a logic state "1" (eg, a high logic level), the fourth logic state may be a logic state "1", and the fifth The logic state can be a logic state of "0" (eg, a low logic level). In another embodiment, the third logic state may be a logic state "0", the fourth logic state may be a logic state "0", and the fifth logic state may be a logic state "1".

3 is a timing diagram illustrating signals of the circuit of FIG. 1 in accordance with an embodiment of the present invention. Please refer to FIG. 1 and FIG. 3. In the embodiment shown in FIG. 3, "when the clock signal SCL of the clock pin CK is in the logic state 1 (for example, the high logic level), the main data signal MOSI of the first data pin D1 is changed from the logic state 1 State to logic state 0 (eg, low logic level) is defined as a start signal STA, and "when the clock signal SCL is logic state 1, the main data signal MOSI transitions from logic state 0 to logic state 1" It is defined as an end signal STP. The start signal STA indicates the start of the data transmission period, and the end signal STP indicates the end of the data transmission period.

In the embodiment shown in FIG. 3, the initial state of the direction control signal DIR is assumed to be a logic state of "0" (eg, a low logic level). When the direction control signal DIR is in the logic state "0", the second integrated circuit 120 takes control. When the second integrated circuit 120 obtains the control right (that is, when the direction control signal DIR is in the logic state "0"), the second integrated circuit 120 can output the clock signal SCL to the first integrated circuit 110, and The second integrated circuit 120 can output the start signal STA to the first integrated circuit 110 to turn on a data transmission period DP1. During the data transmission period DP1, the pulse width of the clock signal SCL (the duration of the continuous high logic level) or the valley width (the length of the continuous low logic level) is less than the threshold width, wherein the threshold width can be designed according to the design requirements. To decide. During the data transmission period DP1, the second integrated circuit 120 can output the main data signal MOSI to the first integrated circuit 110, and the first integrated circuit 110 can output the servant data signal MISO to the second integrated circuit 120. During the data transmission period DP1, the main data signal MOSI can be transitioned when the clock signal SCL is at a low logic level, and the main data signal MOSI does not change when the clock signal SCL is at a high logic level. . The operation of the servant data signal MISO can be analogized with the relevant description of the main data signal MOSI. The second integrated circuit 120 can output the end signal STP to the first integrated circuit 110 to end the data transfer period DP1.

The first integrated circuit 110 can pull the direction control signal DIR to a logic state 1 (eg, a high logic level) to retrieve control from the second integrated circuit 120. When the first integrated circuit 110 obtains the control right (that is, when the direction control signal DIR is in the logic state "1"), the first integrated circuit 110 can output the clock signal SCL to the second integrated circuit 120, and An integrated circuit 110 can output a start signal STA to the second integrated circuit 120 to turn on a data transmission period DP2. In the data transmission period DP2, the first integrated circuit 110 can output the main data signal MOSI to the second integrated circuit 120, and the second integrated circuit 120 can output the servant information signal MISO to the first integrated circuit 110. The operation of the clock signal SCL, the main data signal MOSI and the servant data signal MISO in the DP2 during data transmission can be analogized with reference to the relevant description of the DP1 during the data transmission period. The first integrated circuit 110 can output the end signal STP to the second integrated circuit 120 to end the data transfer period DP2.

It is assumed here that the pulse width (or trough width) of the clock signal SCL during data transmission (for example, DP1 during data transmission or DP2 during data transmission shown in FIG. 3) is less than one threshold width. The threshold width can be determined according to design requirements. In the embodiment shown in FIG. 1, "when the first integrated circuit 110 takes control, the pulse width (or valley width) of the clock signal SCL is greater than the threshold width" is defined as a reset signal. The first integrated circuit 110 can reset the second integrated circuit 120 by the reset signal. Thereby, the first integrated circuit 110 (the second integrated circuit 120) can dispense with an additional reset pin.

4 is a timing diagram illustrating signals of the circuit of FIG. 1 in accordance with another embodiment of the present invention. Please refer to FIG. 1 and FIG. 4. In the embodiment shown in FIG. 4, "When the first integrated circuit 110 obtains the control right (that is, when the direction control signal DIR is in the logic state "1"), the clock signal SCL and/or the main data signal MOSI are Pulling down and continuing beyond the threshold width (eg, more than 1 millisecond) is defined as a reset signal RST. The first integrated circuit 110 can reset the second integrated circuit 120 by the reset signal RST.

FIG. 5 is a timing diagram illustrating signals of the circuit of FIG. 1 in accordance with still another embodiment of the present invention. Please refer to FIG. 1 and FIG. 5. In the embodiment shown in FIG. 5, "the pulse width PW of the direction control signal DIR falls within a width range" is defined as an interrupt signal INT. The width range can be determined according to design requirements. For example, the width may range from 1 microsecond to 10 microseconds. The first integrated circuit 110 can notify the second integrated circuit of an interrupt request by the interrupt signal INT. Thereby, the first integrated circuit 110 (second integrated circuit 120) can dispense with additional interrupt pins.

6 is a timing diagram illustrating signals of the circuit of FIG. 1 in accordance with a further embodiment of the present invention. Please refer to FIG. 1 and FIG. 6. It is assumed here that the first integrated circuit 110 has an interrupt flag (or an interrupt register). In the embodiment shown in FIG. 6, when the second integrated circuit 120 obtains control from the first integrated circuit 110 (that is, when the direction control signal DIR is changed from the logic state "1" to the logic state "0" Thereafter, the second integrated circuit 120 first requests the interrupt flag (or interrupt register) of the first integrated circuit 110 by the main data signal MOSI. Based on the request/control of the second integrated circuit 120, the first integrated circuit 110 can transmit the content of the interrupt flag (or the interrupt register) to the second integrated circuit by using the servant signal MISO. 120. According to the content of the interrupt flag (or interrupt register), the second integrated circuit 120 can know whether the first integrated circuit has an interrupt request. Thereby, the first integrated circuit 110 (second integrated circuit 120) can dispense with additional interrupt pins.

It should be noted that in different application scenarios, the related functions of the first integrated circuit 110 and/or the second integrated circuit 120 can utilize a general programming language (such as C or C++), a hardware description language. (hardware description languages, such as Verilog HDL or VHDL) or other suitable programming language to implement as software, firmware or hardware. The programming language that can perform the related functions can be arranged as any known computer-accessible media, such as magnetic tapes, semiconductors, magnetic disks, or optical disks. (compact disks, such as CD-ROM or DVD-ROM), or the programming language can be transmitted over the Internet, wired communication, wireless communication, or other communication medium. The programming language can be stored in an accessible medium of the computer such that the software (or firmware) programming codes are accessed/executed by the processor of the computer. For hardware implementation, one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable Various logic blocks, modules, and circuits in a Field Programmable Gate Array (FPGA) and/or other processing unit may be used to implement or perform the functions described in this embodiment. Additionally, the apparatus and method of the present invention can be implemented by a combination of hardware and software.

In summary, the electronic device 100 and the operating method thereof according to the above embodiments can dynamically switch to one of the first integrated circuit 110 and the second integrated circuit 120 by the direction control signal DIR. When the first integrated circuit 110 obtains the control right, the first integrated circuit 110 can output the clock signal SCL to the second integrated circuit 120, and the first integrated circuit 110 can output the main data signal MOSI to the second integrated body. Circuit 120. Based on the control of the first integrated circuit 110 that obtains the control, the second integrated circuit 120 can output the servant signal MISO to the first integrated circuit 110. When the second integrated circuit 120 obtains the control right, the second integrated circuit 120 can output the clock signal SCL to the first integrated circuit 110, and the second integrated circuit 120 can output the main data signal MOSI to the first integrated body. Circuit 110. Based on the control of the second integrated circuit 120 that obtains the control, the first integrated circuit 110 can output the servant signal MISO to the second integrated circuit 120.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧Electronic devices

110‧‧‧First integrated circuit

120‧‧‧Second integrated circuit

CK‧‧‧ clock pin

D1‧‧‧First data pin

D2‧‧‧Second data pin

DIR‧‧‧ direction control signal

DP1, DP2‧‧‧ data transmission period

DR‧‧‧ direction pin

INT‧‧‧ interrupt signal

MISO‧‧‧ servant information signal

MOSI‧‧‧ Master Data Signal

PW‧‧‧ pulse width

RST‧‧‧Reset signal

S210～S260‧‧‧Steps

SCL‧‧‧ clock signal

STA‧‧‧ start signal

STP‧‧‧End signal

FIG. 1 is a schematic diagram of a circuit block of an electronic device according to an embodiment of the invention. FIG. 2 is a schematic flow chart of a method of operating an electronic device according to an embodiment of the invention. 3 is a timing diagram illustrating signals of the circuit of FIG. 1 in accordance with an embodiment of the present invention. 4 is a timing diagram illustrating signals of the circuit of FIG. 1 in accordance with another embodiment of the present invention. FIG. 5 is a timing diagram illustrating signals of the circuit of FIG. 1 in accordance with still another embodiment of the present invention. 6 is a timing diagram illustrating signals of the circuit of FIG. 1 in accordance with a further embodiment of the present invention.

Claims (14)

An electronic device comprising: a first integrated circuit having at least one direction pin and one clock pin, wherein the direction pin of the first integrated circuit outputs a direction control signal; and a second integrated circuit Having at least one direction pin and one clock pin, wherein the direction pin of the second integrated circuit is coupled to the direction pin of the first integrated circuit to receive the direction control signal, the second integrated body The clock pin of the circuit is coupled to the clock pin of the first integrated circuit, wherein the first integrated circuit obtains a control right when the direction control signal is a first logic state, when the first When the integrated circuit obtains the control right, the clock pin of the first integrated circuit outputs a first clock signal to the clock pin of the second integrated circuit, and when the direction control signal is a second In the logic state, the second integrated circuit obtains the control right, and when the second integrated circuit obtains the control right, the clock pin of the second integrated circuit outputs a second clock signal to the first The clock pin of the integrated circuit. The electronic device of claim 1, wherein the initial state of the direction control signal is the second logic state. The electronic device of claim 1, wherein the first integrated circuit further has a first data pin and a second data pin, and the second integrated circuit further has a first data pin. The first data pin of the second integrated circuit is coupled to the first data pin of the first integrated circuit, and the second data pin of the second integrated circuit is coupled to a second data pin. The second data pin of the first integrated circuit is coupled to the second integrated circuit; wherein the first integrated circuit of the first integrated circuit serves as the first integrated circuit when the first integrated circuit obtains the control a data output pin, the first data pin of the second integrated circuit is used as a data input pin of the second integrated circuit, and the second data pin of the first integrated circuit is used as the first a data input pin of the integrated circuit, wherein the second data pin of the second integrated circuit serves as a data output pin of the second integrated circuit; and wherein the second integrated circuit obtains the When the control is performed, the first data pin of the second integrated circuit serves as the second integrated circuit a data output pin, the first data pin of the first integrated circuit is used as a data input pin of the first integrated circuit, and the second data pin of the second integrated circuit is used as the second A data input pin of the integrated circuit, and the second data pin of the first integrated circuit serves as a data output pin of the first integrated circuit. The electronic device of claim 3, wherein the signals of the first data pins are changed from a fourth logic state to a signal when the signals of the clock pins are in a third logic state. The fifth logic state is defined as a start signal, and the start signal indicates the beginning of a data transmission period, and "the signal of the first data pins when the signals of the clock pins are the third logic state" The transition from the fifth logic state to the fourth logic state is defined as an end signal indicating the end of the data transmission period. The electronic device of claim 1, wherein a pulse width of the first clock signal during a data transmission period is less than a threshold width, "when the first integrated circuit obtains the control right, the first The pulse width of the one-time pulse signal is greater than the threshold width is defined as a reset signal, and the first integrated circuit resets the second integrated circuit by the reset signal. The electronic device of claim 1, wherein "a pulse width of the direction control signal falls within a width range" is defined as an interrupt signal, and the first integrated circuit notifies the interrupt signal by the interrupt signal The second integrated circuit is interrupted. The electronic device of claim 1, wherein the first integrated circuit has an interrupt flag, and when the second integrated circuit obtains the control right from the first integrated circuit, the second product The body circuit reads the interrupt flag of the first integrated circuit to know whether the first integrated circuit has an interrupt request. An operating method of an electronic device, wherein the electronic device includes a first integrated circuit and a second integrated circuit, the operating method includes: outputting a directional control signal from a direction pin of the first integrated circuit a direction pin of the second integrated circuit; when the direction control signal is a first logic state, obtaining a control right by the first integrated circuit; when the first integrated circuit obtains the control right, And outputting a first clock signal to a clock pin of the second integrated circuit by a clock pin of the first integrated circuit; and when the direction control signal is a second logic state, the second product The body circuit obtains the control right; and when the second integrated circuit obtains the control right, the clock pin of the second integrated circuit outputs a second clock signal to the first integrated circuit Clock pin. The operating method of claim 8, wherein the initial state of the direction control signal is the second logic state. The method of claim 8, wherein a first data pin of the second integrated circuit is coupled to a first data pin of the first integrated circuit, and the second integrated circuit a second data pin is coupled to a second data pin of the first integrated circuit; when the first integrated circuit obtains the control, a first data pin of the first integrated circuit serves as the first data pin a data output pin of the first integrated circuit, the first data pin of the second integrated circuit is used as a data input pin of the second integrated circuit, and the second data of the first integrated circuit a pin as a data input pin of the first integrated circuit, and the second data pin of the second integrated circuit serves as a data output pin of the second integrated circuit; and when the second product When the control circuit obtains the control, the first data pin of the second integrated circuit serves as a data output pin of the second integrated circuit, and the first data pin of the first integrated circuit serves as the data pin. a data input pin of the first integrated circuit, the second data connection of the second integrated circuit As a data input of the second integrated circuit pin, the first integrated circuit and the second data pin of a data output of the first integrated circuit as a pin. The operation method of claim 10, further comprising: "turning the signals of the first data pins from a fourth logic state when the signals of the clock pins are in a third logic state State to a fifth logic state is defined as a start signal, wherein the start signal indicates the beginning of a data transmission period; and "the first time when the signals of the clock pins are the third logic state The signal of the data pin transitions from the fifth logic state to the fourth logic state is defined as an end signal, wherein the end signal indicates the end of the data transmission period. The method of claim 8, wherein the first pulse signal has a pulse width less than a threshold width during a data transmission, and the operating method further comprises: “When the first integrated circuit is When the control is obtained, the pulse width of the first clock signal is greater than the threshold width defined as a reset signal, wherein the first integrated circuit resets the second integrated circuit by the reset signal. The method of operation of claim 8 further includes: defining "a pulse width of the direction control signal within a width range" as an interrupt signal, wherein the first integrated circuit is interrupted by the interrupt The signal informs the second integrated circuit of an interrupt request. The operation method of claim 8, wherein the first integrated circuit has an interrupt flag, and the operating method further comprises: obtaining the control from the first integrated circuit when the second integrated circuit In the right time, the interrupt flag of the first integrated circuit is read by the second integrated circuit to know whether the first integrated circuit has an interrupt request.