TWI534615B - Serial peripheral interface (spi) controller, serial peripheral interface flash memory and access method and access control method thereof - Google Patents

Description

Serial peripheral interface controller, serial peripheral interface flash memory, access method thereof and access control method

The present invention relates to a memory device, and more particularly to a serial flash memory device.

Flash memory devices are commonly used in electronic applications such as personal computers, personal digital assistants (PDAs), digital cameras, and mobile phones. Generally, a flash memory device is divided into a parallel flash memory device and a tandem flash memory device. Serial flash memory has fewer transmission lines and pins than parallel flash memory. Therefore, the package size of the serial flash memory can be relatively reduced, and the serial flash memory can be used as the dominant memory of the portable electronic device.

A traditional 8-pin Serial Peripheral Interface (SPI) NAND flash memory includes a chip select pin CS#, a serial clock pin SCK, and a serial data input/serial data. Input and output pins SI/SO0, serial data output/serial data input and output pins SO/SO1, write protection/serial data input and output pin WP#/SO2, hold/serial data input and output pin HOLD#/SO3, power supply pin VCC and ground pin GND. In this specification, for the sake of brevity, serial data input/serial data input and output pin SI/SO0, serial data output/serial data input and output pin SO/SO1, write protection/serial data Input and output pins WP#/SO2 and hold/serial data input and output pins HOLD#/SO3 can also be referred to as serial input and output pins. The memory receives the wafer selection signal through the wafer selection pin CS#. When the wafer select signal goes low, the memory is in an active power mode. When the wafer select signal becomes high, the memory is disabled, and the serial data output pin SO is placed in the high impedance state High-z. The memory receives the serial clock signal through the serial clock pin SCK for providing serial interface timing for the memory. The address information, instructions, and data are latched or retrieved at the rising edge of the serial clock signal, and the output of the data is triggered after the falling edge of the serial clock signal.

1A, 1B, and 1C are timing charts showing the page read operation of the above conventional SPI NAND flash memory. The page read operation is performed to transfer the data in the NAND flash array to the cache. First, after the wafer select signal is enabled, the memory receives the page read command CMD-PR through the serial data input pin SI. Then, the memory receives the block/page address ADD-P. When the block / page address ADD-P registered (Registered), starts transmitting data to the memory cache by the NAND flash array, and the work (BUSY) t _CS long duration. Thereafter, the feature acquisition command CMD-GF is issued to detect the operation state. Based on the received status register address ADD-SR, the status register data D-SR indicating the operation status is read from the status register and then output through the serial data output pin SO.

After successfully completing the state, a random data read operation is initiated to read the data in the cache memory. The random data read operation may be a single read operation, a dual read operation, or a quad read operation. In a single read operation, the serial input and output pins SI/SO0 are used for input instructions, and the serial input and output pins SO/SO1 are used to output read data, so the bandwidth of the output data stream is 2 bits. (bits). In addition, in the quad-read operation, the serial input and output pins SI/SO0, SO/SO1, WP#/SO2, and HOLD#/SO3 are all used to output the read data, so the bandwidth of the output data stream is 4 bits.

2A and 2B are timing charts showing the quadruple read operation of the above conventional SPI NAND flash memory. In the quad-read operation, the memory receives the quad-read command CMD-RC through the serial input and output pins SI/SO0 after the wafer select signal has been enabled. After the three virtual bit DBs and the planned selection bit PS, the memory receives the column address ADD-C. Then, after a dummy byte DBy, according to the row address ADD-C, the memory will cache the memory through the serial input and output pins SI/SO0, SO/SO1, WP#/SO2, and HOLD#/SO3. The read data in the volume (such as the bits B1, B2, B3, and B4 in Figure 2B) is output.

However, in an electronic device having the capability to process multiple data streams, when the electronic device switches between different data streams to read data from the SPI NAND flash memory or write to the SPI NAND flash memory. When there is data, there may be many wait cycles. For example, when reading data through the first data stream, performing a page read operation on the first page Read and random data read operations to read data from memory. When switching to reading data through the second data stream, performing a page read operation and a random data read operation on the second page. Thereafter, when switching back to read data through the first data stream, since the cache memory currently stores the data of the second page, the page read operation on the first page needs to be performed again to read the information of the first page. The cache memory is fetched, and then a random data read operation is performed to read the data in the cache memory. In other words, it is possible to initiate a page read instruction, a block/page address, a get feature instruction, a state register address, and a row address again. Therefore, due to the increased waiting period and repeated transmission of some information (such as address, instructions, previously read data, etc.) without re-use, especially in the case of frequent switching between different streams of data to perform access Under conditions, it is possible to waste a lot of time and access resources.

In view of the above, the present invention provides at least one serial peripheral interface controller, a serial peripheral interface flash memory, an access method thereof, and an access control method.

The present invention provides an access method for a serial peripheral interface flash memory, wherein the serial peripheral memory flash memory comprises a flash memory array and supports a plurality of data streams, the access method comprising: Receiving a stream initiate instruction for one of the plurality of data streams, wherein the stream initiation instruction includes an access type and an identification code of the data stream; receiving the address information, wherein the address information Include a page address and an address pointer of a page of the flash memory array; and read data from the flash memory array to correspond to the flow start instruction and the page address The information Streaming a stream register, or according to the stream start command, storing data to be written into the flash memory array into the stream register corresponding to the data stream.

The present invention further provides an access control method for a serial peripheral interface flash memory, wherein the serial peripheral interface flash memory includes a flash memory array and supports multiple data streams, and the access method The method includes: sending a first-class startup command to the serial peripheral interface flash memory, wherein the flow startup instruction is used for one of the plurality of data streams, and the flow startup instruction includes an access type of the data stream and An identification code; sending address information to the serial peripheral interface flash memory, wherein the address information includes one page address and an address index of one of the pages of the flash memory array; and starting according to the stream The instruction and the page address, controlling the serial peripheral interface flash memory to read data from the flash memory array to a stream register corresponding to the data stream, or controlling the string according to the stream start command The column peripheral interface flash memory stores data to be written to the memory array into the stream register corresponding to the stream.

The invention further provides a serial peripheral interface flash memory, which supports multiple data streams. The serial peripheral memory flash memory comprises: a flash memory array; a plurality of stream registers, each stream temporarily stored Corresponding to one of the plurality of data streams; and a control logic coupled to the flash memory array and the plurality of stream registers for receiving one of the plurality of data streams a first-level boot command and address information, wherein the stream start command includes an access type of the data stream and an identification code, and the address information includes a page address and a bit of one of the pages of the flash memory array An address indicator, wherein the data is read from the flash memory array to a stream register corresponding to the data stream according to the stream start command and the page address, or the data is stored according to the stream start command. In this capital The stream is in the stream register.

The present invention further provides a serial peripheral interface controller coupled to a serial peripheral interface flash memory for controlling access operation of the serial peripheral interface flash memory, wherein the serial peripheral interface flash memory The body comprises a flash memory array and supports a plurality of data streams. The serial peripheral interface controller comprises: a control logic, and sends a flow start command and address information for one of the plurality of data streams Up to the serial peripheral interface flash memory, wherein the stream startup instruction includes an access type of the data stream and an identification code, and the address information includes one page address of one of the pages of the flash memory array And an address indicator, and the control logic controls the serial peripheral interface flash memory to read data from the flash memory array to correspond to one of the data streams according to the flow start command and the page address. The memory, or the control logic, stores the data to be written into the flash memory array into the stream register corresponding to the data stream according to the stream start command.

By using the serial peripheral interface controller, the serial peripheral interface flash memory, the access method and the access control method provided by the invention, the data stream access can be efficiently operated and the processing time can be shortened.

30‧‧‧Main processor

35‧‧‧Main processor bus

40‧‧‧ main memory

50‧‧‧SPI controller

56‧‧‧SPI bus

60‧‧‧SPI Flash Memory

410, 420, 480‧‧‧ data buffer

500, 600‧‧‧ control logic

510, 610‧‧ ‧ stream register group

511, 512, 518, 611, 612, 618‧‧ ‧ stream registers

521, 522, 523, 620‧‧ ‧ multiplexers

530‧‧‧Serial/Parallel Converter

531‧‧‧Parallel to QPI Converter

532‧‧‧QPI to Parallel Converter

540, 640‧‧‧ input/output buffers

541, 642‧‧‧ tristate buffer

542, 641‧‧ ‧ buffer

630‧‧‧Page cache memory

650‧‧‧ instruction register

660‧‧‧ address register

670‧‧‧data register

680‧‧‧ memory core

682‧‧‧Flash memory array

684‧‧‧ column decoder

686‧‧‧ line decoder

ADD, ADD_I‧‧‧ address information

ADD_C‧‧‧ address

ADD_P‧‧‧ Block/Page Address

ADD_SR‧‧‧Status Register Address

B1, B2, B3, B4‧‧‧ bytes

CMD-GF‧‧‧Get feature instructions

CMD-ID‧‧‧Continuous reading instructions

CMD-PR‧‧‧ page read command

CMD-RC‧‧‧ four-fold read command

CMD-SI‧‧‧ flow start command

CS#‧‧‧ wafer selection pin

D-SR‧‧‧ Status Register Information

DB‧‧‧ virtual bit

DBy‧‧‧virtual byte

High-z‧‧‧high impedance state

PS‧‧‧ plan selection bit

SCK‧‧‧ series clock pin

SI/SO0, SO/SO1, WP#/SO2, HOLD#/SO3‧‧‧ serial input and output pins

1A, 1B, and 1C show timing diagrams of page read operations of conventional SPI NAND flash memory.

Figures 2A and 2B show timing diagrams of a quad-read operation of a conventional SPI NAND flash memory.

3A and 3B show SPI NAND fast in accordance with an embodiment of the present invention Timing diagram of the flash memory start operation.

Figure 4 is a timing diagram showing successive read operations of a SPI NAND flash memory in accordance with an embodiment of the present invention.

Figure 5 shows a block diagram of an SPI controller 50 in accordance with an embodiment of the present invention.

Figure 6 shows a block diagram of SPI memory 60 in accordance with an embodiment of the present invention.

Certain terms are used throughout the description and claims to refer to particular components. It should be understood by those of ordinary skill in the art that hardware manufacturers may refer to the same component by different nouns. This specification and the scope of the patent application do not use the difference of the names as the means for distinguishing the components, but the difference in the function of the components as the criterion for distinguishing. The term "including" as used throughout the specification and the scope of the patent application is an open term and should be interpreted as "including but not limited to". "About" means that within the acceptable error range, those skilled in the art can solve the technical problem within a certain error range, and basically achieve the technical effect. In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, the first device can be directly electrically connected to the second device, or can be electrically connected to the second device through other devices or connection means. Device. The description of the present invention is intended to be illustrative of the preferred embodiments of the invention. The scope of the invention is defined by the scope of the appended claims.

An embodiment of the present invention provides an access method for SPI flash memory. The SPI flash memory contains a flash memory array and supports multiple streams of data. The SPI flash memory further includes a plurality of stream registers, each stream register corresponding to one of the plurality of data streams. The access method includes a stream initiation operation, a page access operation, and a continuous access operation, wherein the flow initiation operation is used to initiate one of a plurality of data streams. The number of data streams described above can range from 4 to 8.

3A and 3B are timing diagrams showing the flow start operation of the SPI NAND flash memory in accordance with an embodiment of the present invention. First, a stream initiation command CMD-SI is received for one of a plurality of data streams (e.g., ^Xth data stream). The stream start command CMD-SI contains the access type of the data stream and the identification code of the data stream. The access type may be a read type or a write type, wherein the read type indicates that the access operation of the data stream is a read operation, the write type indicates that the access type of the data stream is a write operation, and for a single data stream There is only one access type. The access type and identification code of the data stream can be determined according to the command word of the stream start command CMD-SI. For example, the instruction word indicating a 4Xh X ^th data stream and performs a read operation start command ilk. Then, the address information ADD-I is received. The address information ADD-I contains the page address and address index of the page of the flash memory array. The access type and the received address information ADD-I can be stored in a stream register corresponding to the data stream, and the address indicator is used to point to the data stored in the stream register. Therefore, the address information ADD-I can be a combination of the page address ADD-P in the 1A and 1B pictures and the row address ADD-C in the 2A picture. When the SPI flash memory receives the stream start instruction and the address information for the data stream, and the access type has been stored in the corresponding stream register, the data stream is started, in other words, the stream start operation ends.

The page access operation follows the stream start operation, and is used to read the page data from the flash memory array to the stream register corresponding to the data stream according to the stream start instruction and the page address, or to write according to the stream start instruction. The data entered into the flash memory is stored in a stream register corresponding to the stream. The page access operation for the data stream is performed spontaneously after the end of the flow for streaming the data stream. For example, if the first stream start instruction indicates a stream start operation for the first data stream and performs a read operation, after the first data stream is started, the page address in the address information is read from the flash memory. The page data is stored in the first stream register of the SPI flash memory corresponding to the first data stream. If the second stream start instruction indicates a stream start instruction for the second data stream start instruction and the write operation, when the second data stream is started, the page data to be written to the flash memory array is sent, and It is stored in the second stream register of the SPI flash memory corresponding to the second data stream.

The continuous access operation follows the page access operation for outputting the read page data (continuous read operation) from the stream register according to the address index, or the page in the stream register according to the address index Data is written to the flash memory array (continuous write operation). In a continuous access operation, successive access instructions for the data stream are first received. The continuous access instruction contains the identification code of the data stream. In the continuous read operation, according to the address index, the read page data in the stream register corresponding to the data stream is read out from the SPI flash memory, wherein the stream register can be identified according to the data stream. The code determines and the address indicator increases after the data is output. In the continuous write operation, according to the page address and the address index, the page data corresponding to the stream buffer of the data stream is written into the flash memory, wherein the stream is temporarily stored. The device can be determined according to the identification code of the data stream, and the address indicator is increased after the data is written.

Figure 4 is a timing diagram showing successive read operations of a SPI NAND flash memory in accordance with an embodiment of the present invention. First, a continuous read command CMD-ID containing the identification code of the data stream is received. For example, the instruction word indicates a sequential read 5Xh X ^th data stream of instructions. Then, according to the address index stored in the ^Xth stream register, the page data in the ^Xth stream register is read (such as the output data bytes B1, B2, B3, and B4 in FIG. 4). The address indicator read from the SPI flash memory and stored in the ^Xth stream register is incremented after the read page data is output in the ^Xth stream register. For example, in a data stream for the X ^th ilk received the start-up operation of the first address pointer point to the X ^th X ^th data stream in the stream register has been read a first group of bits of the data page. After outputting the first byte, the second byte, the third byte, and the fourth byte by the X ^th stream register, the address index stored in the X ^th data stream is increased to point to X The fifth byte of the page data has been read in the ^th stream register. Therefore, when the four bytes of the read page data in the ^Xth stream register have been output, if the SPI flash memory is switched from the ^Xth stream to another stream, then switch back to ^Xth. For the data stream, the fifth byte of the read page data in the ^Xth stream register can be directly output according to the address index without sending the row address. Further, after the ^Xth data stream is started, since the read page data for the ^Xth data stream is stored in the ^Xth stream register, it is not necessary to initiate the page address again when switching back to the ^Xth stream. Page read operation. Accordingly, the above access operations consume less processing time than prior art techniques.

In addition, during a continuous access operation, if the address indicator stored in the stream register enters the page boundary area of the page stored in the stream register In a (boundary zone), pre-fetch is close to the data of another page of the page, so that when the page boundary is crossed, the data can be accessed continuously without waiting for the page waiting period at the page boundary. The page boundary area can be N bits in front of the page boundary. For example, N can be 16 or 32.

In one embodiment, a stream initiation operation for multiple data streams may be initiated in succession. The sequence of operations and page access operations for the initiation of the plurality of streams may be determined based on the order in which the stream start instructions are received. In addition, continuous access operations for data streams cannot be performed until the start of the data stream and the end of the page access operation. In addition, if the stream initiation operation and the page access operation of the data stream are not completed when the continuous access operation for the data stream is initiated, a pause vector may be output from the SPI flash memory to notify the SPI control. The device and/or host processor operation is not completed. As described above, for example, a stream initiation operation for the first data stream, a stream initiation operation for the second data stream, a stream initiation operation for the third data stream, and a continuous access operation for the first data stream Continuous access operation for the second data stream, continuous access operation for the first data stream, continuous access operation for the third data stream, and successive access operations for the first data stream are sequentially initiated . Therefore, the initiation of operation of multiple data streams is more efficient and the processing time is relatively shorter compared to the prior art.

FIG. 5 shows a block diagram of an SPI controller 50 in accordance with an embodiment of the present invention, wherein the SPI controller 50 performs an access control method for the SPI flash memory 60. The SPI controller 50 is coupled to the main processor 30 via the main processor bus 35. The SPI controller 50 is coupled to the main memory 40 and coupled to the SPI flash memory 60 via the SPI bus 56. SPI flash memory 60 contains flash memory array The column supports and supports multiple data streams (eight data streams in this embodiment). The SPI controller 50 can be integrated into the main processor 30 or can be integrated into one of the external SPI interfaces coupled to the main processor 30. The SPI controller 50 receives an access command from the main processor 30 to control the access operation of the SPI flash memory 60. The SPI controller 50 sends the data to be written (such as the write data WD from the main memory 40) to the SPI flash memory 60, or transmits the data read in the SPI flash memory 60 to the main processor 30. .

The SPI controller 50 includes control logic 500, stream register set 510, multiplexers 521, 522, and 523, a serial/parallel converter 530, and an input/output buffer 540, wherein the stream register set 510 The stream registers 511-518 are included, and the serial/parallel converter 530 includes a parallel to Quad Peripheral Interface (QPI) converter 531 and a QPI to parallel converter 532. The input/output buffer 540 includes three states. A tri-state buffer 541 and a buffer 542. Each stream register of the stream register group 510 stores instruction, status, and address information of a corresponding stream of the plurality of data streams. The instructions stored in each of the stream registers of the stream register group 510 are coupled to the multiplexer 521, and the address information information stored in each stream register of the stream register group 510. Connected to the multiplexer 522. The multiplexer 521 outputs the selected command/state CS to the control logic 500, and the multiplexer 522 outputs the selected address information ADD to the input of the multiplexer 523. The other input of the multiplexer 523 receives the write data WD from the main memory 40 to be written to the SPI flash memory 60. The main memory 40 can include data buffers for a plurality of data streams, such as data buffers 410-480. The output of the multiplexer 523 is coupled to the parallel to QPI converter 531, and the parallel to QPI converter 531 is coupled to the tristate buffer 541. The control logic 500 is coupled to the multiplexers 521, 522, and 523. The instructions, status, address information, and write data of the plurality of data streams are selected based on the access instructions from the main processor 30. Control logic 500 also controls serial/parallel converter 530 and tristate buffer 541. The read data from the SPI flash memory 60 is sent to the buffer 542 via the SPI bus 56 and thereafter sent to the QPI to parallel converter 532. The QPI-to-parallel converter 532 outputs the read data RD, and the read data RD is sent to the main processor 30 through the main processor bus 35.

Control logic 500 controls the components of SPI controller 50 to control the access operation of SPI flash memory 60. The control logic 500 sends a stream start command for one of the plurality of data streams and address information of the data stream to the SPI flash memory 60 to control the SPI flash memory 60 according to the stream start command and the address. The information is executed for the stream initiation operation and page access operation of the data stream. The stream start command includes the access type of the data stream and the identification code of the data stream. The address information includes the page address and address index of the page of the flash memory array of the SPI flash memory 60. When the access type of the data stream indicates the read operation, according to the flow start command and the page address, the control logic 500 controls the SPI flash memory 60 to read the data from the flash memory to the SPI corresponding to the data stream. A stream register in the flash memory 60. Optionally, when the access type of the data stream indicates the write operation, according to the flow start instruction, the control logic 500 controls the SPI flash memory 60 to store the data to be written into the flash memory array into the data stream. The stream register in the SPI flash memory 60. The details of the stream start operation and the page access operation have been described above, and for brevity, no further details are provided herein.

Control logic 500 further transmits successive access instructions for the data stream to SPI flash memory 60 to control SPI flash memory 60 to perform successive access operations for the data stream. The continuous access instruction contains the identification code of the data stream. when When the access type of the data stream indicates the read operation, the control logic 500 controls the SPI flash memory 60 according to the address index stored in the stream register in the SPI flash memory 60 corresponding to the data stream. The output data in the stream register in the SPI flash memory 60 corresponding to the data stream is sent to the SPI controller 50, and the address index is increased after the data is output. Optionally, when the access type of the data stream indicates the write operation, the control logic is based on the page address and the address index stored in the stream buffer in the SPI flash memory 60 corresponding to the data stream. The 500 control SPI flash memory 60 writes the data stored in the stream register in the SPI flash memory 60 corresponding to the data stream to the flash memory array, and the address index is increased after the data is written. . The details of the continuous access operation and the address index have been described above, and for brevity, no further details are provided herein.

When the address metric stored in the stream register in the SPI flash memory 60 corresponding to the data stream enters the page boundary area of the page, the control logic 500 can further control the SPI flash memory 60 to prefetch the proximity. Corresponding to the data of another page of the page stored in the stream register in the SPI flash memory 60 of the stream. Therefore, data can be accessed continuously across page boundaries without having to wait for page wait cycles at page boundaries. The page boundary area can be N bits in front of the page boundary. For example, N can be 16 or 32.

Please note that the SPI controller 50 in FIG. 5 is only a preferred example, and the present invention is not limited thereto. For example, the SPI controller 50 can further include a signal generating unit for generating a signal, such as a serial clock signal generating unit.

Figure 6 shows a block diagram of SPI memory 60 in accordance with an embodiment of the present invention. The SPI memory 60 supports a plurality of data streams (eight data streams in this embodiment), and includes a control logic 600, a stream register group 610, and a multiplexer 620. Page cache memory 630, input/output buffer 640, instruction register 650, address register 660, data register 670 and memory core 680, wherein stream register group 610 includes stream register 611~618, the input/output buffer 640 includes a buffer 641 and a tristate buffer 642. The memory core 680 includes a flash memory array 682, a row decoder 684, and a column decoder 686. Control logic 600 controls the components of SPI flash memory 60 to perform access operations based on instructions and information received from SPI controller 50. The input/output buffer 640 is coupled to the SPI bus 56. The instruction register 650, the address register 660, and the data register 670 are coupled to the buffer 641. The address register 660 and the data register 670 are further coupled to the memory core 680. The instructions for the data stream received from the SPI controller 50 are temporarily stored in the instruction register 650 and then transmitted and stored to the corresponding stream register in the stream register group 610. The address information of the data stream received from the SPI controller 50 is temporarily stored in the address register 660 and then transmitted and stored to the corresponding stream register in the stream register group 610. When the continuous access operation for the data stream is initiated, the address information stored in the stream register corresponding to the data stream is sent to the address register 660, so that the continuous access operation can be based on the address information. carried out. The data received from the SPI controller 50 to be written to the flash memory array 682 is temporarily stored in the data register 670 and then transmitted and stored to the corresponding stream register in the stream register group 610. When a continuous write operation for the data stream is initiated, the data stored in the stream register corresponding to the data stream is sent to the data register 670 for writing to the flash memory array 682.

The control logic 60 receives the stream start command from the SPI controller 50 for one of the plurality of data streams and the address information for the data stream, and controls the SPI flash according to the stream start command and the address information. Memory 60 The component performs a stream initiation operation and a page access operation for the data stream. The stream start instruction includes an access type of the data stream and an identification code of the data stream. The address information includes the page address and address indicator of the page of the flash memory array 682. The access type and the received address information are stored in a stream register in the stream register group 610 corresponding to the data stream. When the access type indicates a read operation, the control logic 600 controls the SPI flash memory 60 to read data from the flash memory array 682 to the page cache memory 630 according to the stream start command and the page address. Then, Based on the identification code of the data stream, the page data in the page cache 630 is sent and stored to the stream register in the stream register group 610 corresponding to the data stream. Optionally, when the access type indicates a write operation, according to the flow start command, the control logic 600 controls the SPI flash memory 60 to store the data to be written into the flash memory array 682 into the stream corresponding to the data stream. The stream register in the register set 610. The details of the stream start operation and the page access operation have been described above, and for brevity, no further details are provided herein.

Control logic 600 further receives successive access instructions for data streams from SPI controller 50 and controls SPI flash memory 60 to perform successive access operations for the data stream. The continuous access instruction contains the identification code of the data stream. When the access type of the data stream indicates a read operation, the control logic 600 controls the SPI flash memory 60 based on the address index stored in the stream register in the stream register group 610 corresponding to the data stream. The data is output from the stream register in the stream register group 610 corresponding to the data stream to the tristate buffer 642, and the control logic 600 increases the address index after the data is output. Optionally, when the access type indicates a write operation, the control logic 600 controls the SPI according to the page address and the address index stored in the stream register in the stream register group 610 corresponding to the data stream. Flash memory The body 60 writes the data stored in the stream register in the stream register group 610 corresponding to the stream to the flash memory array 682. The continuous access operation and address metrics have been described above, and for brevity, they are not described here.

When the address indicator stored in the stream register enters the page boundary area of the page stored in the stream register, the data of another page near the page is prefetched into the stream register. Thus, data can be accessed continuously across page boundaries without having to wait for page wait periods at page boundaries. The page boundary area can be N bits in front of the page boundary. For example, N can be said to be 16 or 32.

Please note that the above SPI flash memory and SPI controller are backward compatible. For example, in an embodiment, access operations of large data traffic, such as access operations related to booting and data download or data copying of multiple data blocks, may be based on the above Access protocol execution, other small data traffic access operations can be performed according to known access protocols.

As described above, the present invention provides a multi-stream serial flash memory device and a multi-stream access protocol thereof for efficiently initiating data stream operations and shortening processing time.

While the present invention has been described by way of example only, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

60‧‧‧SPI Flash Memory

600‧‧‧Control logic

610‧‧‧Stream register group

611, 612, ..., 618‧‧ ‧ stream register

620‧‧‧Multiplexer

630‧‧‧Page cache memory

640‧‧‧Input/Output Buffer

641‧‧‧buffer

642‧‧‧Three-state buffer

650‧‧‧ instruction register

660‧‧‧ address register

670‧‧‧data register

680‧‧‧ memory core

682‧‧‧Flash memory array

684‧‧‧ column decoder

686‧‧‧ line decoder

Claims (12)

An access method for a serial peripheral memory flash memory, wherein the serial peripheral memory flash memory comprises a flash memory array and supports multiple data streams, the access method includes: receiving a first-class boot The instruction is used for one of the plurality of data streams, wherein the stream initiation instruction includes an access type of the data stream and an identification code; and receiving the address information, wherein the address information includes the flash memory a page address and an address pointer of one of the array pages; and reading data from the flash memory array to a stream register corresponding to the data stream according to the stream start command and the page address, Or according to the flow start command, the data to be written into the flash memory array is stored in the stream register corresponding to the data stream. The access method of claim 1, further comprising: receiving a continuous access instruction for the data stream, wherein the continuous access instruction includes the identification code of the data stream; and Taking the type and the address indicator, outputting the data from the stream register corresponding to the data stream, or writing the data to the flash memory array; wherein the address indicator is output or written in the data Increase after entering. The access method of claim 2, further comprising: prefetching data of another page close to the page when the address indicator enters a page boundary area of the page. An access control method for a serial peripheral interface flash memory, wherein the serial peripheral interface flash memory comprises a flash memory array and supports Assisting multiple data streams, the access method includes: sending a first-class startup command to the serial peripheral interface flash memory, wherein the flow startup instruction is used for one of the plurality of data streams, and the flow initiation instruction Include one access type of the data stream and an identification code; send address information to the serial peripheral interface flash memory, wherein the address information includes a page address of one of the pages of the flash memory array and An address indicator; and controlling, according to the stream start command and the page address, the serial peripheral interface flash memory to read data from the flash memory array to a stream register corresponding to the data stream, Or according to the flow start command, controlling the serial peripheral interface flash memory to store data to be written into the memory array into the stream register corresponding to the data stream. The access control method of claim 4, further comprising: transmitting a continuous access instruction to the serial peripheral interface flash memory, wherein the continuous access instruction is used for the data stream, and the The continuous access instruction includes the identification code of the data stream; and controlling, according to the access type and the address indicator, the serial peripheral interface flash memory to be output by the stream register corresponding to the data stream Data, or write the data to the flash memory array; wherein the address indicator is incremented after the data is output or written. The access control method of claim 5, further comprising: controlling the string when the address indicator enters a page boundary area of the page The column peripheral interface flash memory prefetches data near another page of the page. A serial peripheral interface flash memory supporting a plurality of data streams, the serial peripheral memory flash memory comprising: a flash memory array; a plurality of stream registers, each stream register corresponding to the One of the plurality of data streams; and a control logic coupled to the flash memory array and the plurality of stream registers to receive a flow start command for one of the plurality of data streams and An address information, wherein the flow start instruction includes an access type of the data stream and an identification code, and the address information includes a page address and an address indicator of one of the pages of the flash memory array; The data is read from the flash memory array to a stream register corresponding to the data stream according to the stream start command and the page address, or the data is stored according to the stream start command. The stream is in the stream register. The serial peripheral interface flash memory of claim 7, wherein the control logic further receives a continuous access instruction for the data stream, the continuous access instruction including the identification code of the data stream The data is output or written to the flash memory array by the stream register corresponding to the data stream according to the access type and the address indicator, and the control logic outputs or writes the data in the data stream. Increase the address indicator after entering. The serial peripheral interface flash memory as described in claim 8 wherein the data of another page adjacent to the page is when the address indicator enters the Prefetch when one of the page boundary areas of the page. A serial peripheral interface controller coupled to a serial peripheral interface flash memory for controlling access operation of the serial peripheral interface flash memory, wherein the serial peripheral interface flash memory comprises a fast Flash memory array and supporting multiple data streams, the serial peripheral interface controller includes: a control logic, sending a flow start command and address information for one of the plurality of data streams to the serial a peripheral interface flash memory, wherein the stream startup command includes an access type of the data stream and an identification code, and the address information includes a page address and an address of one of the pages of the flash memory array The indicator, and the control logic controls, according to the flow start command and the page address, the serial peripheral interface flash memory to read data from the flash memory array to a stream register corresponding to the data stream, or The control logic stores data to be written to the flash memory array into the stream register corresponding to the data stream according to the stream start command. The serial peripheral interface controller of claim 10, wherein the control logic further transmits a continuous access instruction for the data stream to the serial peripheral interface flash memory, wherein the continuous access The instruction includes the identification code of the data stream, and the control logic controls the serial peripheral interface flash memory according to the access type and the address indicator to output the data from the stream register corresponding to the data stream. Up to the serial peripheral interface controller or writing the data to the flash memory array, wherein the address indicator is incremented after the data is output or written. The serial peripheral interface controller according to claim 11, wherein when the address indicator enters a boundary area of a page of the page, the control The logic controls the serial peripheral interface flash memory to prefetch data adjacent to another page of the page.