TWI688955B - Memory apparatus and accessing method for memory thereof - Google Patents

Abstract

A memory apparatus and an accessing method for a memory thereof are provided. The accessing method includes: receiving a write-in data stream, where the write-in data stream includes a plurality of data packages arranged in sequential; duplicating the data packages to generate a plurality of cloned data packages, and arranging each of the data packages and corresponding cloned data package in sequential to generate an updated write-in data stream; generating a data request signal with a plurality of transition points according to the updated write-in data stream, where each of the transition points corresponds to each of the data packages or each of the cloned data packages; and writing the updated write-in data stream to the memory according to the data request signal.

Description

Memory device and memory access method

The invention relates to a memory device and a memory access method, and in particular to a memory device and a memory access method that can accelerate the data reading rate.

In NAND type flash memory, its native access interface can be divided into traditional mode (Legacy mode) and swap mode (Toggle mode). In an electronic device, the flash memory management device used to store the flash memory, when accessing the flash memory, must first search for the flash memory interface mode before the flash memory can be accessed. Read the correct information in the flash memory. Taking the reading action of the boot table as an example, the conventional technology needs to read for two different interface modes in order to know the correct information about the boot table. As a result, the reading time is wasted and the working efficiency of the electronic device is reduced.

The invention provides a memory device and a memory access method, which can speed up the data reading rate.

The memory access method of the present invention includes: receiving a written data sequence, the written data sequence includes a plurality of data packets arranged in sequence; copying the data packet to generate a plurality of copied data packets, so that each data packet Arrange each corresponding copy data packet in sequence to generate an updated write data sequence; correspondingly update the written data sequence to generate a data access request signal, wherein the data access request signal has multiple transition points, each The transition point corresponds to each data packet or each copied data packet; and, the update write data sequence is written into the memory according to the data access request signal.

The memory device of the present invention includes a memory and a controller. The controller is coupled to the memory and is used to: receive the written data string, which includes multiple data packets arranged in sequence; copy the data packet to generate multiple copied data packets, so that each data packet and Corresponding copy data packets are arranged in sequence with each other to generate an updated write data sequence; correspondingly update the written data sequence to generate a data access request signal, wherein the data access request signal has multiple transition points, each The state point corresponds to each data packet or each copied data packet; and, the updated write data sequence is written into the memory according to the data access request signal.

Based on the above, the present invention copies a plurality of data packets written in the data string, and arranges the data packets and copies the data packets to generate an updated write data string. By writing the update write data series into the memory and making the memory in the read mode, the read data can be obtained through a fixed mode. In this way, the controller does not need to know the writing mode of the data in the memory, and can directly obtain the correct data, increasing the reading rate.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

Please refer to FIG. 1, which is a flowchart of a memory access method according to an embodiment of the invention. In this embodiment, the memory may be a non-volatile memory, such as a NAND flash memory. In FIG. 1, step S110 receives a write data sequence, where the write data sequence includes multiple data packets arranged in sequence. Next, in step S120, the data packets written in the data string are copied to generate a plurality of copied data packets, and each data packet and the corresponding copied data packets are arranged in sequence with each other, and an updated write data string is generated.

Please note that the content of the data in each data packet and the corresponding copy data packet is exactly the same. Moreover, the data size of each data packet may be 1 byte, or may be multiple bytes (for example, 4K bytes), and there is no certain limit. The designer can set the size of each data packet according to different applications of the memory. The size of each data packet and the data in the corresponding copy data packets are also the same.

Following the above description, step S130 correspondingly updates the timing of writing the data sequence to generate a data access request signal, where the data access request signal may be a digital signal and has multiple transitions from logic high levels To logic low level, and the transition point from logic low level to logic high level. Each of the above transition points corresponds to updating the data packet written in the data sequence or copying the data packet.

Finally, step S140 causes the updated write data series to be written into the memory according to the data access request signal.

In order to explain the implementation details of this embodiment more clearly, please refer to FIG. 1, FIG. 2 and FIG. 3 together, where FIG. 2 illustrates the generation method of the update write data sequence according to the embodiment of the invention, and FIG. 3 illustrates the invention Operation waveform diagram of the data writing mode of the embodiment. Taking the drawing of FIG. 2 as an example, when step S110 receives the written data sequence DATA including data packets B0, B1, ..., step S120 can copy the written data sequence DATA by copying each data packet and Corresponding copy data packets are arranged in sequence with each other to generate an updated write data sequence WDATA including data packets B0, B0, B1, B1,...

In FIG. 3, according to control signals such as chip enable signal CEn, data latch signal CLE, address latch signal ALE, write signal WEn and read signal REn, the memory can enter data write mode and execute data Write action. In this embodiment, corresponding to the timing of updating the write data sequence WDATA, the memory controller (not shown) can provide a continuously transitional data access request signal DQS. In FIG. 3, the data access request signal DQS has a plurality of transition points TP1~TP4 generated at time points t1~t4, respectively. Among them, the transition points TP1 and TP3 are the rising edges from the logic low level to the logic high level, and the transition points TP2 and TP4 are the falling edges from the logic high level to the logic low level.

In this embodiment, the transition points TP1 to TP4 correspond to the data packets B0, B0, B1, B1 in the updated write data sequence WDATA, respectively. Among them, it is worth mentioning that the updated write data sequence WDATA can provide data packets B0, B0, B1, B1, ... with stable voltage values at time points t1~t4, respectively. In this way, according to the multiple transition points TP1~TP4 of the data access request signal DQS, updates can be written into the data packets B0, B0, B1, B1, ... in the data sequence WDATA sequentially into the memory .

It should be noted that in the above-mentioned embodiment, the update write data sequence WDATA is written into the memory according to the first working mode. Here, the first operating mode is the so-called toggle mode.

For the part of the data reading mode, please refer to FIG. 4, wherein FIG. 4 illustrates an action waveform diagram of the data reading mode of the embodiment of the present invention. In FIG. 4, the memory controller provides a read signal REn with multiple transition points, and provides a data access request signal DQS with multiple transition points according to the read signal REn. The read signal REn has multiple transition points as falling edges at time points t2 and t5, respectively, and the data access request signal DQS has multiple falling edges or rising edges at time points t1, t3, t4, and t6, respectively. Turning point. Also, it is worth noting that the read signal REn and the data access request signal DQS have a phase difference.

Through multiple transition points of the data access request signal DQS, the memory is read out through a second working mode (legacy mode), and multiple read data packets arranged in sequence are obtained The read data series consisting of B0, B0, B1, B1, B2, and B2 is RDATA. Wherein, the read data packets B0, B0, B1, B1, ... correspond to multiple transition points of the data access request signal DQS, respectively, and are generated in sequence at time points t1, t3, t4, t6, ....

On the other hand, through the read signal REn generated at the time points t2, t5 as the transition point of the falling edge, data can be read for the read data packets (eg, data packets B0, B1) in the read data series RDATA Capture the action and get the correct reading data.

From the above description, it is not difficult to find that through the data writing method of the embodiment of the present invention, under the condition that the interface mode of the memory is the first working mode (exchange mode), the second working mode (traditional mode) can still be successfully passed ) Interface mode to read the correct reading data. That is to say, in the embodiment of the present invention, the reading operation of the memory data does not need to spend extra time to determine the interface mode used when writing the data by searching. Can directly read the correct reading data through the traditional mode interface mode.

Please refer to FIG. 5 below, which is a schematic diagram of a memory device according to an embodiment of the invention. The memory device 500 includes a memory 510 and a controller 520. The controller 520 is coupled to the memory 510, and is used to perform the data writing operation and the data reading operation as mentioned in the foregoing embodiment. The operation details of the controller 520 are described in detail in the foregoing embodiment, and will not be described in detail below.

Incidentally, in this embodiment, the memory 510 may be a non-volatile memory, such as a NAND flash memory. In addition, the controller 520 may be a processor with computing capability. Alternatively, the controller 520 can be designed through a hardware description language (Hardware Description Language, HDL) or any other design method of digital circuits well known to those skilled in the art, and through a field programmable logic gate array ( Field Programmable Gate Array (FPGA), complex programmable logic device (Complex Programmable Logic Device, CPLD) or special application integrated circuit (Application-specific Integrated Circuit, ASIC) to realize the hardware circuit.

In summary, the present invention writes the data series by copying, and generates the update write data series by arranging the data packets and copying the data packets, and writes the update write data series into the memory. In this way, when the data reading operation is performed on the memory, the correct reading data can be quickly obtained, and the working efficiency is improved.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

S110~S140: Memory access steps DATA: Write data series WDATA: update write data series B0, B1: data packet CEn: Wafer enable signal CLE: data latch signal ALE: address latch signal WEn: write signal REn: read signal DQS: data access request signal WDATA: update write data series t1~t6: time point TP1~TP4: transition point RDATA: read data series 500: memory device 510: memory 520: Controller

FIG. 1 is a flowchart of a memory access method according to an embodiment of the invention. FIG. 2 illustrates the generation method of the update write data sequence according to an embodiment of the invention. FIG. 3 illustrates an operation waveform diagram of the data writing mode according to an embodiment of the invention. FIG. 4 illustrates an operation waveform diagram of the data reading mode according to an embodiment of the invention. 5 is a schematic diagram of a memory device according to an embodiment of the invention.

S110~S140: Memory access steps

Claims (12)

A memory access method, including: Receiving a write data series, the write data series including multiple data packets arranged in sequence; Copying the data packets to generate a plurality of copying data packets, so that each data packet and the corresponding copying data packets are arranged in sequence with each other to generate an update write data sequence; Corresponding to updating the written data sequence to generate a data access request signal, wherein the data access request signal has multiple transition points, and each of the transition points corresponds to each of the data packets or each of the copied data packets; and The update write data series is written into the memory according to the data access request signal. The method for accessing a memory as described in item 1 of the patent application, wherein the step of causing the updated write data series to be written into the memory according to the data access request signal includes: The update is written into the data series according to a first working mode according to the data access request signal to be written into the memory. The memory access method as described in item 2 of the patent application scope, wherein the first working mode is a swap mode. The method for accessing memory as described in item 1 of the patent application, wherein the size of each data packet is 4K bytes. The memory access method as described in item 1 of the patent application scope further includes: In a data reading mode, a reading signal is provided, and the data access request signal is generated according to the reading signal, wherein the reading signal and the data access request signal have a phase difference. The memory access method as described in item 5 of the patent application scope further includes: According to the transitional edges of the data access request signal, a read data sequence with a plurality of read data packets is read out from the memory, and according to the first transitional edges of the read signal Retrieve each read data packet. The method for accessing a memory as recited in item 6 of the patent application range, wherein the first transition edge of the read signal is the falling edge of the read signal. The memory access method as described in item 5 of the patent application scope, wherein each first transition edge of the read signal occurs after each transition edge of the corresponding data access request signal, and the Each first transition edge of the read signal is adjacent to the occurrence time point of each transition edge of the corresponding data access request signal. The memory access method as described in item 5 of the patent application scope, wherein the data reading mode is a traditional mode. A memory device, including: A memory; and A controller, coupled to the memory, is used to: Receiving a write data series, the write data series including multiple data packets arranged in sequence; Copying the data packets to generate a plurality of copying data packets, so that each data packet and the corresponding copying data packets are arranged in sequence with each other to generate an update write data sequence; Corresponding to updating the written data sequence to generate a data access request signal, wherein the data access request signal has multiple transition points, and each of the transition points corresponds to each of the data packets or each of the copied data packets; and The update write data series is written into the memory according to the data access request signal. The memory device as described in item 10 of the patent application scope, wherein the controller is further used to: In a data reading mode, providing a reading signal and generating the data access request signal according to the reading signal, wherein the reading signal and the data access request signal have a phase difference; and A read data is read from the memory according to a first transition edge of the data access request signal, and the read data is retrieved according to a second transition edge of the read signal. The memory device as described in item 11 of the patent application range, wherein the controller is set to a conventional mode in the data reading mode.

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