CN101740102B - Multi-channel flash memory chip array structure and write-in and read-out methods thereof - Google Patents
Multi-channel flash memory chip array structure and write-in and read-out methods thereof Download PDFInfo
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Abstract
The invention relates to a multi-channel flash memory chip array structure and write-in and read-out methods thereof, which overcome the defect of a slow read-write speed of flash memory data in the prior art. The multi-channel flash memory chip array structure comprises a plurality of channels consisting of flash memory chips, data buses, control buses, and chip selection signal wires, wherein each flash memory chip corresponds to one chip selection signal wire; the chip selection signal wire of each chip is independent; and all the flash memory chips in each channel share one data bus and one control bus which are independent of the other channels. The write-in method comprises the following steps of: transmitting a command and an address message to a command resolving unit through a command interface; starting a data interface management unit and a channel arbitration unit; pre-distributing the channels according to the address message by the channel arbitration unit, and transmitting the data to the channel arbitration unit and a data distribution unit; writing the data in a cache of a corresponding channel, and then starting a corresponding flash memory sequence generation module by the channel arbitration unit; and finally, writing the data into the flash memory chip. The flash memory has a fast write-read speed and high data write-in reliability.
Description
Technical field
The present invention relates to a kind of memory device and write and reading method, relate in particular to a kind of multi-channel flash memory array structure and write and reading method.
Background technology
The plurality of advantages such as flash memory is as a kind of new non-volatile memory medium, large, easy to carry, low in energy consumption with its storage density, the power failure data retention time long and shock resistance is good, very universal in field of consumer electronics.At industry and military industry field, also more and more come into one's own and welcome.In some mass data storage application scenarios, often have multi-bank flash-memory cascade or form permutation and use, to expand the handling capacity of storage space and raising data.But, because flash memory needs to carry out the wait of long period after data writing, to guarantee that data correctly write.Typically, write-once need to be waited for 200us, and maximum latency needs 700us.If according to normal operation thinking, after data writing in flash memory, just to wait for, the writing speed of data can be very slow, cannot meet actual request for utilization.
In flash memory use procedure, most crucial problem is exactly how to improve the read or write speed of data.In existing solution, a plurality of passages of also employing that have, but a public data bus, can not realize parallel processing truly; Although the use multiple bus having, and a plurality of chips in every bus, have also been hung, but the management method of a plurality of chips can not parallel processing on each passage, and in order to obtain high writing speed, sacrifice the stand-by period that writes of each chip, can make like this unreliability of data reduce.
Summary of the invention
Object of the present invention is for solving the slow defect of flash data read or write speed in prior art, provide a kind of can fast reading and writing flash memory multi-channel flash memory array structure and write and reading method.
Technical solution of the present invention is:
A kind of multi-channel flash memory chip array structure, comprise by flash chip, and a plurality of passages of the data bus being connected with flash chip, control bus and chip selection signal line formation, each flash chip is corresponding selects signal wire with a silver, the chip selection signal line of each chip is independent, and its special character is:
A public data bus and the control bus that is independent of other passages of all flash chips in described each passage.
A multi-channel flash memory chip array structure, comprises by flash chip, and a plurality of passages of the data bus being connected with flash chip, control bus and chip selection signal line formation, and its special character is:
Flash chip in described each passage carries out cascade after forming flash memory chip set, a public data bus and the control bus that is independent of other passages of all chipsets in each passage, the chip in each chipset shares control bus and chip selection signal bus.
A multi-channel flash memory wiring method, its special character is:
Comprise following steps:
1], order and address information pass to command resolution unit by command interface;
2], after command resolution unit receives orders, log-on data interface management unit and channel arbitration unit;
3], channel arbitration unit carries out the predistribution of passage according to address information, meanwhile, data interface management unit is from data-interface reading out data, and passes to channel arbitration unit and data allocations unit;
4], data allocations unit is according to the channel number that distributed, directly data write in the buffer memory of respective channel, then by channel arbitration unit, starts corresponding flash memory sequence generation module;
5], corresponding flash memory sequence generation module by the data in this passage buffer memory by with the corresponding passage of flash memory sequence generation module in public control bus and data bus write in flash chip;
6], after data allocations unit completes and writes to the data of certain passage, still have data to write fashionable, again can be again from data-interface reading out data, the data of carrying out next cycle write work.
Above-mentioned steps 5] in data while writing flash chip, comprise following steps:
501], take actual write time of first flash chip in respective channel, by control bus and data bus to first flash chip data writing;
502], utilize stand-by period that writes of current flash chip, by control bus and data bus, to next flash chip, continue data writing;
503], according to step 502] mode, utilize the stand-by period that writes of first flash chip, successively to remaining flash chip data writing in passage, until completing a secondary data, all flash chips in passage write work, and finish when stand-by period that writes of first flash chip, write operation in respective channel one week is complete;
504], return to step 501], again, to first flash chip data writing, start new write operation, until the work that writes of all data completes, circulation write operation is complete.
A multi-channel flash memory reading method, its special character is:
Comprise following steps:
1], order and address information pass to command resolution unit by command interface;
2], command resolution unit analyzes after data and order, and the order after conversion and address are passed to passage arbitration and data allocations unit;
3], by the sequence generation module of channel arbitration unit unit starting respective channel;
4], by with the corresponding passage of flash memory sequence generation module in public control bus and data bus reading out data from flash chip, leave in corresponding passage buffer memory;
5], notice passage arbitration and data allocations unit, reading out data from passage buffer memory, passes to data-interface by data interface management unit by data;
6], when data interface management unit completes after the data reading of certain passage, while still having data to read, can, again from flash chip reading out data, carry out the data reading work in next cycle again.
Tool of the present invention has the following advantages:
1, flash reading and writing speed is fast.In speed, can break through the theoretical read or write speed of flash memory, make more than the read or write speed of flash memory can reach 100MByte/s, to adapt to high-speed interface standard as PATA, SATA, 1394 and USB etc.
2, to write reliability high for data.Time response in strict accordance with flash disk operation in reliability is waited for, guarantees the reliability of data under various conditions.
Accompanying drawing explanation
Fig. 1 is flash memory chip array structure schematic diagram of the present invention.
Fig. 2 is the flash chip read-write streamline management method schematic diagram in each passage of the present invention.
Fig. 3 is flash memory chip data read-write process flow diagram of the present invention.
Embodiment
A kind of multi-channel flash memory chip array structure of the present invention, comprise by flash chip, and a plurality of passages of the data bus being connected with flash chip, control bus and chip selection signal line formation, each flash chip is corresponding selects signal wire with a silver, the chip selection signal line of each chip is independent, a public data bus and the control bus that is independent of other passages of all flash chips in each passage.When the flash chip in each passage forms flash memory chip set cascade, chipset is pieced together the data bus of 16 or 32 bit wides by 2 or 4 chips, the object that builds chipset is in order to increase bit wide, improve the writing speed of data in the unit interval, chip in chipset shares control bus and sheet selects bus, and data bus does not share.
The present invention adopts hyperchannel, i.e. the management by methods flash chip of multi-dimension array, and flash memory chip array structure is referring to Fig. 1.By multi-plate chip, form row-column configuration.Form a flash array.For example, every row has 16 flash chips, and every two flash chips are a pair of, forms the data bus of 16, and every a pair of chip shares control bus and chip selection signal line.8 pairs of flash chips are shared 16 bit data bus and a public control bus.The chip selection signal line of every pair of chip is independent.16 bit data bus and a control bus that these 8 pairs of chips are shared, and chip selection signal line corresponding to every a pair of chip forms an independently passage jointly.
Flash chip in each passage is shared a data bus and control bus by cascade, and each chip has oneself independently chip selection signal.Owing to having a plurality of chips in a bus, for example, can adopt 4 pairs of chip cascades of hyperchannel as shown in Figure 1, flash chip reading/writing method of the present invention improves total line use ratio, thereby improves the writing speed of data.In the present invention, each flash memory passage has oneself independently passage buffer memory, and independently sequence generation module, has independently DCB of byte.A plurality of like this passages can concurrent working, is independent of each other.And, by hardware logic, realize data to the automatic distribution on each passage, improved greatly the transmission speed of data.Whole flash chip array consists of a plurality of passages, passage of every increase, and the read or write speed of data doubles in theory, breaks through the limit read or write speed restriction of flash memory, when expanding memory capacity, also can increase exponentially the throughput of data.The passage number of array can be decided according to the actual requirements.In theory, if control the MCU of flash memory or the resource of FPGA enough, and front end do not have speed bottle-neck, adopts method provided by the present invention, the read or write speed of flash memory does not have the upper limit.
Flash memory array management method of the present invention realizes based on FPGA.Dotted portion in Fig. 3 has been described the administrative unit of multi-channel flash memory array structure, and wherein administrative unit comprises following components composition: the flash memory sequence generation unit of command resolution unit, data interface management unit, passage arbitration and data allocations unit, each passage buffer memory and each passage.
Corresponding oneself independently passage buffer memory and the flash memory sequence generation unit of each passage, data bus and the data bus of the corresponding flash memory of each flash memory sequence generation unit, controlling the flash chip of a line.Wherein,
Command resolution unit is responsible for and external microcontroller communicates, and the order that outside is imported into is resolved, and these command routings is arrived to the module of administrative unit inside, is the command channel of whole administrative unit.
The transmission of data is responsible in data interface management unit, is similar to the function of a dma controller.The Chinese of DMA is called direct memory access, be a kind of without CPU and directly and internal memory carry out the computer operation pattern of exchanges data, its benefit has been to reduce the burden of CPU, and has improved greatly the speed of data interaction
Data are responsible for to the distribution of passage in passage arbitration and data allocations unit.
Data-interface is responsible for from outside data-carrier store or external data bus reading out data or to external transmission data, is the data channel of whole administrative unit.Data-interface can be external memory storage, can be also the data bus of microcontroller.
Command interface can be RAM, can be also the control bus of microcontroller.
A kind of multi-channel flash memory wiring method of the present invention, includes following steps:
1], order and address information pass to command resolution unit by command interface;
2], after command resolution unit receives orders, log-on data interface management unit and channel arbitration unit;
3], channel arbitration unit carries out the predistribution of passage according to address information, meanwhile, data interface management unit is from data-interface reading out data, and passes to channel arbitration unit and data allocations unit;
4], data allocations unit is according to the channel number that distributed, directly data write in the buffer memory of respective channel, then by channel arbitration unit, starts corresponding flash memory sequence generation module;
5], corresponding flash memory sequence generation module by the data in this passage buffer memory by with the corresponding passage of flash memory sequence generation module in public control bus and data bus write in flash chip;
6], after data allocations unit completes and writes to the data of certain passage, still have data to write fashionable, again can be again from data-interface reading out data, the data of carrying out next cycle write work.
Several unit collaborative work in passage buffer memory left side, only data moving to idle channel buffer memory on responsible data-interface in Fig. 3; The flash memory sequence generation module on passage buffer memory right side is responsible for data writing to each flash chip in this passage.This two parts concurrent working, is independent of each other, and has improved greatly the throughput of data.
The sequence generation module of each passage when the chip of this passage of management, for example, has 4 chips in passage, adopt the flash chip read-write streamline management method in each passage shown in Fig. 2.After writing first chipset, allow the chip of current chipset in writing waiting status, proceed to immediately the operation of next chip, not because the first core assembly sheet makes bus idle in writing waiting status.By that analogy, when cycling, get back to first chipset after one week, just the write latency of the first core assembly sheet completes, and can carry out the operation of next round again.The method of this streamline managing chip group guarantees that the data bus of each passage is always in busy state, thereby has improved the data rate of each passage.And, because the write latency of each chip is guaranteed, also just guaranteed the reliability that data write.
Therefore, in above-mentioned step 5] in, each single pass data writes and can also comprise following steps:
501], take actual write time of first flash chip in respective channel, by control bus and data bus to first flash chip data writing;
502], utilize stand-by period that writes of first flash chip, by control bus and data bus, to next flash chip, continue data writing;
503], according to step 502] mode, utilize the stand-by period that writes of current flash chip, successively to remaining flash chip data writing in passage, until completing a secondary data, all flash chips in passage write work, and finish when stand-by period that writes of first flash chip, write operation in respective channel one week is complete;
504], return to step 501], again, to first flash chip data writing, start new write operation, until the work that writes of all data completes, circulation write operation is complete.
Described step 504] implication be after flash chip completes writing of one-period, still to have data to write fashionable, then according to step 501] to 503] loop data and write, until the work that writes of all data completes.Guaranteed that like this data bus in each passage, always in busy state, can not underspeed due to the stand-by period that writes of data, thereby improved the data rate of each passage.
Flash data read method of the present invention is contrary with above-mentioned data write-in method for flash memory.
A kind of multi-channel flash memory reading method of the present invention, includes following steps:
1], order and address information pass to command resolution unit by command interface;
2], command resolution unit analyzes after data and order, and the order after conversion and address are passed to passage arbitration and data allocations unit;
3], by channel arbitration unit, start the sequence generation module of respective channel;
4], by with the corresponding passage of flash memory sequence generation module in public control bus and data bus reading out data from flash chip, leave in corresponding passage buffer memory;
5], notice passage arbitration and data allocations unit, reading out data from passage buffer memory, passes to data-interface by data interface management unit by data;
6], when data interface management unit completes after the data reading of certain passage, while still having data to read, can, again from flash chip reading out data, carry out the data reading work in next cycle again.
In the time of reading out data, passage arbitration and data allocations unit have and can carry out data reading operation by a plurality of passages of one-shot, each passage reading out data leaves in corresponding passage buffer memory later, by passage arbitration and data allocations unit, is responsible for a data reading to front transfer.When passage is data cached be read out after, if this passage such as also has at the order to be read, can carry out read operation next time again.So when read operation, the unit on passage buffer memory right side is only responsible for data and is read from flash array, and is written in passage buffer memory.The unit collaborative work in passage buffer memory left side, is responsible for data and reads from passage buffer memory, is delivered on data-interface.Two parts remain concurrent working, do not interfere with each other.
Data write-in method for flash memory of the present invention has guaranteed that the time sequential routine of each chip is correct, and the parameter maximal value that the stand-by period that writes flash chip of guaranteeing data provides in strict accordance with flash chip operates, so just guaranteed that, in severe external environment condition, data still can be written in flash chip reliably.Concretely, exactly at previous chip when writing the state of wait, be transferred at once next position flash chip and carry out write operation, the rest may be inferred, sequential write flash chip, chip in single channel has all completed after a data write operation, and first chip in single channel carries out the flash chip of data write operation for the first time just in time in waiting for completion status, and the data that can carry out next time so again write.When having guaranteed the writing speed of data, guaranteed data write reliability.And, because the write latency of each chip has obtained sufficient assurance, also just realized the reliability that data write.And in the multi-channel flash memory that has single channel to form, single channel of the present invention of every increase just can make the read or write speed of the multi-channel flash memory that forms double than original single channel read or write speed, thereby significantly improve the read or write speed of flash memory.
Claims (3)
1. a multi-channel flash memory wiring method, is characterized in that:
Comprise following steps:
1], order and address information pass to command resolution unit by command interface;
2], after command resolution unit receives orders, log-on data interface management unit and channel arbitration unit;
3], channel arbitration unit carries out the predistribution of passage according to address information, meanwhile, data interface management unit is from data-interface reading out data, and passes to channel arbitration unit and data allocations unit;
4], data allocations unit is according to the channel number that distributed, directly data write in the buffer memory of respective channel, then by channel arbitration unit, starts corresponding flash memory sequence generation module;
5], corresponding flash memory sequence generation module by the data in this passage buffer memory by with the corresponding passage of flash memory sequence generation module in public control bus and data bus write in flash chip;
6], after data allocations unit completes and writes to the data of certain passage, still have data to write fashionable, again can be again from data-interface reading out data, the data of carrying out next cycle write work;
Command resolution unit, data interface management unit, channel arbitration unit and the collaborative work of data allocations unit, only data moving to idle channel buffer memory on responsible data-interface; Described flash memory sequence generation module is responsible for data writing to each flash chip in this passage; This two parts concurrent working;
The flash memory sequence generation module of each passage is when the chip of this passage of management, after writing first chipset, allow the chip of current chipset in writing waiting status, proceed to immediately the operation of next chip, not because the first core assembly sheet makes bus idle in writing waiting status; By that analogy, when cycling, get back to first chipset after one week, just the write latency of the first core assembly sheet completes, and can carry out the operation of next round again.
2. a kind of multi-channel flash memory wiring method according to claim 1, is characterized in that:
Described step 5] in data while writing flash chip, comprise following steps:
501], take actual write time of first flash chip in respective channel, by control bus and data bus to first flash chip data writing;
502], utilize stand-by period that writes of current flash chip, by control bus and data bus, to next flash chip, continue data writing;
503], according to step 502] mode, utilize the stand-by period that writes of first flash chip, successively to remaining flash chip data writing in passage, until completing a secondary data, all flash chips in passage write work, and finish when stand-by period that writes of first flash chip, write operation in respective channel one week is complete;
504], return to step 501], again, to first flash chip data writing, start new write operation, until the work that writes of all data completes, circulation write operation is complete.
3. a multi-channel flash memory reading method, is characterized in that:
Comprise following steps:
1], order and address information pass to command resolution unit by command interface;
2], command resolution unit analyzes after data and order, and order and address after conversion are passed to channel arbitration unit and data allocations unit;
3], by channel arbitration unit, start the sequence generation module of respective channel;
4], by with the corresponding passage of flash memory sequence generation module in public control bus and data bus reading out data from flash chip, leave in corresponding passage buffer memory;
5], notice channel arbitration unit and data allocations unit, reading out data from passage buffer memory, passes to data-interface by data interface management unit by data;
6], when data interface management unit completes after the data reading of certain passage, while still having data to read, can, again from flash chip reading out data, carry out the data reading work in next cycle again;
During reading out data, channel arbitration unit and data allocations unit a plurality of passages of one-shot carry out data reading operation, each passage reading out data leaves in corresponding passage buffer memory later, by channel arbitration unit and data allocations unit, is responsible for a data reading to front transfer; When passage is data cached be read out after, if this passage such as also has at the order to be read, can carry out again read operation next time; So when read operation, flash memory sequence generation module is only responsible for data and is read from flash array, and is written in passage buffer memory; Command resolution unit, data interface management unit, channel arbitration unit and the collaborative work of data allocations unit, be responsible for data and read from passage buffer memory, is delivered on data-interface; Two parts remain concurrent working, do not interfere with each other.
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| TWI520152B (en) * | 2013-03-01 | 2016-02-01 | 慧榮科技股份有限公司 | Data storage device and flash memory control method |
| IN2013MU02016A (en) * | 2013-06-13 | 2015-06-05 | Mediatek Inc | |
| CN105892944B (en) * | 2016-03-30 | 2019-11-12 | 深圳忆联信息系统有限公司 | A kind of information processing method and electronic equipment |
| CN105975416B (en) * | 2016-04-28 | 2018-11-20 | 西安电子科技大学 | Multichannel friction speed data Transmission system based on FPGA |
| CN106502581B (en) * | 2016-09-30 | 2019-05-28 | 华为技术有限公司 | Flash controller, flash memory control method and solid state hard disk |
| CN106528465B (en) * | 2016-11-10 | 2019-08-02 | 郑州云海信息技术有限公司 | A kind of Nand Flash controller and method |
| CN107766270B (en) * | 2017-10-20 | 2020-05-26 | 深圳市风云实业有限公司 | Data reading management method and device for PCIe (peripheral component interface express) equipment |
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| CN108563399B (en) * | 2018-03-13 | 2020-02-14 | 中山市江波龙电子有限公司 | Data reading method and device of storage device, terminal device and storage medium |
| CN108932204A (en) * | 2018-06-13 | 2018-12-04 | 郑州云海信息技术有限公司 | A kind of multi-channel flash memory storage system |
| US10777232B2 (en) * | 2019-02-04 | 2020-09-15 | Micron Technology, Inc. | High bandwidth memory having plural channels |
| CN114637711A (en) * | 2022-03-31 | 2022-06-17 | 深圳市洲明科技股份有限公司 | Chip control method, control data transmission method and device and computer equipment |
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Address after: 710065 Xi'an high tech Zone, Jin Industrial Road, No., No. C Venture Park, No. 8, Patentee after: Xi'an Keyway Technology Co.,Ltd. Address before: 710077 Xi'an high tech Zone, Jin Industrial Road, No., No. C Venture Park, No. 8, Patentee before: Xi'an Qivi Test & Control Technology Co., Ltd. |
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Address after: 710077 Xi'an high tech Zone, Jin Industrial Road, No., No. C Venture Park, No. 8, Patentee after: Xi'an Qiwei Technology Co. Ltd. Address before: 710065 Xi'an high tech Zone, Jin Industrial Road, No., No. C Venture Park, No. 8, Patentee before: Xi'an Keyway Technology Co.,Ltd. |
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Effective date of registration: 20170920 Address after: 710077 Xi'an high tech Zone, Jin Industrial Road, No., No. C Venture Park, No. 8, Co-patentee after: Beijing Polytechnic Leike Electronic Information Technology Co., Ltd. Patentee after: Xi'an Qiwei Technology Co. Ltd. Address before: 710077 Xi'an high tech Zone, Jin Industrial Road, No., No. C Venture Park, No. 8, Patentee before: Xi'an Qiwei Technology Co. Ltd. |
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Effective date of registration: 20211019 Address after: 710117 No. a1-134, building 4, phase II, information industry park, No. 526, Xitai Road, high tech Zone, Xi'an, Shaanxi Province Patentee after: Xi'an siduoruizhi Information Technology Co.,Ltd. Address before: 710077, No. 8, C zone, pioneering research and Development Park, 69 Kam Yip Road, hi tech Zone, Shaanxi, Xi'an Patentee before: XI'AN KEYWAY TECHNOLOGY Co.,Ltd. Patentee before: BIT RACO ELECTRONIC INFORMATION TECHNOLOGY Co.,Ltd. |
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Effective date of registration: 20211130 Address after: 710117 a2-02, building 4, phase II, information industry park, No. 526, banxitai Road, Xinglong Street, high tech Zone, Xi'an, Shaanxi Province Patentee after: Leizhi digital system technology (Xi'an) Co.,Ltd. Address before: 710117 No. a1-134, building 4, phase II, information industry park, No. 526, Xitai Road, high tech Zone, Xi'an, Shaanxi Province Patentee before: Xi'an siduoruizhi Information Technology Co.,Ltd. |