CN102023943B - Method for controlling as well as reading and writing NandFlash by four-path IO (input-output) interface - Google Patents
Method for controlling as well as reading and writing NandFlash by four-path IO (input-output) interface Download PDFInfo
- Publication number
- CN102023943B CN102023943B CN 201010573113 CN201010573113A CN102023943B CN 102023943 B CN102023943 B CN 102023943B CN 201010573113 CN201010573113 CN 201010573113 CN 201010573113 A CN201010573113 A CN 201010573113A CN 102023943 B CN102023943 B CN 102023943B
- Authority
- CN
- China
- Prior art keywords
- interface
- nandflash
- data
- responsible
- protocol
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Information Transfer Systems (AREA)
Abstract
The invention relates to a method for controlling and reading and writing NandFlash by a four-path IO (input-output) interface. The method comprises: a command resolver is arranged between a QS (quintuple serial) interface and an NF (NandFlash) interface, a QS interface protocol is converted into the original NF interface protocol, and the QS interface is communicated with a main controller. The invention has the following beneficial effects: 1. the QS interface of quintuplet lines replaces the original complex NF interface, thus lowering the complexity of the NandFlash interface, and expanding the use range of the NandFlash; 2. the command resolver is arranged between the QS interface and the NF interface, and thus the QS interface can be introduced in without changing the existing NandFlash design; and 3. the QS interface protocol is formulated, thus realizing all functions of the original NF protocol while realizing a new interface.
Description
Technical field
The present invention relates to the chip design field, especially a kind of method of controlling and read and write NandFlash by four-way IO interface.
Background technology
Nand type Flash (NandFlash) is a kind of widely used nonvolatile memory NVM (Non-VolatileMemory), and its maximum characteristics are that capacity is large.At present, mass-memory unit is all NandFlash as the memory bank that uses on USB flash disk, SD card.
Although NandFlash has advantage capacious, its interface is more complicated.Together with Data-Link and control line, NandFlash needs at least 16 could be by main controller controls with connection.
Following table has listed control and the data-interface of typical N andFlash, and its effect separately has been described take K9F series NandFlash as example.
I: the representative data direction is input;
O: the representative data direction is output;
I/O: the representative data direction is two-way time-sharing multiplex.
The NandFlash interface is realized all equipment operatings according to a cover agreement, and NandFlash can be completed by 14 orders as all operations of example take K9F series, specifically sees the following form:
| Function | 1st Cycle | 2nd Cycle | Accentable Command during Busy |
| Read | 00h | 30h | |
| Read for Copy Back | 00h | 35h | |
| Read ID | 90h | - | |
| Reset | FFh | - | ○ |
| Page Program | 80h | 10h | |
| Two-Plane Page Program(3) | 80h---11h | 81h---10h | |
| Copy-Back Program | 85h | 10h | |
| Two-Plane Copy-Back Program(3) | 85h---11h | 81h---10h | |
| Block Erase | 60h | D0h | |
| Two-Plane Block Erase | 60h---60h | D0h | |
| Random Data Input(1) | 85h | - | |
| Random Data Output(1) | 05h | E0h | |
| Read Status | 70h | ○ | |
| Read EDC Status(2) | 7Bh | ○ |
Summary of the invention
Purpose of the present invention will solve the problems of the technologies described above just, and a kind of method of controlling and read and write NandFlash by four-way IO interface is provided.
The present invention solves the technical scheme that its technical matters adopts: this method of controlling and read and write NandFlash by four-way IO interface, a kind of command analysis device is set between QS interface and NF interface, the QS interface protocol is converted to original NF interface protocol, and adopts the QS interface with the master controller communication.
As preferably, described QS interface is a kind of 5 mouthfuls of line serial line interfaces.
As preferably, the command analysis device is made of two 4 latchs, code translator, data latches, WE/RE clock generator and auxiliary circuits; Two 4 latchs are responsible for the 8 bit parallel data that become the NF interface to need to 4 bit serial data-switching of QS interface under the clock controller effect; Code translator is responsible for 8 bit parallel data are resolved, to differentiate the various command pattern; Data latches is responsible for guaranteeing that the state of data bus remains unchanged in needs, prevent that the operation of other orders from destroying the data mode of data bus; The WE/RE clock generator is responsible for producing the needed WE/RE sequential of NF interface.
The effect that the present invention is useful is:
1, substitute the NF interface of original complexity with the QS interface of 5 mouthfuls of lines, reduced the complicacy of NandFlash interface, enlarged the usable range of NandFlash.
2, introduce the command analysis device between QS interface and NF interface, made the design that need not to change existing NandFlash can introduce the QS interface.
3, formulate the agreement of QS interface, when realizing new interface, realized the repertoire of original NF agreement.
Description of drawings
Fig. 1 is schematic flow sheet of the present invention;
Fig. 2 is command analysis device block diagram of the present invention.
Embodiment
The invention will be further described below in conjunction with drawings and Examples:
This method of controlling and read and write NandFlash by four-way IO interface of the present invention, substitute the original complex interface (hereinafter being called for short the NF interface) of NandFlash with a kind of 5 mouthfuls of line serial line interfaces (hereinafter being called for short the QS interface), and adopt with the QS interface with the master controller communication.Benefit is, has simplified Interface design, has reduced the IO expense of using NandFlash.Design and set up a kind of command analysis device between QS interface and NF interface, be responsible for the QS interface protocol is converted to original NF interface protocol.The benefit of setting up the command analysis device is, needn't revise the former design of NandFlash, can realize the application of new interface.For the QS interface, design one cover standard agreement is to cover the repertoire of original NF agreement.So that the address is programmed for 0x55 as example as the content of 0x01008000, realization flow as shown in Figure 1.
1, the command analysis device is introduced (block diagram as shown in Figure 2) in detail
The command analysis device is responsible for the QS interface of 5 passages with the protocol conversion of NandFlash standard NF interface.The command analysis device mainly is made of two 4 latchs, code translator, data latches, WE/RE clock generator and auxiliary circuits.
● 4 latchs
Two 4 latchs are responsible for the 8 bit parallel data that become the NF interface to need to 4 bit serial data-switching of QS interface under the clock controller effect.
● code translator
Code translator is responsible for 8 bit parallel data are resolved, to differentiate the various command pattern.
● data latches
Data latches is responsible for guaranteeing that the state of data bus remains unchanged in needs, prevent that the operation of other orders from destroying the data mode of data bus.
● the WE/RE clock generator
The WE/RE clock generator is responsible for producing the needed WE/RE sequential of NF interface.
2, the QS agreement is introduced in detail
For satisfying the characteristics of QS interface work in series, can also cover all functions of original NF interface protocol simultaneously, the present invention has designed the QS interface protocol.The QS interface protocol is comprised of 15 orders, and being divided into is two classes.One class is the order of signal handling type, and another kind of is the order of data manipulation type.
● the order of signal handling type
The order of signal handling type is responsible for hardware signal is driven, and the hardware signal of demand motive is CEx, WP, ALE, CLE.
The order of signal handling type is divided into four sections, is respectively type codes 1, type codes 2, signal code, numeric data code.Every segment data length is 4.
The content of type codes 1 is fixed as 0xf; The content of type codes 2 is fixed as 0x8.The combination 0xf8 of two type codes represents that this order is the order of signal handling class.
Signal code length is 4, and object is controlled in representative, and valid data are 0x0,0x1, and 0x2,0x3, concrete meaning sees the following form.
Numeric data code length is 4, when controlling object and be CEx, the number of significant digit of numeric data code is decided (to suppose to have 3 CE lines according to the number of CE signal, the numeric data code effective length is 3), bits per inch represents the high-low level state (1 is high level, and 0 is low level) of every CE data line according to the data of code.When controlling object for other signals, numeric data code only lowest order is effective, the high-low level state of its data representation signal line (1 is high level, and 0 is low level).For example concrete meaning sees the following form.
The concrete form of signal handling order is:
● the order of data manipulation type
The order of data manipulation type is mainly to complete reading and writing to the NandFlash data, the function such as wipe.The instruction of data manipulation type comprises totally 14 orders (concrete form see below form), 14 command functions of corresponding NF interface protocol respectively.Concrete method is, increases 0xf before original order, and the type codes that 0x7 is two 4 is with expression order kind; Simultaneously, each 8 bit field of NF protocol command are changed into two 4 bit fields.Such benefit is, after the command analysis device parses concrete order, directly by code translator the IO bus that latchs respectively data in two 4 latchs and send to NF, can be identified by the NF agreement.
In addition to the implementation, the present invention can also have other embodiments.All employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop on the protection domain of requirement of the present invention.
Claims (1)
1. one kind is passed through the method that NandFlash was controlled and read and write to four-way IO interface, it is characterized in that: a kind of command analysis device is set between QS interface and NF interface, the QS interface protocol is converted to original NF interface protocol, and adopts the QS interface with the master controller communication; Described QS interface is a kind of 5 mouthfuls of line serial line interfaces, and described NF interface is the original complex interface of NandFlash; The command analysis device is made of two 4 latchs, code translator, data latches, WE/RE clock generator and auxiliary circuits; Two 4 latchs are responsible for the 8 bit parallel data that become the NF interface to need to 4 bit serial data-switching of QS interface under the clock controller effect; Code translator is responsible for 8 bit parallel data are resolved, to differentiate the various command pattern; Data latches is responsible for guaranteeing that the state of data bus remains unchanged in needs, prevent that the operation of other orders from destroying the data mode of data bus; The WE/RE clock generator is responsible for producing the needed WE/RE sequential of NF interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010573113 CN102023943B (en) | 2010-11-25 | 2010-11-25 | Method for controlling as well as reading and writing NandFlash by four-path IO (input-output) interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010573113 CN102023943B (en) | 2010-11-25 | 2010-11-25 | Method for controlling as well as reading and writing NandFlash by four-path IO (input-output) interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102023943A CN102023943A (en) | 2011-04-20 |
| CN102023943B true CN102023943B (en) | 2013-06-19 |
Family
ID=43865256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010573113 Active CN102023943B (en) | 2010-11-25 | 2010-11-25 | Method for controlling as well as reading and writing NandFlash by four-path IO (input-output) interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102023943B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790308A (en) * | 2005-12-27 | 2006-06-21 | 北京中星微电子有限公司 | Multi-channel flash memory transmission controller, chip and storage device |
| CN101740102A (en) * | 2008-11-11 | 2010-06-16 | 西安奇维测控科技有限公司 | Multi-channel flash memory chip array structure and write-in and read-out methods thereof |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4550439B2 (en) * | 2003-02-28 | 2010-09-22 | 東芝メモリシステムズ株式会社 | ECC controller |
| KR100560767B1 (en) * | 2003-09-02 | 2006-03-13 | 삼성전자주식회사 | System including insertable and removable storage and control method thereof |
-
2010
- 2010-11-25 CN CN 201010573113 patent/CN102023943B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790308A (en) * | 2005-12-27 | 2006-06-21 | 北京中星微电子有限公司 | Multi-channel flash memory transmission controller, chip and storage device |
| CN101740102A (en) * | 2008-11-11 | 2010-06-16 | 西安奇维测控科技有限公司 | Multi-channel flash memory chip array structure and write-in and read-out methods thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102023943A (en) | 2011-04-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100843280B1 (en) | Memory system and data transfer method thereof | |
| CN101273413B (en) | Portable data memory using single layer unit and multi-layer unit flash memory | |
| US8140738B2 (en) | Flash memory interface device | |
| CN101349963B (en) | Solid state disk controller and data processing method thereof | |
| CN101241752B (en) | Memory card and memory system having the same | |
| CN109697024B (en) | Memory system and operating method thereof | |
| CN101635172B (en) | Non-volatile memory devices and programming methods for the same | |
| JP5787444B2 (en) | Programmable memory controller | |
| US9710191B1 (en) | Rapid memory buffer write storage system and method | |
| CN101226456A (en) | Method and system for a serial peripheral interface | |
| CN102096647A (en) | Multi-chip memory system and related data transfer method | |
| CN110058799A (en) | Memory device and the method for operating memory device | |
| CN109753232A (en) | The operating method of storage system and storage system | |
| CN102708058A (en) | Non-volitile memory device for performing ftl and method thereof | |
| CN110489360A (en) | The operating method of Memory Controller and the Memory Controller | |
| TWI425515B (en) | Data storage device and data writing method of a flash memory | |
| CN102968396B (en) | Dedicated data transmission module from Flash chip to sram chip | |
| TW200933646A (en) | Semiconductor memory device suitable for interconnection in a ring topology | |
| TW202135059A (en) | Data storage device and data processing method | |
| US20170147235A1 (en) | Memory system controlling interleaving write to memory chips | |
| TWI416523B (en) | Method for writing fail retry for a non-volatile memory, non-volatile memory, controller, and memory card | |
| CN103106155A (en) | Storage storing device, storage controller and data transmission method thereof | |
| CN102023943B (en) | Method for controlling as well as reading and writing NandFlash by four-path IO (input-output) interface | |
| CN101266828A (en) | Mixed flash memory device and its operation method | |
| CN101593556A (en) | The method that nonvolatile semiconductor memory member is programmed |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: The city of Hangzhou in West Zhejiang province 311121 No. 998 Building 9 East Sea Park Patentee after: Hangzhou Shengyuan Chip Technique Co., Ltd. Address before: 310012, room 17, building 176, 203 Tianmu Mountain Road, Hangzhou, Zhejiang, Xihu District Patentee before: Hangzhou Shengyuan Chip Technique Co., Ltd. |
|
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: The city of Hangzhou in West Zhejiang province 311121 No. 998 Building 9 East Sea Park Patentee after: HANGZHOU SYNODATA SECURITY TECHNOLOGY CO., LTD. Address before: The city of Hangzhou in West Zhejiang province 311121 No. 998 Building 9 East Sea Park Patentee before: Hangzhou Shengyuan Chip Technique Co., Ltd. |