CN101266828A - Mixed flash memory device and its operation method - Google Patents
Mixed flash memory device and its operation method Download PDFInfo
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- CN101266828A CN101266828A CNA2008100863000A CN200810086300A CN101266828A CN 101266828 A CN101266828 A CN 101266828A CN A2008100863000 A CNA2008100863000 A CN A2008100863000A CN 200810086300 A CN200810086300 A CN 200810086300A CN 101266828 A CN101266828 A CN 101266828A
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Abstract
The invention discloses a mixed type flesh memory equipment, comprising: a microcontroller connected with HBUS for receiving write data of a host; and a memory module which is connected with the microcontroller and comprises a first type flesh memory and a second type flesh memory. Wherein, when the write data is more than or less than a particular data quantity, the write data is written into a first temporary block of the first type flesh memory, and when the write data is less than or more than a particular data quantity, the write data is written into a second temporary block of the second type flesh memory. In the invention, when the microcontroller processes an action of replacing the temporary block, a known sort program and a write program without using the block are not processed, so as to greatly improve an efficiency of the memory module.
Description
Technical field
The present invention relates to a kind of flash memory device (flash memory storage device) and control method thereof, and be particularly related to a kind of mixed type (hybrid) flash memory device and control method thereof.
Background technology
As everyone knows, flash memory (flash memory) have shock resistance (shock), non-volatile (nonvolatile), with advantage such as high storage density.Therefore, the flash memory collocation formed flash memory device of control circuit (flashmemory storage device) is used widely.For example, USB flash disk (thumb drive), compact flash memory storage (compact flash, abbreviation CF card), safety digital storage device (secure digital is called for short the SD card), multimedia card memory storage (multi media card is called for short mmc card) or the like.
In general, Sheffer stroke gate flash memory on the market (Nand-Flash memory) can be divided into two kinds, that is, single level memory cell type Sheffer stroke gate flash memory (Signal Level Cell Nand-Flash, hereinafter to be referred as SLC type flash memory) and many level memory cell type Sheffer stroke gate flash memory (Multi Level Cell Nand-Flash is hereinafter to be referred as MLC type flash memory).So-called SLC type flash memory is exactly can a position of access (bit) in single memory cell (memory cell); Otherwise MLC type flash memory is exactly can the more than one position of access in single memory cell.
Above-mentioned two kinds of flash memories are to utilize different manufacture method manufacturings, though all have non-volatile characteristic, its treatment efficiency and characteristic still have significant difference.Below summarize the difference of SLC type flash memory and MLC type flash memory.
(I) each page or leaf (Page) of SLC type flash memory has the characteristic that can repeat to write (multi-write) data, and can be write by any number of pages.(II) correctness (reliability andmaintainability) that writes of SLC type flash data is very high, does not therefore need too complicated bug patch code (error correction code).(III) serviceable life of SLC type flash memory (available) is long.(IV) block erase time of SLC type flash memory (block erase time) and page or leaf write time (page programming time) are shorter.(V) price of SLC type flash memory is higher.
(I) each page or leaf (Page) of MLC type flash memory only once writes the characteristic of data, and must be write in regular turn by low number of pages.(II) therefore the error rate height that writes of MLC type flash data needs complicated bug patch code (error correction code) come debug.(III) serviceable life of MLC type flash memory is short.(IV) the block erase time of MLC type flash memory and page or leaf write time are longer.(V) price of MLC type flash memory is lower, and MLC type flash memory has higher data density (high density) in equal area.
Please refer to Figure 1A, it is depicted as known flash memory device Organization Chart.Comprise a microcontroller (micro controller) 20 and memory module (memory modular) 40 in the flash memory device 10.In general, main frame (host, not shown) then can utilize a host bus (host bus) 22 to come data in the access flash memory device 10.Certainly, host bus 22 can be a compact flash memory storage (compactflash, abbreviation CF) bus, safety digital storage device (secure digital, abbreviation SD) bus, multimedia card memory storage (multi media card, abbreviation MMC) bus, USB (universal serial bus) (universalserial bus is called for short USB) or IEEE1394 bus etc.
Moreover when main frame during with writing data into memory module 40, microcontroller 20 can send one and write and instruct to memory module 40 and will write writing data into memory module 40.Otherwise during data in main frame reads memory module 40, microcontroller 20 can send a reading command to memory module 40, therefore, memory module 40 can the output reading of data to microcontroller 20 and export above-mentioned reading of data.
Moreover, please refer to Figure 1B and Fig. 1 C, it is depicted as the memory module synoptic diagram in the known flash memory device.Because the difference of SLC type flash memory and MLC type flash memory, therefore, the memory module 40 in the known flash memory device 10 all is made up of the flash memory of phase homotype.That is to say that shown in Figure 1B, memory module 40 can be that a plurality of SLC type flash memory 42-1～42-N forms.Perhaps, shown in Fig. 1 C, memory module 40 can be that a plurality of MLC type flash memory 44-1～44-N forms.
No matter memory module 40 is formed or is made up of MLC type flash memory 44-1～44-N by SLC type flash memory 42-1～42-N, in memory module 40, can also be divided into a lot of block (block), comprise a plurality of pages or leaves (Page) in each block again.Therefore, one memory map table (memory mapping table) is arranged in the microcontroller 20, pointer (pointer) is arranged in the above-mentioned memory map table, its record logical block addresses (logical block address, hereinafter to be referred as LBA) with physical blocks address (physicalblock address is hereinafter to be referred as PBA) between relation.In general, the read write command that main frame sends all is the data of the specific LBA of read-write, therefore utilizes memory map table promptly can determine PBA actual in the memory module 40, and the data among the PBA are read or write.
Please refer to Fig. 2, it is the memory mapped hoist pennants.For instance, suppose that main frame sends reading command and desires to read data in the LBA 0, according to the memory map table in the microcontroller 20 35, the address of data actual storage is at the PBA 5 of memory module 40, therefore, data among the PBA 5 of memory module 40 can be read out, and output flash memory device 10 is to main frame.
Because the difference of SLC type flash memory and MLC type flash memory, the therefore flash memory device 10 finished of structure also difference to some extent when write activity.Below illustrate: supposing has four pages or leaves (Page) in each block, that is zero page (Page 0), first page (Page 1), second page (Page 2), the 3rd page (Page3).Moreover microcontroller 20 can select at least one not use block (freeblock) as the temporary transient block (log block) that writes data in memory module 40.
Please refer to Fig. 3 A～G, it is depicted as by the constructed synoptic diagram of flash memory device when writing data of SLC type flash memory.Suppose that (I) main frame sends a write command and begins to write two pages data D1 ', D2 ' to LBA 0 and by first page (Page 1); (II) main frame sends a write command to LBA 0 and begun to write the data D0 ' of one page by zero page (Page 0); And (III) main frame sends a write command and begins to write four pages data D7 ', D8 ', D9 ', D10 ' to LBA 3 and by the 3rd page (Page 3).
As shown in Figure 3A, before flash memory device is not received write command as yet, by the memory map table in the microcontroller 20 35 as can be known, LBA 0 can correspond to the PBA 1 of memory module 40, and zero page (Page 0) has been stored D0 data, first page (Page 1) and stored that D1 data, second page (Page 2) have been stored the D2 data, the 3rd page (Page 3) have stored the D3 data among the PBA1; LBA 3 can correspond to the PBA 7 of memory module 40, and zero page (Page 0) has been stored D4 data, first page (Page 1) and stored that D5 data, second page (Page 2) have been stored the D6 data, the 3rd page (Page 3) have stored the D7 data among the PBA 7; LBA 4 can correspond to the PBA 4 of memory module 40, and zero page (Page 0) has been stored D8 data, first page (Page 1) and stored that D9 data, second page (Page 2) have been stored the D10 data, the 3rd page (Page 3) have stored the D11 data among the PBA 4.Moreover above-mentioned memory module 40 has two temporary transient blocks (log block), and the first temporary transient block (log block1) is set at PBA 5, the second temporary transient blocks (log block 2) and is set at PBA 3; And PBA0, PBA2 and PBA6 are and do not use block (free block).
Shown in Fig. 3 B, flash memory device receives that (I) main frame sends a write command and begins to write two pages data D1 ', D2 ' to LBA 0 and by first page (Page 1).At this moment, these data (D1 ', D2 ') can be placed on the first temporary transient block (log block 1) earlier.Because SLC type flash memory can be write by any number of pages, therefore, data D1 ', D2 ' can be written into first page (Page 1) and second page (Page 2) of the first temporary transient block (log block 1).
Shown in Fig. 3 C, flash memory device receives that (II) main frame sends a write command to LBA 0 and begun to write the data D0 ' of one page by zero page (Page 0).Because the data that write of LBA 0 are placed in the first temporary transient block (log block 1) and SLC type flash memory can be write by any number of pages, so data D0 ' can be placed on the zero page (Page 0) of the first temporary transient block (log block 1).
When flash memory device receives that (III) main frame sends a write command and begins to write four pages data D7 ', D8 ', D9 ', D10 ' to LBA 3 and by the 3rd page (Page 3).Clearly, D7 ' data must write the 3rd page of LBA 3 (Page 3), and D8 ', D9 ', D10 ' must write LBA4 zero page (Page 0), first page (Page 1) and second page (Page 2).
Therefore, shown in Fig. 3 D, earlier the data D7 ' of LBA 3 is write the 3rd page (Page 3) of the second temporary transient block (log block2).At this moment, because memory module 40 has not had spendable temporary transient block (log block), so, must carry out and change temporary transient block action (flush out log block).That is to say, do not use block (free block) to be used as the first temporary transient block (log block 1) by seeking in the memory module 40 once more.
Therefore, shown in Fig. 3 E, microcontroller 20 can carry out a consolidation procedure (mergingprocedure) 46 earlier.So-called consolidation procedure 46 is exactly by taking out data D3 in PBA 1 the 3rd page (Page 3), then, data in the data D3 and the first temporary transient block (log block 1) are merged, make zero page (Page 0) storage data D0 ' in the temporary area piece of winning (log block 1), first page (Page 1) storage data D1 ', second page (Page 2) storage data D2 ', storage data D3 in the 3rd page (Page 3).
Then, shown in Fig. 3 F, the LBA in the memory map table 35 0 is corresponded to the PBA 5 of memory module 40.Therefore, the first old temporary transient block (log block 1) can become LBA0.Then, microcontroller 20 is not selected one and is become the first new temporary transient block (log block 1) by a plurality of the use in the block, and for example, PBA 0.And owing to all data among the former PBA 1 have been substituted, utilize block erase instruction (block erase command) and to make PBA 1 become with the data erase among the PBA 1 and do not use block (free block) and finish the temporary transient block action of replacing.
Shown in Fig. 3 G, because the new first temporary transient block (log block 1) forms, therefore, D8 ', D9 ', D10 ' can write new first temporary transient block (the log block 1) zero page (Page 0), first page (Page1) and second page (Page 2).
Please refer to Fig. 4 A～4G, it is by the constructed synoptic diagram of flash memory device when writing data of MLC type flash memory.Suppose that (I) main frame sends a write command and begins to write two pages data D1 ', D2 ' to LBA 0 and by first page (Page 1); (II) main frame sends a write command to LBA 0 and begun to write the data D0 ' of one page by zero page (Page 0); And (III) main frame sends a write command and begins to write four pages data D7 ', D8 ', D9 ', D10 ' to LBA 3 and by the 3rd page (Page 3).
Shown in Fig. 4 A, before flash memory device is not received write command as yet, by the memory map table in the microcontroller 20 as can be known, LBA 0 can correspond to the PBA 1 of memory module 40, and zero page (Page 0) has been stored D0 data, first page (Page 1) and stored that D1 data, second page (Page 2) have been stored the D2 data, the 3rd page (Page 3) have stored the D3 data among the PBA 1; LBA 3 can correspond to the PBA 7 of memory module 40, and zero page (Page 0) has been stored D4 data, first page (Page 1) and stored that D5 data, second page (Page 2) have been stored the D6 data, the 3rd page (Page 3) have stored the D7 data among the PBA 7; LBA 4 can correspond to the PBA 4 of memory module 40, and zero page (Page 0) has been stored D8 data, first page (Page 1) and stored that D9 data, second page (Page 2) have been stored the D10 data, the 3rd page (Page 3) have stored the D11 data among the PBA 4.Moreover above-mentioned memory module 40 has two temporary transient blocks (log block), and the first temporary transient block (log block 1) is set at PBA 5, the second temporary transient blocks (log block 2) and is set at PBA 3; And PBA0, PBA2 and PBA6 are and do not use block (free block).
Shown in Fig. 4 B, flash memory device receives that (I) main frame sends a write command and begins to write two pages data D1 ', D2 ' to LBA 0 and by first page (Page 1).At this moment, these data D1 ', D2 ' can be placed on the first temporary transient block (log block 1).Because the number of pages of MLC type flash memory must write in regular turn, therefore, data D1 ', D2 ' can be written into the zero page (Page 0) and first page (Page 1) of the first temporary transient block (log block 1).
Shown in Fig. 4 C, flash memory device receives that (II) main frame sends a write command to LBA 0 and begun to write the data D0 ' of one page by zero page (Page 0).Because the data that write of LBA 0 are placed in the first temporary transient block (log block 1) and MLC type flash memory must write in regular turn, so data D0 ' is placed on second page (Page 2) of the first temporary transient block (log block 1).
When flash memory device receives that (III) main frame sends a write command and begins to write four pages data D7 ', D8 ', D9 ', D10 ' to LBA 3 and by the 3rd page (Page 3).Clearly, D7 ' data must write the 3rd page of LBA 3 (Page 3), and D8 ', D9 ', D10 ' must write LBA4 zero page (Page 0), first page (Page 1) and second page (Page 2).
Therefore, shown in Fig. 4 D, earlier the data D7 ' of LBA 3 is write the zero page (Page 0) of the second temporary transient block (log block2).At this moment, because memory module 40 has not had spendable temporary transient block (log block), so, must carry out and change temporary transient block action (flush out log block).That is to say, do not use block (free block) to be used as the first temporary transient block (log block 1) by seeking in the memory module 40 once more.
Because the data number of pages offset in the first temporary transient block (log block 1) is true, therefore, microcontroller 20 can carry out an ordering and consolidation procedure (merging and sorting procedure) 47 earlier, and one does not use block write-in program (write to free block procedure) 48.
Shown in Fig. 4 E, ordering and consolidation procedure 47 promptly are to receive data D3 among the PBA 1 and data D1 ', D2 ', the D0 ' in the first temporary transient block (log block 1), and become D0 ', D1 ', D2 ', D3 according to the rank order and the merging of number of pages.And do not use block write-in program 48 promptly is the data that ordering and consolidation procedure are finished to be write do not use in the block, and for example PBA 6.
Then, shown in Fig. 4 F, the LBA in the memory map table 35 0 is corresponded to the PBA 6 of memory module 40.Therefore, microcontroller 20 is not selected one and is become the first new temporary transient block (log block 1) by a plurality of use in the block, and for example, PBA 0.And since among former PBA 1 and the PBA 5 all data be substituted, utilize two block erase instructions (block erase command) and to make PBA 1 and PBA 5 become not use block (free block) and finish and change temporary transient block and move the data erase among PBA1 and the PBA 5.
Shown in Fig. 4 G, because the new first temporary transient block (log block 1) forms, therefore, D8 ', D9 ', D10 ' can write new first temporary transient block (the log block 1) zero page (Page 0), first page (Page1) and second page (Page 2).
From the above, because the number of pages of MLC type flash memory must write in regular turn, therefore must carry out an ordering and consolidation procedure 47 and blank block write-in programs 48 carrying out when changing temporary transient block action microcontroller 20.Moreover, because the number of pages of SLC type flash memory can write arbitrarily, therefore change and only utilize a consolidation procedure 46 to get final product when temporary transient block moves in execution.Briefly, MLC type flash memory many than SLC type flash memory complex in the processing that writes data.
Summary of the invention
The present invention proposes a kind of mixed flash memory device, comprises: a microcontroller is connected to a host bus and writes data in order to receive one of a main frame; And a memory module is connected to above-mentioned microcontroller, and above-mentioned memory module comprises at least one first type flash memory and at least one second type flash memory; Wherein, when above-mentioned when writing size of data, the above-mentioned data that write are write when above-mentioned, the above-mentioned data that write are write one second temporary transient block in the above-mentioned second type flash memory less than a particular data amount.
The present invention more proposes a kind of control method of mixed flash memory device, above-mentioned mixed flash memory device comprises a memory module of being made up of at least one first type flash memory and at least one second type flash memory, and above-mentioned control method comprises the following steps: to receive by what a main frame sent and one writes data; When above-mentioned when writing size of data, the above-mentioned data that write are write one first temporary transient block in the above-mentioned first type flash memory less than a particular data amount; And, when above-mentioned when writing size of data, the above-mentioned data that write are write one second temporary transient block in the above-mentioned second type flash memory greater than above-mentioned particular data amount.
As shown in the above description, among the present invention, when the temporary transient block of microcontroller execution replacing moves, need not carry out known sequencer program and not use the block write-in program, therefore can significantly improve the efficient of memory module.
Moreover the present invention is not limited to the mixed flash memory device that SLC type and MLC type flash memory are formed.Those skilled in the art know, no matter SLC type and MLC type flash memory all can further be categorized as the first estate (first grade) product and second grade (second grade) product after manufacturing is finished.The flash memory life-span of the first estate is long and quality is better, that is to say, the flash memory of the first estate allows the number of times that writes repeatedly and read more and data error rate is low; Otherwise the shorter inferior quality of flash memory life-span of second grade that is to say, allows the number of times that writes repeatedly and read less and data error rate is low.
That is to say that the present invention also can utilize the mixed flash memory device that flash memory combined of different brackets.When the size that writes data (size) during, then will write the flash memory that data write the first estate less than above-mentioned particular data amount; Otherwise,, then will write the flash memory that data write second grade when the size that writes data (size) during greater than above-mentioned particular data amount.Therefore, the flash memory of second grade write the indegree of writing that indegree can be less than the first estate, and ensure the life-span of above-mentioned mixed flash memory device.
Description of drawings
Figure 1A is known flash memory device Organization Chart.
Figure 1B, 1C are the memory module synoptic diagram in the known flash memory device.
Fig. 2 is the memory mapped hoist pennants.
Fig. 3 A～3G is by the constructed synoptic diagram of flash memory device when writing data of SLC type flash memory.
Fig. 4 A～4G is by the constructed synoptic diagram of flash memory device when writing data of MLC type flash memory.
Figure.
Fig. 5 is a mixed flash memory device Organization Chart of the present invention.
Fig. 6 A～6I is depicted as the synoptic diagram of mixed flash memory device of the present invention when writing data.
Embodiment
Please refer to Fig. 5, it is a mixed flash memory device Organization Chart of the present invention.Comprise a microcontroller 120 and memory module 140 in the flash memory device 100.Wherein, comprise SLC type flash memory 142-1～142-N and MLC type flash memory 144-1～144-M in the above-mentioned memory module 140.That is to say that compared to known flash memory device, the memory module in mixed type of the present invention (hybrid) flash memory device is made up of SLC type flash memory 142-1～142-N and MLC type flash memory 146-1～145-M.
In general, main frame 110 can utilize a host bus 122 to come data in the access flash memory device 100.Certainly, host bus 122 can be compact flash memory storage bus, safety digital storage device bus, multimedia card memory storage bus, USB (universal serial bus) or IEEE1394 bus.
Moreover when main frame 110 during with writing data into memory module 140, microcontroller 120 can send one and write and instruct to memory module 140, and will write writing data into memory module 140.Otherwise during data in main frame reads memory module 140, microcontroller 120 can send a reading command to memory module 140, and therefore, memory module 140 can the output reading of data export main frame 110 to microcontroller 120.
Moreover, and the SLC type flash memory 142-1～142-N in the memory module 140 and MLC type flash memory 146-1～145-M can be divided into a lot of block (block), comprise a plurality of pages or leaves (Page) in each block again.Therefore, have a memory map table in the microcontroller 120, pointer (pointer) is arranged in the above-mentioned memory map table, the relation between its record LBA and the PBA.
In order to reach the better simply characteristic of processing that lower and highdensity advantage of the MLC type price of flash memory and SLC type flash memory write data, the present invention is in conjunction with SLC type flash memory and the memory of MLC type flash memory and all divide temporary transient block (log block) in SLC type flash memory and MLC type flash memory.That is to say that microcontroller 120 can decide the temporary transient block (log block) that writes data and will be placed on SLC type flash memory or the temporary transient block (logblock) of MLC type flash memory memory according to the LBA of the write command of main frame and data.
According to embodiments of the invention, suppose that main frame sends the corresponding size of data (size) that writes of write command greater than a particular data amount, the data volume of one page for example then above-mentionedly writes the temporary transient block (log block) that data then write the memory of MLC type flash memory; Otherwise, suppose that main frame sends the corresponding size of data (size) that writes of write command less than above-mentioned particular data amount, the then above-mentioned data that write then write the temporary transient block (log block) that SLC type flash memory is remembered.
Below illustrate: supposing has four pages or leaves (Page) in each block, that is zero page (Page 0), first page (Page 1), second page (Page 2), the 3rd page (Page 3).Moreover microcontroller 120 can define definition one second temporary transient block (log block 2) in one first temporary transient block (log block 1) and the MLC type flash memory in the SLC of memory module 140 type flash memory.
Please refer to Fig. 6 A～6I, it is the synoptic diagram of mixed flash memory device of the present invention when writing data.We explain with known use identical instances at this, with as the actual difference that reads mode.As shown in Figure 6A, comprise the block sPBA 0～sPBA 3 of SLC type flash memory and the block mPBA 4～mPBA7 of MLC type flash memory memory in the memory module 140 at least.Moreover, before flash memory device is not received write command as yet, by the memory map table in the microcontroller 120 135 as can be known, LBA 0 can correspond to the sPBA 1 of memory module 140, and zero page (Page 0) has been stored D4 data, first page (Page 1) and stored that D5 data, second page (Page 2) have been stored the D6 data, the 3rd page (Page 3) have stored the D7 data among the sPBA 1; LBA 1 can correspond to the mPBA 4 of memory module 140, and zero page (Page 0) has been stored D8 data, first page (Page 1) and stored that D9 data, second page (Page 2) have been stored the D10 data, the 3rd page (Page 3) have stored the D11 data among the mPBA 4; LBA 2 can correspond to the sPBA 0 of memory module 140, and zero page (Page 0) has been stored D12 data, first page (Page 1) and stored that D13 data, second page (Page 2) have been stored the D14 data, the 3rd page (Page 3) have stored the D15 data among the sPBA 0; LBA 3 can correspond to the mPBA 7 of memory module 140, and zero page (Page 0) has been stored D0 data, first page (Page1) and stored that D1 data, second page (Page 2) have been stored the D2 data, the 3rd page (Page 3) have stored the D3 data among the mPBA 7.Moreover according to embodiments of the invention, above-mentioned memory module 140 has two temporary transient blocks (log block), and the first temporary transient block (log block 1) is set at sPBA 3, the second temporary transient blocks (log block 2) and is set at mPBA 5.That is to say, definition one second temporary transient block (log block 2) in definition one first temporary transient block (log block 1) and the MLC type flash memory in SLC type flash memory, moreover 6 of mPBA are not for using block (freeblock) in sPBA in the SLC type flash memory 2 and the MLC type flash memory.Shown in Fig. 6 B, flash memory device receives that (I) main frame sends a write command to LBA 3 and begun to write the data D1 ' of one page by first page (Page 1).Because data D1 ' size is one page, so data D1 ' can be placed on the first temporary transient block (log block 1) earlier.Because SLC type flash memory can be write by any number of pages, therefore, data D1 ' can be written into first page (Page 1) of the first temporary transient block (log block 1).
Shown in Fig. 6 C, flash memory device receives that (II) main frame sends a write command to LBA 3 and begun to write the data D0 ' of one page by zero page (Page 0).Because the data that write of LBA 0 are placed in the first temporary transient block (log block 1) and SLC type flash memory can be write by any number of pages, so data D0 ' can be placed on the zero page (Page 0) of the first temporary transient block (log block 1).
Then, shown in Fig. 6 D, flash memory device receives that (III) main frame sends a write command and begins to write three pages data D5 ', D6 ', D7 ' to LBA0 and by first page (Page 1).Clearly, because the size of data D5 ', D6 ', D7 ' sum total has surpassed above-mentioned particular data amount.Therefore, these data (D5 ', D6 ', D7 ') must be placed on the second temporary transient block (log block 2).Because MLC type flash memory must write in regular turn, therefore, the present invention utilizes microcontroller 120 to carry out consolidation procedure 142 in advance.That is to say, this consolidation procedure 142 can with the data D4 of the 0th page (start page) among the LAB 0 with write data (D5 ', D6 ', D7 ') and merge earlier, and according to just writing the second temporary transient block (log block 2) after the number of pages ordering.
Owing to stored data in the second whole temporary transient blocks (log block 2), therefore shown in Fig. 6 E, microcontroller 120 is carried out and is changed temporary transient block action.That is to say, LBA in the memory map table 135 0 is corresponded to memory module mPBA 5, and define the second new temporary transient block (log block2) in not using block (free block) mPBA 6, and utilize block erase instruction (block erasecommand) with the data erase among the sPBA 1 and make sPBA 1 become not use block (freeblock).
Then, shown in Fig. 6 F, flash memory device receives that (IV) main frame sends a write command and begins to write three pages data D8 ', D9 ', D10 ' to LBA1 and by zero page (Page 0); Clearly, because the size of data D8 ', D9 ', D10 ' sum total has surpassed above-mentioned particular data amount.Therefore, these data (D8 ', D9 ', D10 ') must be placed on the second temporary transient block (log block 2).Moreover, these data (D8 ', D9 ', D10 ') have comprised the 0th page (Page 0) of above-mentioned block, start page (initial page) just, therefore, microcontroller 120 can directly write these data the second temporary transient block (log block) and not need to carry out consolidation procedure 142.
Receive (V) main frame when flash memory device and send a write command to LBA 2 and begin to write the data D13 ' of one page by first page (Page 1).Clearly, write data D13 ' size and be one page, so data D1 ' can be placed on the first temporary transient block (log block 1).Yet,, therefore must carry out and change temporary transient block action because the first temporary transient block (log block 1) has been stored data.That is to say that definition does not use block (free block) to be used as the first new temporary transient block (log block 1) in the SLC of memory module 140 type flash memory once more.
Therefore, shown in Fig. 6 G, utilize merge cells 146 that data D2, D3 and the data in the first temporary transient block (log block 1) of mPBA 7 second and third pages (Page 2,3) are merged, make zero page (Page 0) storage data D0 ' in the temporary area piece of winning (log block 1), first page (Page 1) storage data D1 ', second page (Page 2) storage data D2, storage data D3 in the 3rd page (Page 3).
Shown in Fig. 6 H, the LBA in the memory map table 135 3 is corresponded to the sPBA 3 of memory module 140.Therefore, microcontroller 120 can define one in memory module 140 not use block be the first new temporary transient block (log block 1), and for example, sPBA 1.Moreover, because all data have been substituted among the former mPBA 7, utilize block erase instruction (block erase command) and to make mPBA 7 become and do not use block the data erase among the mPBA 7.
Shown in Fig. 6 I, owing to the new first temporary transient block (log block 1) forms, and D13 ' can be placed on first page of the first temporary transient block (log block 1).
As shown in the above description, when main frame sends the corresponding size of data of write command (size) above the particular data amount, these data must write the MLC flash memory, and microcontroller 120 utilizes consolidation procedure, makes that being arranged in the above-mentioned data that write comprises that all data of a start page write the above-mentioned second temporary transient block in regular turn before.Therefore, when microcontroller 120 is carried out the temporary transient block action of replacing (flush out log block), need not carry out known sequencer program and not use the block write-in program, therefore can significantly improve the efficient of memory module 140.
Moreover the present invention is not limited to the mixed flash memory device that SLC type and MLC type flash memory are formed.Those skilled in the art know, no matter SLC type and MLC type flash memory all can further be categorized as the first estate (first grade) product and second grade (second grade) product after manufacturing is finished.The flash memory life-span of the first estate is long and quality is better, that is to say, the flash memory of the first estate allows the number of times that writes repeatedly and read more and data error rate is low; Otherwise short product of the flash memory life-span of second grade are held relatively poor, that is to say, allow the number of times that writes repeatedly and read less and data error rate is low.
That is to say that the present invention also can utilize the mixed flash memory device that flash memory combined of different brackets.When the size that writes data (size) during, then will write the flash memory that data write the first estate less than above-mentioned particular data amount; Otherwise,, then will write the flash memory that data write second grade when the size that writes data (size) during greater than above-mentioned particular data amount.Therefore, the flash memory of second grade write the indegree of writing that indegree can be less than the first estate, and ensure the life-span of above-mentioned mixed flash memory device.
Comprehensive above technical descriptioon; mixed flash memory device of the present invention and method of operating thereof have solved the shortcoming that is produced in the prior art really; and then finish the development topmost purpose of the present invention; moreover; any change and modification that those skilled in the art of the present invention make do not break away from the scope that claims institute desire is protected.
Claims (12)
1. mixed flash memory device is characterized in that comprising:
Microcontroller is connected to host bus, in order to receive the data that write of main frame; And
Memory module is connected to above-mentioned microcontroller, comprises one first type flash memory and one second type flash memory;
Wherein, when above-mentioned when writing size of data, the above-mentioned data that write are write the first temporary transient block in the above-mentioned first type flash memory less than the particular data amount; When above-mentioned when writing size of data, the above-mentioned data that write are write the second temporary transient block in the above-mentioned second type flash memory greater than above-mentioned particular data amount.
2. mixed flash memory device according to claim 1, it is characterized in that, with above-mentioned when writing data and writing the above-mentioned second temporary transient block in the above-mentioned second type flash memory, above-mentioned when writing data and comprising start page, directly the above-mentioned data that write are write the above-mentioned second temporary transient block.
3. mixed flash memory device according to claim 1, it is characterized in that, with above-mentioned when writing data and writing the above-mentioned second temporary transient block in the above-mentioned second type flash memory, above-mentioned when writing data and not comprising start page, utilize consolidation procedure, comprise that all data of start page write the above-mentioned second temporary transient block before being arranged in the above-mentioned data that write.
4. mixed flash memory device according to claim 1 is characterized in that, the above-mentioned first type flash memory is single level memory cell type flash memory, and the above-mentioned second type flash memory is many level memory cell type flash memory.
5. mixed flash memory device according to claim 1 is characterized in that, the above-mentioned first type flash memory is the first estate flash memory, and the above-mentioned second type flash memory is the second grade flash memory.
6. mixed flash memory device according to claim 1 is characterized in that, above-mentioned mixed flash memory device is USB flash disk, compact flash memory storage, safety digital storage device or multimedia card memory storage.
7. the control method of a mixed flash memory device, above-mentioned mixed flash memory device comprises the memory module of being made up of one first type flash memory and one second type flash memory, above-mentioned control method comprises the following steps:
Reception writes data by what main frame sent;
When above-mentioned when writing size of data, the above-mentioned data that write are write the first temporary transient block in the above-mentioned first type flash memory less than the particular data amount; And
When above-mentioned when writing size of data, the above-mentioned data that write are write the second temporary transient block in the above-mentioned second type flash memory greater than above-mentioned particular data amount.
8. the control method of mixed flash memory device according to claim 7, it is characterized in that, with above-mentioned when writing data and writing the above-mentioned second temporary transient block in the above-mentioned second type flash memory, above-mentioned when writing data and comprising start page, directly the above-mentioned data that write are write the above-mentioned second temporary transient block.
9. the control method of mixed flash memory device according to claim 7, it is characterized in that, with above-mentioned when writing data and writing the above-mentioned second temporary transient block in the above-mentioned second type flash memory, above-mentioned when writing data and not comprising start page, utilize a consolidation procedure, comprise that all data of start page write the above-mentioned second temporary transient block before being arranged in the above-mentioned data that write.
10. the control method of mixed flash memory device according to claim 7 is characterized in that, the above-mentioned first type flash memory is single level memory cell type flash memory, and the above-mentioned second type flash memory is many level memory cell type flash memory.
11. the control method of mixed flash memory device according to claim 7 is characterized in that, the above-mentioned first type flash memory is the first estate flash memory, and the above-mentioned second type flash memory is the second grade flash memory.
12. the control method of mixed flash memory device according to claim 7 is characterized in that, above-mentioned mixed flash memory device is USB flash disk, compact flash memory storage, safety digital storage device or multimedia card memory storage.
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| CN102419734A (en) * | 2010-09-27 | 2012-04-18 | 北京中星微电子有限公司 | Method and device for storing data |
| CN102541755A (en) * | 2010-12-29 | 2012-07-04 | 深圳市硅格半导体有限公司 | Flash memory and data receiving method thereof |
| CN106648443A (en) * | 2015-10-30 | 2017-05-10 | 群联电子股份有限公司 | Valid data merging method, memory controller and memory storage device |
| CN107341681A (en) * | 2016-05-03 | 2017-11-10 | 华北理工大学 | Information service system |
| WO2019051861A1 (en) * | 2017-09-12 | 2019-03-21 | 山东大学 | Mixed flash memory read/write method and mixed read/write flash memory |
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| CN100583832C (en) * | 2007-03-30 | 2010-01-20 | 华为技术有限公司 | Data management method and system |
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| CN102419734A (en) * | 2010-09-27 | 2012-04-18 | 北京中星微电子有限公司 | Method and device for storing data |
| CN102419734B (en) * | 2010-09-27 | 2016-05-11 | 北京中星微电子有限公司 | A kind of method of data storage and device |
| CN102541755A (en) * | 2010-12-29 | 2012-07-04 | 深圳市硅格半导体有限公司 | Flash memory and data receiving method thereof |
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| CN106648443A (en) * | 2015-10-30 | 2017-05-10 | 群联电子股份有限公司 | Valid data merging method, memory controller and memory storage device |
| CN106648443B (en) * | 2015-10-30 | 2019-06-25 | 群联电子股份有限公司 | Valid data merging method, Memory Controller and memory storage apparatus |
| CN107341681A (en) * | 2016-05-03 | 2017-11-10 | 华北理工大学 | Information service system |
| CN110603531A (en) * | 2017-04-04 | 2019-12-20 | 美光科技公司 | Garbage collection |
| EP3607449A4 (en) * | 2017-04-04 | 2020-12-16 | Micron Technology, Inc. | Garbage collection |
| US10949344B2 (en) | 2017-04-04 | 2021-03-16 | Micron Technology, Inc. | Garbage collection |
| US11416391B2 (en) | 2017-04-04 | 2022-08-16 | Micron Technology, Inc. | Garbage collection |
| WO2019051861A1 (en) * | 2017-09-12 | 2019-03-21 | 山东大学 | Mixed flash memory read/write method and mixed read/write flash memory |
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