WO2019051861A1

WO2019051861A1 - Mixed flash memory read/write method and mixed read/write flash memory

Info

Publication number: WO2019051861A1
Application number: PCT/CN2017/102557
Authority: WO
Inventors: 陈杰智; 杨文静
Original assignee: 山东大学
Priority date: 2017-09-12
Filing date: 2017-09-21
Publication date: 2019-03-21
Also published as: CN107527655A

Abstract

A mixed flash memory read/write method and a mixed read/write flash memory. In the mixed flash memory read/write method, operations of the following four storage modes are mixed: single-level storage, multi-level storage, triple-level storage, and quad-level storage, and at least two of the four storage modes are mixed and applied to different word lines in the same storage region. The mixed read/write flash memory comprises a data interface, a NAND controller, and a storage region. The NAND controller is provided with a storage region management module responsible for managing storage region division and storage mode control modules corresponding to different storage region action modes. The different action modes may be defined at an initial stage, and may also be dynamically adjusted during memory reading/writing, thereby reducing a probability of an error code caused by a change in a memory cell characteristic. The present invention achieves a balance between high storage density and high reliability while ensuring storage density, and effectively improves reliability of a flash memory.

Description

Flash memory hybrid read/write method and hybrid read/write flash memory

Technical field

The present invention relates to the field of memory, and in particular to a method for hybrid read and write of flash memory and a hybrid read/write flash memory.

Background technique

Flash memory is a new type of storage medium that was born in the late 1980s. Due to its excellent characteristics such as non-volatility, high speed, high shock resistance, low power consumption, small size and light weight, flash memory has been widely used in embedded systems and portable devices such as mobile phones and data acquisition in recent years, such as mobile phones and portable media. Players, digital cameras, sensors, also used in aerospace and other fields, such as aerospace vehicles. The flash memory of the planar structure has reached the limit of expansion. The three-dimensional flash memory technology vertically stacks multiple layers of data storage units to support higher storage capacity in a smaller space, resulting in greater cost savings and lower energy consumption. And a significant performance boost to meet the needs of many consumer mobile devices and the most demanding enterprise deployments.

The three-dimensional flash memory shown in FIG. 1 mainly includes a silicon-core core (core-SiO2) 1, a polysilicon Chanel 2, a tunneling layer 3, and a charge storage layer from the inside to the outside. (charge trapping layer) 4, blocking layer 5 and electrode 6. As the process changes and is optimized, the materials in the same vertical annular channel structure may be different. For example, the polysilicon channel may be replaced by other materials, and the materials of the tunneling layer material, the charge storage layer material, and the barrier layer may be replaced.

Figure 2 shows the polysilicon channel in a three-dimensional flash memory. Due to the special structure of the three-dimensional flash memory, the characteristics and shape structure of the channel material will vary depending on the depth of the memory hole. For example, in the polysilicon channel, the area A near the bottom of the deep hole, the size of the polycrystalline silicon crystal is larger, the density of the channel defect is lower; the storage area C, the size of the polycrystalline silicon crystal is smaller, the density of the channel defect is higher; The size of the polycrystalline silicon grains in B is relatively uniform, and the channel defect density is between the regions A and C. In other words, the characteristics of the memory cells distributed in the region B are relatively close, and the characteristic distribution can be well controlled; and the characteristics of the memory cells in the regions A and C are quite different, in the same storage operation mode. The distribution of characteristics can be difficult to control, which can be very difficult for storage in multi-value mode.

Figure 3 shows the various read and write modes of operation of the flash memory. Currently, the memory operation mode mainly includes three read and write operation modes: single value storage (SLC), multi value storage (MLC), and three value storage (TLC). In recent years, in the three-dimensional flash memory, due to the large size of the memory cell, various inter-cell interferences between the memory cells are well controlled, and each cell stores four bits of QLC four. The value storage mode is also implemented. Four-valued memory (QLC) is also used in 3D flash memory. SLC means that each unit stores one bit, the erasing speed is fast, the data reading window is large, the byte misreading rate is extremely low, and the erasable life is long; MLC means that each unit stores two bits, which is more than the storage capacity of the SLC. Doubled, the erasing speed is reduced, and the life is average; TLC stores three bits per unit, the erasing speed is slow, and the erasable life is short; QLC stores four bits per unit, and the storage density is 16 times that of SLC mode. However, the erasing speed is very slow, and the data reading error rate is high. It is necessary to cooperate with a good ECC (Error Checking and Correcting) to improve the data reading accuracy, and the number of erasable times is extremely limited.

However, in the three-dimensional flash memory, one problem that cannot be avoided is its polysilicon channel. The size of the crystal in the polysilicon channel is closely related to the depth of the channel, and the deeper the polysilicon channel grain is. Since the size of the die is closely related to the channel defect density, the characteristics of the memory cells in the three-dimensional flash memory vary greatly depending on the depth of the polysilicon channel, which greatly affects the MLC, TLC and QLC. The storage mode application brings difficulties for flash memory with greater storage density in the future.

Summary of the invention

The invention provides a flash memory hybrid read/write method capable of effectively improving the reliability of the flash memory, and a hybrid read/write flash memory for realizing the method, in combination with a plurality of read and write modes of the memory, and a plurality of read and write modes of the memory. Memory.

The flash memory hybrid read/write method of the present invention performs a mixed operation of four storage modes of single value storage (SLC), multi value storage (MLC), three value storage (TLC) and four value storage (QLC) in a flash memory. At least two of the four storage modes are applied to different word-lines of the same block.

The flash memory sets a fixed read/write mode of different areas during use, or dynamically selects a read/write mode for each word line, each layer of storage area or each piece of storage area.

The mixing operation is applied to a flash memory having a difference in memory cell characteristics and a difference in memory distribution in the same memory area.

Different storage modes in the hybrid operation are either initially defined or dynamically adjusted during memory read and write.

If the flash memory is a two-dimensional planar flash memory, the hybrid operation is in a different memory chip or memory area.

If the flash memory is a three-dimensional flash memory, the hybrid operation is in the following modes: one is applied to different memory chips or storage areas, and the other is to select different read and write modes for different word lines in the same storage area by adding a selection controller. Set the adjacent two layers to different read/write modes, or divide different storage areas to correspond to different read/write modes.

If the flash memory is a three-dimensional flash memory, the upper and lower memory cell regions of the three-dimensional flash memory adopt a single value storage (SLC) mode, and the middle portion of the memory cell region adopts a multi-value storage (MLC) or a three-value storage (TLC) mode. Read and write and control by selecting a controller.

The hybrid read/write flash memory implementing the above method adopts the following technical solutions:

The hybrid read/write flash memory includes a data interface, a NAND controller and a storage area; the NAND controller is provided with a storage area management module responsible for managing storage area division and a storage mode control module corresponding to different storage area operation modes.

The storage area management module is divided into the same number of storage areas according to the number of storage modes (currently four types: SLC, MLC, TLC, and QLC).

The data writing process of the above mixed read/write flash memory is: after obtaining the data input instruction, the data to be written is saved in the buffer storage space, and the data storage address is determined according to the memory usage condition, and then according to the NAND controller. The storage area management module responsible for managing the storage area division and the storage mode control module corresponding to the operation mode of the different storage area determine the storage mode, and then perform the data write operation, and end the data write on the premise that the write data is correct. process.

The data reading process of the hybrid read/write flash memory is: after obtaining the data read command, determining the data read mode according to the storage area management module and the storage mode control module, and then performing the data read operation, and determining The data reading process is ended on the premise that the data is read without errors. Since data reading and data writing are in one-to-one correspondence, the same reading method cannot be used to read data of different writing modes, and it is necessary to determine the operation mode when data is read according to the writing mode in different storage areas. .

The invention applies a plurality of operation modes to different word lines of the same storage area (Block), realizes a balance of high storage density and high reliability, and effectively improves the reliability of the flash memory.

DRAWINGS

1 is a schematic diagram of a three-dimensional flash memory structure.

2 is a schematic diagram of a polysilicon channel in a three-dimensional flash memory.

3 is a schematic diagram of various different modes of operation of a flash memory.

4 is a schematic diagram of a write state distribution of different regions of a three-dimensional flash memory.

FIG. 5 is a schematic diagram of dividing different operation modes according to a memory cell characteristic region.

6 is a schematic diagram showing the structure of a hybrid read/write flash memory of the present invention.

Figure 7 is a schematic diagram of a storage area management module in the present invention.

Figure 8 is a diagram showing the data writing of the mixed operation mode memory in the present invention.

Fig. 9 is a view showing the data reading of the mixed operation mode memory in the present invention.

Detailed ways

The flash memory hybrid read/write method of the present invention is to apply a plurality of operation modes of the flash memory to different word lines of the same memory to achieve a balance between high storage density and high reliability. A combination of at least two of single-value storage (SLC), multi-value storage (MLC), three-value storage (TLC), and four-value storage (QLC) modes of operation of the flash memory can be applied to the same memory (Block) Word-line.

For two-dimensional planar flash memory, since the memory cell characteristics of different word lines in the same memory area are not much different, the operation mode mixing mainly lies in different memory chips or memory areas. For the three-dimensional flash memory, the mixed operation mode can be applied to different memory chips or storage areas, and different read and write modes can be selected for different word lines in the same memory area by adding a selection controller, and the adjacent two layers can be set as Different reading and writing methods can also divide different storage areas to correspond to different reading and writing modes. Different read and write modes can be dynamically adjusted, that is, the read/write mode of the memory can be set before reading and writing, and the read and write modes of each area can be dynamically adjusted during the process of reading and writing the memory, thereby reducing the characteristics of the memory unit. The change causes the probability of error code, and improves the working efficiency of the memory as a whole.

The flash memory hybrid read/write method of the present invention can be applied to a memory having a difference in memory cell characteristics and a memory distribution difference in the same memory area, for example, a three-dimensional flash memory: a memory cell characteristic difference between an upper layer and a lower layer of a three-dimensional flash memory is large. The memory cell characteristics in the middle part are relatively uniform. Various types of reading and writing methods of the three-dimensional flash memory, such as SLC mode, MLC mode, and TLC mode, are used, and the memory cell area with large difference in characteristics adopts the SLC mode, and the memory cell area with uniform characteristics is read and written by the MLC mode or the TLC mode. And by controlling the controller to ensure the storage density of the three-dimensional flash memory while ensuring the reliability characteristics of all memory cells, including Data retention characteristics and memory unit lifetime.

Figure 4 shows a schematic diagram of the write state distribution of different regions of a three-dimensional flash memory. In the same operation mode, data is written to the storage area in the erased state, and the distribution of the write state is relatively wide. In the SLC action mode, due to its large data read window, it generally does not cause byte misreading; however, for high memory density MLC, TLC and QLC action modes, the data read window is very wide. The write state distribution greatly increases the data misreading rate. The distribution can be simplified into three different regions. The memory cells distributed in region 1 have a higher threshold voltage distribution, mainly derived from the memory cells of region A in FIG. 2; the threshold voltage distributions of the memory cells distributed in region 2 are compared. The average is mainly derived from the memory cells of region B in FIG. 2; and the memory cells distributed in region 3 have a lower threshold voltage distribution, mainly derived from the memory cells of region C in FIG.

With process optimization, material changes, device structure design, and changes in operating modes, the relationship between memory cell characteristics and deep hole depth in deep wells may change, for example, a higher threshold voltage distribution in region 1. The storage unit may be mainly derived from the area C in FIG. 2 above, and the higher threshold voltage distribution storage unit in the area 3 may be mainly derived from the area A in FIG. 2 described above. However, regardless of how its distribution relevance changes, the more uniform storage unit in Region 2 is mainly derived from Region B in Figure 2.

Figure 5 shows the different action modes divided according to the memory cell characteristic area. According to FIG. 4, the storage units of different regions have different distributions in the same operation mode, so that the overall distribution is widened. Therefore, different operation modes can be used to read and write memory cells of different regions. For example, the operation mode A can read and write the memory cells near the upper region of the NAND memory cell array (NAND String) by using the single-value mode SLC, and the operation mode B can be used. The ternary mode TLC reads and writes the memory cells of the area in which most of the NAND memory cell arrays have relatively uniform storage characteristics, and the action mode C can use the binary mode MLC to read and write the memory cells near the lower area of the NAND memory cell array.

The division of the above areas and the designation of the operation mode can be flexibly specified according to the characteristics of different memory chips. At the same time, since the degradation speed of the memory cells is different under different operation modes, the memory cell life in the multi-value operation mode such as MLC/TLC/QLC is much shorter than that of the SLC mode, so the storage unit can be stored during the erasing process. The characteristics of the unit are similar to the dynamic evaluation shown in Figure 4, and the division and action patterns are redefined according to the evaluation results.

As shown in FIG. 6, the hybrid read/write flash memory of the present invention mainly includes a data interface, a NAND controller and a storage area. In addition to the general control functions, the NAND controller adds a storage area management module responsible for managing storage area division and a storage mode control module corresponding to different storage area operation modes. Specifically, different storage and read mode single-value storage (SLC), multi-value storage (MLC), three-value storage (TLC), and four-value storage (QLC) of the flash memory are correspondingly controlled in the storage area, in the NAND controller. Choose different read and write modes for different storage areas.

As shown in FIG. 7, the storage area management module can be generally divided into a storage area 1, a storage area 2, and a storage area 3 according to an operation mode, which respectively correspond to commonly used single value storage (SLC), multi-value storage (MLC), and three-value storage. (TLC). When the four-value storage (QLC) action mode is applied, a memory area 4 can be added. When the storage area of the selected storage area is better and the performance distribution is relatively uniform, the MLC operation mode or the TLC action mode can be used for reading and writing. When the storage performance is poor or the storage area characteristic distribution is relatively wide, the SLC mode can be used for reading and writing. This can improve the overall erasing speed and lifetime of the effective memory cells of the flash memory while ensuring the storage density. Different storage methods are optional, and can be dynamically changed. The storage mode of the memory is set at the initial stage, and the storage mode of each area can be dynamically adjusted during the process of erasing the memory.

As shown in FIG. 8, the data writing process of the hybrid read/write flash memory of the present invention is performed after the data input instruction is obtained. The data to be written is stored in the buffer storage space, and the data storage address is determined according to the memory usage condition, and then the storage area management module responsible for managing the storage area division in the NAND controller and the storage mode corresponding to the operation mode of the different storage area are used. The control module determines the storage mode, and then performs a data write operation to end the data write process on the premise that the write data is correct.

As shown in FIG. 9, the data reading process of the hybrid read/write flash memory of the present invention determines the data read mode according to the storage area management module and the storage mode control module after obtaining the data read command, and then performs data readout. The operation ends the data reading process on the premise that it is determined that the read data is correct. Since data reading and data writing are in one-to-one correspondence, the same reading method cannot be used to read data of different writing modes, and it is necessary to determine the operation mode when data is read according to the writing mode in different storage areas. .

The mixed read/write flash memory can set the fixed read/write mode of different areas in use, and can dynamically select the read/write mode for each word line, each layer storage area or each storage area during use. In the process of erasing and writing a memory cell, the memory cells in the MLC mode and the TLC mode are easily degraded. Therefore, the read and write modes adopted by the different read/write modes corresponding to the present invention are not static and can be dynamically adjusted, thereby Solve the reliability degradation caused by the change of the characteristics of the memory cell in the initial process during the initial process.

Claims

A flash memory hybrid read/write method, characterized in that four storage modes of single value storage, multi-value storage, three-value storage and four-value storage are mixed in a flash memory, and at least two of the four storage modes are used. Mix different word lines applied to the same memory area.
The flash memory hybrid read/write method according to claim 1, wherein the flash memory sets a fixed read/write mode in different areas during use, or stores each word line, each layer storage area or each slice. The area dynamically selects the read and write mode.
The flash memory hybrid read/write method according to claim 1, wherein said mixing operation is applied to a flash memory having a difference in memory cell characteristics and a memory distribution difference in the same memory area.
The flash memory hybrid read/write method according to claim 1, wherein different storage modes in the mixing operation are either initially defined or dynamically adjusted during memory read and write.
The flash memory hybrid read/write method according to claim 1, wherein if the flash memory is a two-dimensional planar flash memory, the hybrid operation is in a different memory chip or a memory area.
The flash memory hybrid read/write method according to claim 1, wherein if the flash memory is a three-dimensional flash memory, the mixed operation is in the following mode: one is applied to different memory chips or storage areas, and the second is added by The controller is selected to select different read/write modes for different word lines in the same storage area, and the adjacent two layers are set to different read/write modes, or different storage areas are allocated to correspond to different read/write modes.
The flash memory hybrid read/write method according to claim 1, wherein if the flash memory is a three-dimensional flash memory, the upper and lower memory cell regions of the three-dimensional flash memory adopt a single value storage mode, and the middle portion of the memory cell region Read and write using multi-value storage or three-value storage mode and control by selecting a controller.
A hybrid read/write flash memory, comprising a data interface, a NAND controller and a storage area; wherein: the NAND controller is provided with a storage area management module responsible for managing storage area division and storage corresponding to different storage area operation modes Mode control module.
The hybrid read/write flash memory according to claim 8, wherein said storage area management module is divided into the same number of storage areas according to the number of storage modes.