CN110211622A - Improve the data erasing-writing method of multivalue NAND-flash memory data storage total amount - Google Patents
Improve the data erasing-writing method of multivalue NAND-flash memory data storage total amount Download PDFInfo
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- CN110211622A CN110211622A CN201910513247.6A CN201910513247A CN110211622A CN 110211622 A CN110211622 A CN 110211622A CN 201910513247 A CN201910513247 A CN 201910513247A CN 110211622 A CN110211622 A CN 110211622A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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Abstract
A kind of data erasing-writing method improving multivalue NAND-flash memory data storage total amount, the service condition in NAND-flash memory space is judged in advance, set memory space threshold value, can memory space be lower than given threshold when, erasable operation is executed according to the erasable mode of standard, if can memory space when being greater than given threshold, the quasi- erasable operation of monodrome is carried out to super multivalue NAND-flash memory, single bit of information is repeatedly continuously written into same storage region in the case where not wiping data with existing.The present invention is based on NAND-flash memories, it can effectively improve writing speed, improve storage unit utilization efficiency, effectively increase data storage total amount and erasing and writing life, it theoretically can be under the identical degree of wear, data storage total amount 75% can be promoted using QSLC in TLC NAND-flash memory, data storage total amount 87.5% can be promoted using QSLC mode in QLC NAND-flash memory.
Description
Technical field
The present invention relates to a kind of for improving the erasable operation side of data of multivalue NAND-flash memory data storage total amount
Method belongs to flash memories technical field.
Background technique
Flash memories mainly include two types according to memory cell architecture, and NAND-flash memory and NOR flash memory are deposited
Reservoir；According to the storage mode of storage unit, can be divided into SLC (Single-Level Cell) monodrome storage (1bit/cell),
MLC (Multi-Level Cell) dibit stores (2bit/cell), TLC (Trinary-Level Cell) three bit storages
(3bit/cell), QLC (Quad-Level Cell) four bit storages (4bit/cell).The present invention is dodged for super multivalue NAND
Memory is deposited, what is be mainly directed towards is TLC nand flash memory and QLC nand flash memory.
The big data of sharp increase with cloud storage and to(for) storage capacity requirement and storage density demand, large capacity NAND
Flash memories using more and more extensive, pushed the continuous renewal of NAND-flash memory technology, such as put down from framework
Face two-dimensional storage framework is transformed into three-dimensional perpendicular overlapping shelf structure, and also further development realizes TLC to SLC and MLC memory module
Surpass multilevel storage with QLC.
However, the Performance And Reliability relative to SLC and MLC memory module, under the super multilevel storage mode such as TLC and QLC
It all needs to be further improved, such as writing speed is slow, recyclable erasing and writing life is short, storage unit benefit when small data stores
With the degeneration and the increase of data garbage etc. of rate.
Therefore, the service life (increasing data storage total amount) for how improving super multivalue NAND-flash memory, mentions simultaneously
Its high writing speed and storage unit utilization rate, these are that very core is also very crucial for super multivalue nand memory
's.The wherein erasable number of storage unit, i.e. service life are the most key parameter indexes of NAND-flash memory,
Deciding factor is that erasable be charge tunnelling caused by the injection of realization charge and the required high electric field added of charge removal in the process
The degeneration of layer.
Fig. 1 gives the erasable operating principle of floating gate type NAND-flash memory.Fig. 1 (a) is that floating gate type nand flash memory is deposited
The erasing operation schematic diagram of reservoir, erasing operation reset the data of all cells in a block simultaneously, it means that erasing behaviour
Make to execute in block rank.By applying high positive voltage (such as in the channel and control gate of all units in selected block
20V), the electronics of all charge layers all passes through FN tunneling mechanism and goes out, and after an erase operation, all cells all become in block
For erase status (Erase).Fig. 2 (b) is the write operation schematic diagram of floating gate type NAND-flash memory, will in write operation
Wordline is set as write-in voltage, and electron number is increased in floating gate layer, and write operation is completed.
Fig. 2 gives the erasable operating principle of charge trap-type NAND-flash memory.Fig. 2 (a) is charge trap-type
The erasing operation of NAND-flash memory, erasing operation reset the data of all cells in a block simultaneously, it means that wipe
Except operation is executed in block rank.By applying high positive voltage (such as in the channel and control gate of all units in selected block
20V), the electronics of all electric charge capture layers can all go out, and after an erase operation, all cells all become wiping shape in block
State (Erase).Fig. 2 (b) is that wordline is set as writing by the write operation of charge trap-type NAND-flash memory in write operation
Enter voltage, electron number is increased in electric charge capture layer, and write operation is completed.
Fig. 3 gives the threshold voltage distribution of TLC NAND-flash memory.NAND has erasing, write-in and reads three bases
This operation, erasing is with block (Block) for basic unit, and write-in and reading are using page as basic unit.Three-dimensional TLC NAND dodges
It deposits memory and is divided into three kinds of different page types, i.e. LSB, CSB and MSB.TLC nand flash memory includes eight storage states
(erasing, A, B, C, D, E, F, G).
Fig. 4 gives data storage total amount and bit error rate BER (bit error ratio) and storing data total amount is closed
System.With the increase of storing data total amount, the probability that mistake occurs shows nonlinear rapid growth.It is specific in Fig. 4
Relationship are as follows: figure middle polyline is as the general of mistake occurs for the increase of the i.e. data storage total amount of increase of program/erase cycle-index
Nonlinear rapid growth is presented in rate.
Currently, being to pass through in system level SLC single-bit bifurcation mode nand flash memory chip and multivalue in mainstream technology
The mixed Performance And Reliability to improve total system of mode nand flash memory storage chip；Or by being directed to different uses
Environment and use condition carry out Optimization Work parameter to reach the optimum performance and reliability that NAND chip uses；Or pass through core
Blade technolgy optimizes fundamentally to improve the Performance And Reliability of multivalue NAND chip.In sum, the NAND of process stabilizing is dodged
Chip is deposited, most of solution is all the global reliability for improving system from the angle of system optimization, and there is no independent needles
Its data storage total amount is fundamentally improved to prolong its service life to multivalue nand flash memory chip.
The present invention is intended to provide a kind of data erasing-writing method for improving multivalue NAND-flash memory data storage total amount.
Summary of the invention
The present invention for super multivalue TLC and QLC NAND-flash memory existing in terms of data store total amount raising not
Foot provides a kind of energy raising super multivalue NAND-flash memory service life, increases data and store total amount, and improve write simultaneously
Enter the data erasing-writing method of speed and storage unit utilization rate.
The data erasing-writing method of raising multivalue NAND-flash memory data storage total amount of the invention is:
This method is based on super multivalue NAND-flash memory, and the service condition in NAND-flash memory space is carried out
Pre- judgement, sets memory space threshold value, can memory space be lower than given threshold when, executed according to the erasable mode of standard erasable
Operation, if can memory space when being greater than given threshold, to super multivalue NAND-flash memory carry out quasi- monodrome (Quasi-SLC,
QSLC) erasable operation is repeatedly continuously written into single bit of information to same storage region in the case where not wiping data with existing.
The threshold value refers to that the erasable mode of quasi- monodrome (QSLC) specified according to practical application scene and the super multivalue of standard are wiped
The storage capacity value of WriteMode switching, it is assumed that TLC mode (3 bits/cell) Memory Storage Unit number is A, then data are deposited
Storage capacity is X=A*3 bit, if needing again after the storage unit of 50% or more quantity is written according to QSLC mode
Data are written and then need to be switched to TLC multilevel storage mode, then threshold definitions be occupied storage unit data volume (
It is believed that threshold value is exactly to have occupied the data volume of storage unit in memory), it is Y=A/2 bit.When data storage capacity arrives
When up to Y bit, need to switch to TLC multivalue mode.The instantaneous lifts of capacity can be realized by being switched to super multilevel storage mode,
QSLC memory module can realize low capacity data no write de-lay and high storage unit utilization rate.
The erasable mode of standard is the erasable mode of TLC or QLC of standard, i.e., 8 states (TLC) are completed when being written every time
Or the one-time write of 16 states (QLC), primary erasing is executed to legacy data memory space before new data write-in
Operation.
The erasable operation of quasi- monodrome (QSLC) is after an erase operation, to carry out in the case where no longer wiping data with existing
Continuous monodrome bifurcation write operation, every time be written data only there are two state distribution (such as TLC nand flash memory store
Device can be successively from erasing state and A state, A state and B state, B state and C state, C state and D state, D state and E state, E state and F state, F state and G
This seven kinds of modes of state are sequentially written in), and without carrying out data erasing operation in writing process.Data writing process can also
Certain intermediate states therein are skipped with selectivity to obtain lower bit error rate.
The mode of operation that is repeatedly sequentially written in of the invention can effectively improve writing speed, improve storage unit using effect
Rate promotes memory capacity and service life.The present invention is applicable not only to no used storage region, is also applied for repeatedly
Region after erasing operation is written, can theoretically use in TLC NAND-flash memory under the identical degree of wear
QSLC can promote data storage total amount 75%, can promote data storage using QSLC mode in QLC NAND-flash memory
Total amount 87.5%.
Detailed description of the invention
Fig. 1 is the erasable schematic diagram of floating gate type NAND-flash memory, and wherein Fig. 1 (a) is the storage of floating gate type nand flash memory
The erasing schematic diagram of device, Fig. 1 (b) are the write-in schematic diagrams of floating gate type NAND-flash memory.
Fig. 2 is the erasable schematic diagram of charge trap-type NAND-flash memory, and wherein Fig. 2 (a) is that charge trap-type NAND dodges
Memory erasing schematic diagram is deposited, Fig. 2 (b) is charge trap-type NAND-flash memory write-in schematic diagram.
Fig. 3 is the threshold voltage distribution map of TLC NAND-flash memory.
Fig. 4 is data storage total amount and bit error rate BER (bit error ratio) relation characteristic figure.
Fig. 5 is the timing diagram of the double mode mixing storage system of super multilevel storage and QSLC storage.
Fig. 6 is the specific Storageunit Usage of NAND-flash memory.
Fig. 7 is the erasable first embodiment of QSLC mode (mode for being sequentially written in adjacent states) of TLC NAND-flash memory
Schematic diagram.
Fig. 8 is that the erasable second embodiment of QSLC mode of TLC NAND-flash memory (selectively skips certain intermediate states
Mode) schematic diagram.
Fig. 9 is the erasable 3rd embodiment of the QSLC mode of TLC NAND-flash memory.
Figure 10 is the erasable schematic diagram of QSLC mode of QLC NAND-flash memory.
Figure 11 is to store total amount increase figure for data of the TLC NAND Flash under different erasable modes.
Figure 12 is specific test result display diagram.
Specific embodiment
Fig. 5 gives the timing diagram of the double mode mixing storage system of super multilevel storage and QSLC storage.Firstly the need of right
Write-in data volume and NAND-flash memory can memory space judged in advance, can memory space lower than a certain given threshold
When, then execute erasable operation according to the erasable mode of standard, if can memory space when being greater than the given threshold, it is carried out quasi- single
Be worth (Quasi-SLC, QSLC) erasable operation, i.e., it is repeatedly continuous to same storage region in the case where not wiping data with existing
The operation of single bit of information is written.
Fig. 6 gives the storage unit distribution situation of entire nand flash memory device, and wherein a-quadrant is to carry out the erasable operation of QSLC
Region, when a-quadrant is write it is full when, it was demonstrated that reach threshold value, remaining B area carry out standard the erasable mode of TLC or QLC into
It exercises and uses, simultaneously, a-quadrant storing data is backuped into the region C in a manner of multilevel storage, to realize a-quadrant again
Secondary utilization.
Fig. 7 gives erasable one embodiment of QSLC mode of TLC NAND-flash memory, is to be sequentially written in phase
The mode of adjacent state.Specific method is: carrying out lowest threshold single-bit bifurcation first to memory space under erase status and writes
Enter, i.e. write-in data are stored in erasing state and A state；It to be write in same storage region while storing data no longer needs
When entering new data, erasing operation is no longer executed, but directly carries out single-bit again using A state and B state as data storage state
The data of bifurcation are written；Equally, when the data that A state and B state are stored as storage state no longer need, data erasing is not executed,
New data are directly written in same storage region again using B state and C state as storage state；According to same writing mode,
The data of C state and D state can be arranged to store composite state, the data storage composite state of D state and E state, the data storage of E state and F state
The data of composite state, F state and G state store composite state, execute come successively sequence to the covering of legacy data and writing for new data
Enter.When the data that F state and G state are stored need erasing or cover, just finally executing an erasing operation makes to store state time
To erase status.In short, the erasable mode of QSLC is to execute erasing state/A state, A state/B state, B state/C state, C state/D in sequence
State, D state/E state, E state/F state, F state/G state, seven kinds of single-bit bifurcations be sequentially written in after movement that carry out primary erasing dynamic
Make.
Fig. 8 gives the erasable second embodiment of QSLC mode of TLC NAND-flash memory, is data writing process
Selectivity skips the mode of certain intermediate states, to obtain lower bit error rate.In the mistake in view of some practical storage states
Rate bit rate can be bigger, can also selectively combine two kinds of storage states and is sequentially written in.Such as when nand flash memory stores
It when the F state of device and the higher wrong bitrate of G state, can carry out skipping F state/G state composite state, complete E state/F state
Write-in after execute erasing operation.Since write-in state is single-bit bifurcation, Data writing time is available significantly to be changed
It is kind；Simultaneously as being reduced to bifurcation from eight states on every page the storage byte number in every page is reduced, low capacity data are write
The utilization efficiency of fashionable storage unit can significantly be improved.
Fig. 9 gives the erasable 3rd embodiment of QSLC mode of TLC NAND-flash memory, specific writing mode
Also it can be adjusted according to the actual situation, such as to wipe state/B state, B state/D state, D state/F state is sequentially written in data,
After execute erasing operation.
Figure 10 gives the erasable mode of QSLC mode of QLC NAND-flash memory.It is stored for QLC nand flash memory
Device carries out the write-in of lowest threshold single-bit bifurcation first under erase status to memory space, i.e. write-in data are stored in 1
State and 2 states；When new data are written in same storage region while storing data no longer needs, wiping is no longer executed
Except operation, but directly carry out the data write-in of single-bit bifurcation again using 2 states and 3 states as data storage state；Equally with this
Analogize, according to same writing mode, the data of 3 states and 4 states can be arranged to store composite state, the data storage of 4 states and 5 states
The data of composite state ... E state and F state store composite state, and the data storage composite state of F state and G state carrys out successively sequence execution pair
The covering of legacy data and the write-in of new data.It is just final when the data that F state and G state are stored need to wipe or cover
Executing an erasing operation makes storage state return to erase status.It can compare in the error rate bit rate in view of some practical storage states
It is larger, it selective two kinds of storage states of combination can also be sequentially written according to the actual situation.
Figure 11 gives the comparison of data total storage capacity under the erasable mode of different Q SLC.This sentences the storage of TLC nand flash memory
For device, it is assumed that it is 1 that the erasable mode of common standard, which reaches the total amount of data stored when a certain degree of degeneration, if using successively
Write-in erasing state/A state, A state/B state, B state/C state, C state/D state, D state/E state, this six write-ins of E state/F state add primary wipe
The mode removed, can be when reaching identical degree of degeneration, and data storage capacity reaches 1.5, i.e. storing data total amount can promote hundred
/ five ten.If using erasing state and A state, A state and B state, B state and C state, C state and D state, D state and E state, E state is sequentially written in
, can be when reaching identical degree of degeneration with mode F state, F state and G state this seven write-ins plus once wiped, data storage
Amount reaches 1.75, i.e. storing data total amount can promote 75 percent.
Figure 12 gives specific test result.Test is 3D TLC NAND Flash, real in information as shown in the figure
Line is when using the method for the present invention to different masses, and (this time the loop of experiment is after carrying out 1,1000,2000 loop to it
First carry out erasing operation), then it is sequentially written in erasing state and A state, A state and B state, B state and C state, C state and D state, D state and E state, E
State and F state.Individually test the wrong bitrate BER of its random writing after multiple loop operation.Dotted line is to difference
When block is using conventional erasing-writing method, after carrying out 1,1000,2000 cycling to it, an erasing operation is referred to carried out
Carrying out write-once operation again is a cycling.Individually test its random writing after multiple cycling operation
BER.By the comparison discovery to result, the erasable mode of QSLC of the invention and the erasable mode of standard are to NAND Flash
Abrasion on have identical trend, i.e. continuous several times write operation will not bring degeneration and the error rate bit rate of erasable number
Rising.
The present invention is write high state from low state or is selectively skipped intermediate certain states using continuous single-bit bifurcation,
Then erasing operation is carried out again.It is demonstrated experimentally that this mode, which is repeatedly sequentially written in operation, can effectively improve writing speed, mention
High storage unit utilization efficiency promotes memory capacity and service life.The present invention is applicable not only to no used memory block
Domain is also applied for that the region after erasing operation is repeatedly written, and can theoretically dodge under the identical degree of wear in TLC NAND
Data storage total amount 75% can be promoted using QSLC by depositing in memory, and QSLC mode is used in QLC NAND-flash memory
Data storage total amount 87.5% can be promoted.
Claims (4)
1. it is a kind of for improving the data erasing-writing method of multivalue NAND-flash memory data storage total amount, it is characterized in that: for
The service condition in NAND-flash memory space judged in advance, sets memory space threshold value, can memory space lower than setting
When threshold value, execute erasable operation according to the erasable mode of standard, if can memory space be greater than given threshold when, to super multivalue NAND dodge
It deposits memory and carries out the quasi- erasable operation of monodrome, same storage region is repeatedly continuously written into the case where not wiping data with existing
Single bit of information.
2. according to claim 1 for improving the data erasing-writing method of multivalue NAND-flash memory data storage total amount,
It is characterized in that: the threshold value refers to the erasable mode of quasi- monodrome and the erasable mode of the super multivalue of standard specified according to practical application scene
The storage capacity value of switching.
3. according to claim 1 for improving the data erasing-writing method of multivalue NAND-flash memory data storage total amount,
It is characterized in that: the erasable mode of standard be standard TLC perhaps the erasable mode of QLC i.e. every time write-in when complete 8 states or
The one-time write of 16 states executes an erasing operation to legacy data memory space before new data write-in.
4. according to claim 1 for improving the data erasing-writing method of multivalue NAND-flash memory data storage total amount,
It is characterized in that: the erasable operation of quasi- monodrome is after an erase operation, to carry out the company in the case where no longer erasing data with existing
Continuous monodrome bifurcation write operation, data are written every time, and only there are two the distributions of state, and without carrying out data erasing in writing process
Operation.
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| CN114564151A (en) * | 2022-02-28 | 2022-05-31 | 深圳忆联信息系统有限公司 | Method and device for improving SSD data retention, computer equipment and storage medium |
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Application publication date: 20190906 |