CN111782145A

CN111782145A - Answer-type or-type flash memory digital verification method, system, storage medium and terminal

Info

Publication number: CN111782145A
Application number: CN202010612267.1A
Authority: CN
Inventors: 陈胜源
Original assignee: XTX Technology Shenzhen Ltd
Current assignee: Xtx Technology Inc
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2020-10-16
Anticipated expiration: 2040-06-30
Also published as: CN111782145B

Abstract

The invention discloses a digital verification method, a system, a storage medium and a terminal of a response-type or non-type flash memory, wherein the method comprises the steps of predefining abnormal enabling corresponding to abnormal data of a data area in a Nor flash memory chip and corresponding data reliability; sending response information to the Nor flash memory chip; according to the response information, corresponding reliability marking is carried out on abnormal data of a data area in the Nor flash memory chip; by introducing positive reliability and negative reliability parameters, on one hand, the internal characteristics of the analog circuit are truly reflected, so that the verification process is closer to the real behavior of the memory chip, and on the other hand, the internal data bit of the memory chip is flexible and controllable, the verification space is larger, and the verification completeness is higher; the use of macro definition is reduced in the simulation model, the integrity of the simulation model is ensured, and the readability and the portability of the simulation model are improved.

Description

Answer-type or-type flash memory digital verification method, system, storage medium and terminal

Technical Field

The invention relates to a verification method, in particular to a response-type or non-type flash memory digital verification method, a system, a storage medium and a terminal.

Background

The digital verification of the Nor flash memory chip is different from the verification of an SOC chip, the characteristic of an analog circuit is considered in the former, functional points are fully extracted, the analog circuit is reasonably represented and modeled by a digital method, and the verification difficulty is increased.

The verification method and means of the logic function of the memory chip are introduced by taking the memory chip erasing logic as an example. Firstly, the erasing algorithm flow is briefly explained, as shown in fig. 1: from the perspective of digital circuits, the erase operation of the memory chip is a process of changing "0" to "1", and the program operation of the memory chip is a process of changing "1" to "0". After receiving an effective erasing instruction of a user, the memory chip executes erasing operation, reads the data of an erasing area to judge whether the data is all '1', if the data is all '1', skips an algorithm erasing stage, performing soft programming on the data in the selected area, reading the data in the erased area again after the soft programming is completed to judge whether the data is all '1', if not, executing the erasing operation (each time the erasing operation is completed, the erasing number counter is added with 1), soft programming, reading the data in the erasing area again to judge whether the data is all '1', repeating the execution until the data in the erasing area is all '1' and the judgment is passed, if the data is not, when the erasing number counter reaches the set threshold value, and even if the data in the read-erase area is judged to be all '1', the erase operation is not executed any more, the algorithm enters the next stage, the array in which the current data area is located is subjected to enhanced programming, and the erase algorithm is finished after the process is finished. Taking the verification function point that the memory chip erasing algorithm is unsuccessful all the time in the circular erasing and can be safely exited as an example, the data read each time is not all 1 in the judgment process, so as to achieve the purposes of circular erasing and overtime exiting of the algorithm. The conventional verification means without structural judgment generally sets a section of specific code (referred to as "macro definition" in the industry) at a place where a memory chip analog model (constructed in a digital manner and having an analog circuit logic function) reads data, so that the read data is not all "1", and the macro definition is only valid when a specific verification case simulation is executed, in other words, different macro definitions need to be added for verifying different exceptions. Obviously, the macro definitions and the verification cases are in one-to-one correspondence, the scope of the macro definitions is limited, workload is increased due to the fact that the macro definitions are reconstructed every time, meanwhile, a large number of macro definitions of simulation model codes are low in readability, risks of model errors are increased, the simulation cases are transplanted into a new project, verification intentions of the verification cases and the corresponding macro definitions need to be combed again, and accordingly portability is greatly reduced and time cost is increased.

Another common verification means without structure judgment is to forcibly read the data of not all "1" in the verification use case when reading the data in the erasure area (referred to as force operation in the industry), so that the judgment is not performed, but the method avoids adding macro definition, but has lower flexibility, and when a project is transplanted, because the signal in the simulation model is changed, the use case needs to be rechecked and modified, so that the portability is not high, and more importantly, the force operation is used in a large amount, so that the credibility of the verification result is reduced, and the verification risk is greatly increased.

Therefore, the prior art still needs to be improved and developed.

Disclosure of Invention

The invention aims to provide a response-type or non-type flash memory digital verification method, a system, a storage medium and a terminal, which introduce a reliability parameter, truly reflect the internal characteristics of an analog circuit, effectively increase the reliability of a verification result and achieve the aim of improving the verification flexibility.

The technical scheme of the invention is as follows: a response type NOR flash memory digital verification method specifically comprises the following steps:

s1: the method comprises the steps that abnormal enabling corresponding to abnormal data of a data area in a Nor flash memory chip and corresponding data reliability are predefined;

s2: sending response information to the Nor flash memory chip;

s3: and marking the corresponding reliability of the abnormal data of the data area in the Nor flash memory chip according to the response information.

The answer-type or NOR type flash memory digital verification method is characterized in that the reliability comprises 0 and non-0 reliability.

The answer-type or NOR type flash memory digital verification method is characterized in that the non-0 reliability is composed of positive reliability and negative reliability.

The answer-type or non-type flash memory digital verification method comprises the steps that answer information comprises information such as a selected data area, selected abnormal data, corresponding abnormal enabling and corresponding reliability.

A system for using the method for digital authentication of an answerer type flash memory as described in any one of the above, comprising:

a response driving module for sending response information;

the response data channel module is used for storing response information of the Nor flash memory chip;

and the response driving module is used for carrying out corresponding reliability marking on the abnormal data of the data area in the Nor flash memory chip according to the response information.

The system, wherein the system further comprises a clock to increase the response speed of the system.

The system of (a), wherein the clock comprises a reply drive clock and a reply response clock.

The system, wherein the response driver module only marks data with non-0 reliability.

A storage medium having stored therein a computer program which, when run on a computer, causes the computer to perform any of the methods described above.

A terminal comprising a processor and a memory, said memory having stored therein a computer program, said processor being adapted to perform the method of any of the preceding claims by invoking said computer program stored in said memory.

The invention has the following beneficial effects:

(1) the data bit reliability parameter constructed by the technical scheme truly reflects the internal characteristics of the analog circuit, and the reliability and accuracy of the verification result are higher.

(2) According to the answer-type digital verification method provided by the technical scheme, the internal data bit of the memory chip is randomly controlled at the excitation sending end, errors are randomly injected, the verification space is enlarged, and the completeness of verification is improved.

(3) The three functional modules of the response driver, the response data channel and the response constructed by the technical scheme can be embedded into a general verification framework of the Nor flash memory chip as independent functional modules, so that the portability is greatly improved.

(4) The use of macro definition is reduced in the simulation model, the integrity of the simulation model is ensured, and the readability and the portability of the simulation model are improved.

Drawings

FIG. 1 is a diagram illustrating a Nor flash erase algorithm in the prior art.

FIG. 2 is a flow chart of the steps of the method for digital verification of an answerer type flash memory according to the present invention.

Fig. 3 is a response driving timing chart in the present invention.

Fig. 4 is a schematic diagram of the system of the present invention.

FIG. 5 is a flowchart of an erase algorithm for a Nor flash memory chip according to the present invention.

Fig. 6 is a schematic diagram of a terminal in the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize applications of other processes and/or uses of other materials.

As shown in fig. 2, a digital verification method for an answerer-type flash memory is applied to logic verification of a front-end logic design of an Nor flash memory chip, including but not limited to verification of a write/erase algorithm logic function of the Nor flash memory chip, and specifically includes the following steps:

s1: the method comprises the steps of predefining abnormal enabling corresponding to abnormal data of a data area in a Nor flash memory chip and corresponding data reliability.

The technical scheme is characterized in that a corresponding response driving protocol is preset. The reliability of the abnormal data in the data area characterizes the reliability of the abnormal data in the data area, which means that the abnormal data in the data area needs to be executed for N times before being successfully executed when a certain operation instruction is executed. For example, the reliability of a certain bit in the Nor flash memory chip is defined as 3FFFH, wherein FFH (decimal 255) corresponding to low 8 bits indicates that when the number of times of erasing exceeds 255 times, the data bit can be successfully erased to 1, which is called as negative reliability; wherein 3FH (decimal 63) corresponding to 8 bits in height indicates that the data bit can be successfully programmed to 0 when the programming times exceed 63, which is called positive reliability; when a bit reliability is defined to be 0, the data bit can be erased and programmed normally, and the reliability is the highest.

The abnormal enabling means that when abnormal data of a data area in the Nor flash memory chip executes a certain operation instruction, the execution is judged to be successful only when the execution times meet the corresponding reliability.

S2: and sending response information to the Nor flash memory chip.

The response information comprises information such as a selected data area, selected abnormal data, corresponding abnormal enabling, corresponding reliability and the like.

Before an erasing instruction is sent, if the reliability of a certain bit in a Nor flash memory chip is required to be set, a sector address and a bit address need to be selected, an enabling signal is turned on, and then the bit reliability is marked according to a response driving timing diagram.

It should be noted that fig. 3 shows the reliability of setting all bits (32768 bits) in 1 sector, and this driving timing chart is also applicable to setting the reliability of only a certain 1 byte, and the reliability of all bits and any bit of the whole chip.

As shown in fig. 4, a system using the method for digital authentication of an answerer type flash memory as described above includes:

a response driver module a1 for sending response information;

a response data channel module A2 for storing response information of the Nor flash memory chip;

and the answer driving module A3 is used for carrying out corresponding reliability marking on the abnormal data of the data area in the Nor flash memory chip according to the answer information.

The response data channel module a2 contains all signals in the driving protocol and can be expanded. In the response data channel module a2, the reliability of the data is sent serially instead of in parallel, which greatly reduces the resource consumption and improves the simulation speed.

The response driving module a3 obtains reliability data according to a driving protocol, stores the reliability data in a dynamic data group, marks the reliability of all data bits, and when the Nor flash memory chip executes erase and program operations, the reliability of the data bits larger than 0, and the erase and program operations need to judge the relationship between the reliability and the times of repeated erase and program operations, and the operations are successful only if the reliability data is respectively larger than a negative reliability (corresponding to the erase operation) and a positive reliability (corresponding to the program operation).

In some embodiments, the system further comprises a clock clk to increase the system response speed; the frequency of the clock clk is increased to improve the response speed, the clk is an internal clock for simulation, and the Nor flash memory chip to be tested does not interfere with each other, and the timing problem caused by over-high frequency is not needed to be worried about.

It should be noted that bit _ addr (bit address), reliability (reliability), and sector _ addr (sector address) are put on the acknowledge data channel module a2 and updated when the clock clk falls.

In some embodiments, the clock clk comprises a reply drive clock and a reply response clock. The response driving clock and the response responding clock can be the same clock, and the bit _ addr, the reliability and the sector _ addr are obtained from the response data channel module A2 when the clock rises.

It should be noted that the response driver module a3 only marks the data bit with reliability greater than 0, so as to reduce the consumption of resources.

It should be noted that, the Nor flash memory chip automatically executes erasing and programming again when the erasing or programming fails, and the times of repeated erasing and programming are respectively determined by the bit with the lowest negative reliability and the bit with the lowest positive reliability, so that the purpose of traversing the erasing and programming algorithms can be achieved without setting the reliability of each bit.

The method and system described above are now described by way of example only:

as shown in FIG. 5, the verification function point "Nor flash memory chip erase algorithm loop erase has been unsuccessful and can be safely exited" includes the following steps:

1. the abnormal enabling corresponding to the abnormal data of the data area in the Nor flash memory chip and the corresponding data reliability are predefined and stored in the response data channel module A2.

2. The reply driver module A1 sends the reply information in the reply data channel module A2 to the reply driver module A3.

3. And the response driving module A3 carries out corresponding reliability marking on the abnormal data of the data area in the Nor flash memory chip according to the response information.

4. And after marking, sending an erasing instruction and an address to be erased to the Nor flash memory chip.

5. And carrying out an erasing operation on the data area in the selected Nor flash memory chip.

6. And after the erasure is finished, the Nor flash memory chip outputs the checking result to a log file.

7. And judging whether the number of times of the erasing operation cycle execution of the Nor flash memory chip is less than or equal to a threshold value, if so, verifying that the functional point passes, otherwise, failing to pass, and feeding back errors due to errors of the design to be tested.

Wherein, if the maximum number of times of erasing is verified to be an algorithm threshold value:

if the reliability setting times are larger than the threshold value, when the algorithm erasing times reach the threshold value, although the erasing is still unsuccessful, the algorithm exits the loop, which indicates that the design requirements are met, and the verification is passed. Otherwise, the number of times of erasing is continuously increased, the loop cannot exit after the number of times of erasing exceeds the threshold value, the loop is considered to enter the dead loop, the verification is not passed, and the design requirement is not met.

If the number of times of setting the reliability is smaller than the threshold value, the erasing is successful when the number of times of erasing is equal to the reliability, the algorithm naturally enters the next step, a loop is skipped, and the verification is passed. In other words, if the wipe is successful, the algorithm has not jumped out of the loop and continues to wipe, thus also failing to meet the design requirements and failing verification.

The passing standard of the verification is to pay attention to whether the execution condition of the algorithm is expected, and the number of times of erasing is a quantitative judgment parameter.

The present invention also provides a storage medium having a computer program stored therein, which when run on a computer causes the computer to perform the method of any of the above to implement the following functions: the method comprises the steps that abnormal enabling corresponding to abnormal data of a data area in a Nor flash memory chip and corresponding data reliability are predefined; sending response information to the Nor flash memory chip; and marking the corresponding reliability of the abnormal data of the data area in the Nor flash memory chip according to the response information.

Referring to fig. 6, an embodiment of the present invention further provides a terminal, as shown in fig. 7, a terminal B300 includes a processor B301 and a memory B302. The processor B301 is electrically connected to the memory B302. The processor B301 is a control center of the terminal B300, connects various parts of the entire terminal using various interfaces and lines, and performs various functions of the terminal and processes data by running or calling a computer program stored in the memory B302 and calling data stored in the memory B302, thereby performing overall monitoring of the terminal B300.

In this embodiment, the processor B301 in the terminal B300 loads instructions corresponding to one or more computer program processes into the memory B302 according to the following steps, and the processor B301 runs the computer program stored in the memory B302, so as to implement various functions: the method comprises the steps that abnormal enabling corresponding to abnormal data of a data area in a Nor flash memory chip and corresponding data reliability are predefined; sending response information to the Nor flash memory chip; and marking the corresponding reliability of the abnormal data of the data area in the Nor flash memory chip according to the response information.

Memory B302 may be used to store computer programs and data. The memory B302 stores a computer program containing instructions executable in the processor. The computer program may constitute various functional modules. The processor B301 executes various functional applications and data processing by calling a computer program stored in the memory B302.

In the description herein, references to the description of the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.

Claims

1. A response type or non-type flash memory digital verification method is characterized by comprising the following steps:

s2: sending response information to the Nor flash memory chip;

2. The method of claim 1 wherein the reliability comprises 0 and non-0 reliability.

3. The method of claim 2, wherein the non-0 reliability consists of a positive reliability and a negative reliability.

4. The method of claim 1, wherein the response message comprises a selected data region, selected exception data, corresponding exception enable, corresponding reliability, and the like.

5. A system for using the responsive nor flash digital authentication method of any of claims 1-4, comprising:

a response driver module (A1) for sending response information;

a response data channel module (A2) for storing response information of the Nor flash memory chip;

and the answer driving module (A3) is used for carrying out corresponding reliability marking on the abnormal data of the data area in the Nor flash memory chip according to the answer information.

6. The system of claim 5, further comprising a clock to increase system response speed.

7. The system of claim 6, wherein the clock comprises an acknowledge drive clock and an acknowledge response clock.

8. The system according to claim 5, characterized in that the reply driver module (A3) only marks data of non-0 reliability.

9. A storage medium having stored thereon a computer program which, when run on a computer, causes the computer to perform the method of any one of claims 1 to 4.

10. A terminal, characterized in that it comprises a processor (B301) and a memory (B302), said memory (B302) having stored therein a computer program, said processor (B301) being adapted to perform the method of any of claims 1 to 4 by calling said computer program stored in said memory (B302).