CN113409869A - Nonvolatile memory erasing method and device, electronic equipment and storage medium - Google Patents
Nonvolatile memory erasing method and device, electronic equipment and storage medium Download PDFInfo
- Publication number
- CN113409869A CN113409869A CN202110736912.5A CN202110736912A CN113409869A CN 113409869 A CN113409869 A CN 113409869A CN 202110736912 A CN202110736912 A CN 202110736912A CN 113409869 A CN113409869 A CN 113409869A
- Authority
- CN
- China
- Prior art keywords
- erasing
- storage area
- erase
- memory
- selected storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 60
- 238000012545 processing Methods 0.000 claims abstract description 11
- 238000012795 verification Methods 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 28
- 238000004590 computer program Methods 0.000 claims description 19
- 238000012360 testing method Methods 0.000 abstract description 17
- 230000006870 function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3472—Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
- G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
Landscapes
- Read Only Memory (AREA)
Abstract
The invention provides a method, a device, electronic equipment and a storage medium for erasing a nonvolatile memory, which are used for verifying whether data in a selected storage area are all '1' or not when an erasing instruction aiming at the selected storage area is received; if not, executing erasing processing on the selected storage area; if so, ending the operation aiming at the selected storage area; therefore, the testing time can be greatly reduced, the testing efficiency is improved, the erasing operation times of the chip are reduced, and the influence on the service life of the chip is reduced.
Description
Technical Field
The present invention relates to the field of semiconductor memory technologies, and in particular, to a method and an apparatus for erasing a nonvolatile memory, an electronic device, and a storage medium.
Background
The operation range of the erasing operation of the nonvolatile memory is the memory cells on a plurality of word lines, and at present, every time a user sends an erasing operation instruction to a specific memory area, all the memory cells in the selected memory area are directly converted into programming cells, and then an erasing step is performed. However, sometimes, all the memory cells in the selected memory area are erased cells, which do not need to be erased, and it is redundant to erase the memory cells again, and when the chip needs to be tested for many times, the redundant erasing operation needs to be performed for many times, so that the testing time is greatly increased, and the testing efficiency is reduced; in addition, the life of each chip is reduced by one more erasing operation, which affects the life of the chip.
Disclosure of Invention
In view of the foregoing disadvantages of the prior art, an object of the embodiments of the present application is to provide a method and an apparatus for erasing a nonvolatile memory, an electronic device, and a storage medium, which can reduce redundant erasing operations, thereby facilitating improvement of test efficiency and reduction of influence on the service life of a chip.
In a first aspect, an embodiment of the present application provides a method for erasing a nonvolatile memory, including:
A1. verifying whether data in a selected storage area are all '1' when an erasing instruction for the selected storage area is received;
A2. if not, executing erasing processing on the selected storage area;
A3. and if so, ending the operation aiming at the selected storage area.
According to the non-volatile memory erasing method, when an erasing instruction for a selected storage area is received, whether data in the selected storage area are all 1 is verified, if the data are all 1, all storage units of the selected storage area are all erasing units, so that erasing is not needed, and at the moment, the operation for the selected storage area is directly finished, so that the testing time is greatly reduced, the testing efficiency is improved, the erasing operation times of a chip are reduced, and the influence on the service life of the chip is reduced.
Preferably, step a2 includes:
A201. performing a pre-programming operation on the selected memory region to convert all memory cells of the selected memory region into programming cells;
A202. performing an erase operation on the selected memory region to erase all memory cells;
A203. performing an erase verification operation on the selected memory area to verify whether each memory cell is successfully erased;
A204. a soft programming operation is performed on the selected memory region to soft program over-erased memory cells to increase their threshold voltage.
Preferably, after step a204, the method further comprises:
A205. and performing a refresh programming operation on the selected storage area to program the storage units affected by the current erasing operation again to ensure that the threshold voltage of the storage units is high enough.
Preferably, if the erase is not successful as verified in step a203, the process returns to step a202 to perform the erase operation again until the erase is successful or the number of erase operations reaches a preset threshold number.
In a second aspect, an embodiment of the present application provides a nonvolatile memory erasing apparatus, including:
the verification module is used for verifying whether the data in the selected storage area are all 1's when an erasing instruction aiming at the selected storage area is received;
a first execution module configured to execute an erasing process on the selected storage area when the data in the selected storage area is not all "1";
and the second execution module is used for ending the operation aiming at the selected storage area when the data in the selected storage area are all 1.
Preferably, the first executing module, when executing the erasing process on the selected storage area:
performing a pre-programming operation on the selected memory region to convert all memory cells of the selected memory region into programming cells;
performing an erase operation on the selected memory region to erase all memory cells;
performing an erase verification operation on the selected memory area to verify whether each memory cell is successfully erased;
a soft programming operation is performed on the selected memory region to soft program over-erased memory cells to increase their threshold voltage.
Preferably, the first execution module, after performing the soft programming operation on the selected storage region, further:
and performing a refresh programming operation on the selected storage area to program the storage units affected by the current erasing operation again to ensure that the threshold voltage of the storage units is high enough.
Preferably, when the first execution module performs the erase process on the selected storage area, if the erase verification operation verifies that the erase is unsuccessful, the first execution module performs the erase operation again until the erase is successful or the number of times of the erase operation reaches a preset number threshold.
In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, where the memory stores a computer program, and the processor is configured to execute the steps of the nonvolatile memory erasing method by calling the computer program stored in the memory.
In a fourth aspect, the present application provides a storage medium, on which a computer program is stored, wherein the computer program is configured to execute the steps of the nonvolatile memory erasing method as described when executed by a processor.
Has the advantages that:
according to the method, the device, the electronic equipment and the storage medium for erasing the nonvolatile memory, provided by the embodiment of the application, when an erasing instruction for a selected storage area is received, whether all data in the selected storage area are 1 is verified; if not, executing erasing processing on the selected storage area; if so, ending the operation aiming at the selected storage area; if the data in the selected storage area are all '1', the data indicate that all the storage units in the selected storage area are all the erasing units, so that erasing is not needed, and at the moment, the operation on the selected storage area is directly finished, so that the test time is greatly reduced, the test efficiency is improved, the erasing operation times on the chip are reduced, and the influence on the service life of the chip is reduced.
Drawings
Fig. 1 is a flowchart of a method for erasing a nonvolatile memory according to an embodiment of the present disclosure.
Fig. 2 is a flowchart of an erasing process in the nonvolatile memory erasing method according to the embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of a nonvolatile memory erasing apparatus according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
The following disclosure provides embodiments or examples for implementing different configurations of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art will recognize applications of other processes and/or uses of other materials.
Referring to fig. 1, an erasing method of a nonvolatile memory according to an embodiment of the present invention includes:
A1. verifying whether data in a selected storage area are all '1' when an erasing instruction for the selected storage area is received;
A2. if not, executing erasing processing on the selected storage area;
A3. and if so, ending the operation aiming at the selected storage area.
According to the non-volatile memory erasing method, when an erasing instruction aiming at a selected storage area is received, whether the data in the selected storage area are all '1' is verified, if the data are all '1', all the storage units of the selected storage area are all the erasing units, so that the erasing is not needed, at the moment, the operation aiming at the selected storage area is directly finished, the testing time is greatly shortened, the testing efficiency is improved, the erasing operation times of a chip are reduced, and the influence on the service life of the chip is reduced.
In some embodiments, the erase command in step a1 includes identification information of the selected storage area, which may be, but is not limited to, location information or label information of the selected storage area. Thus, in step a1, it is verified whether the data in the corresponding storage areas are all "1" based on the identification information.
In the present embodiment, referring to fig. 2, step a2 includes:
A201. performing a pre-programming operation on the selected memory region to convert all memory cells of the selected memory region into programming cells;
A202. performing an erase operation on the selected memory region to erase all memory cells;
A203. performing an erase verification operation on the selected memory area to verify whether each memory cell is successfully erased;
A204. a soft programming operation is performed on the selected memory region to soft program over-erased memory cells to increase their threshold voltage.
In step a201, the process of converting all memory cells of the selected memory area into programming cells is as follows: the method comprises the steps of reading, programming and verifying, specifically, firstly, reading is carried out on a selected storage area, whether programming is needed or not is judged, if not, the current loop is jumped out, the next step is jumped to (step A202), if yes, programming operation is carried out on a unit needing programming, then the step is jumped to the verifying operation step, whether programming is successful or not is verified in the verifying operation step, and if not, programming is continued until programming is successful or the programming frequency reaches a preset frequency threshold.
In step a202, erasing is performed by applying an erase pulse to memory cells in a selected memory area; when the erasing pulse is applied, the erasing pulse can be simultaneously applied to all the storage units, or the erasing pulse can be applied to each storage unit one by one, or the storage units are divided into a plurality of groups, the erasing pulse is applied to each group of the storage units one by one, and the erasing pulse is simultaneously applied to the storage units in the same group; this is not limited herein.
For example, in some embodiments, the selected memory cells are divided into a plurality of groups according to the voltage range in which the erase voltage required by each memory cell is located, the erase voltage required by the memory cells of the same group is within the same voltage range, so that the erase pulse is applied to the memory cells of each group by group, the erase pulse is simultaneously applied to the memory cells of the same group, and the voltage of the applied erase pulse is the characteristic voltage of the memory cells of the group (which may be the maximum value, the minimum value or the average value of the erase voltages required by the memory cells in the group of memory cells, or the maximum value, the minimum value or the middle value of the voltage range in which the erase voltage required by the memory cells in the group of memory cells is within). Therefore, the required voltage is applied to each group of storage units, the probability of successful erasing after one-time erasing is improved, the times of erasing operation can be reduced, and the erasing efficiency is improved.
The process of performing the erase verification operation on the selected storage area in step a203 is as follows: and reading the area needing to be erased currently, judging whether the threshold voltage reaches a set value, marking the memory unit which is not successfully erased, and continuously erasing the memory unit next time.
The process of performing the soft programming operation on the selected storage area in step a204 is as follows: the method comprises the steps of reading operation, programming operation and verification operation, specifically, firstly, reading operation is carried out on a selected storage area, whether programming is needed or not is judged, if not, the current loop is jumped out, the next step is jumped, if yes, programming operation is carried out on a unit needing programming, then the step is jumped to the verification operation step, whether programming is successful or not is verified in the verification operation step, and if not, programming is continued until programming is successful or the programming frequency reaches a preset frequency threshold value.
Preferably, after step a204, the method further comprises:
A205. and performing a refresh programming operation on the selected storage area to program the storage units affected by the current erasing operation again to ensure that the threshold voltage of the storage units is high enough.
In step a205, the process of performing the refresh programming operation on the selected memory area is as follows: the method comprises the steps of reading operation, programming operation and verification operation, specifically, firstly, reading operation is carried out on a selected storage area, whether programming is needed or not is judged, if not, the current loop is jumped out, the next step is jumped, if yes, programming operation is carried out on a unit needing programming, then the step is jumped to the verification operation step, whether programming is successful or not is verified in the verification operation step, and if not, programming is continued until programming is successful or the programming frequency reaches a preset frequency threshold value.
Generally, it is difficult for one erase operation to successfully erase all the memory cells, so if the erase is not verified in step a203, the process returns to step a202 to perform the erase operation again until the erase is successful or the number of erase operations reaches a preset threshold number.
Wherein, if all the memory cells become the erasing unit, the erasing operation is successful. Here, in order to avoid the erasing time being too long, when the number of times of the erasing operation performed in the current erasing process reaches the preset number threshold, the next erasing operation is not performed any more, and at this time, it may be determined that the erasing operation has failed, so that the current erasing process is ended, and a corresponding alarm signal may be sent out.
As can be seen from the above, the nonvolatile memory erasing method verifies whether all data in a selected storage area are "1" or not by receiving an erasing instruction for the selected storage area; if not, executing erasing processing on the selected storage area; if so, ending the operation aiming at the selected storage area; if the data in the selected storage area are all '1', it indicates that all the storage units in the selected storage area are all erasing units, so that erasing is not needed, and at this time, the operation on the selected storage area is directly ended, thereby greatly reducing the testing time, improving the testing efficiency, reducing the number of erasing operations on the chip, and reducing the influence on the service life of the chip.
Referring to fig. 3, an embodiment of the present invention provides a nonvolatile memory erasing apparatus, including:
the verification module 1 is used for verifying whether the data in the selected storage area are all '1' or not when an erasing instruction aiming at the selected storage area is received;
a first executing module 2, configured to execute an erasing process on the selected storage area when the data in the selected storage area is not all "1";
and the second execution module 3 is configured to end this operation on the selected storage area when all the data in the selected storage area are "1".
In some embodiments, the erasure instruction includes identification information of the selected storage area, which may be location information or label information of the selected storage area, but is not limited thereto. Thus, the verification module 1 verifies whether all the data in the corresponding storage areas are "1" based on the identification information.
In this embodiment, when the first execution module 2 executes the erasing process on the selected storage area:
performing a pre-programming operation on the selected memory region to convert all memory cells of the selected memory region into programming cells;
performing an erase operation on the selected memory region to erase all memory cells;
performing an erase verification operation on the selected memory area to verify whether each memory cell is successfully erased;
a soft programming operation is performed on the selected memory region to soft program over-erased memory cells to increase their threshold voltage.
The process of the first execution module 2 converting all the memory cells of the selected memory area into the programming cells is as follows: the method comprises the steps of reading operation, programming operation and verification operation, specifically, firstly, reading operation is carried out on a selected storage area, whether programming is needed or not is judged, if not, the current loop is jumped out, the next step is jumped, if yes, programming operation is carried out on a unit needing programming, then the step is jumped to the verification operation step, whether programming is successful or not is verified in the verification operation step, and if not, programming is continued until programming is successful or the programming frequency reaches a preset frequency threshold value.
The first execution module 2 performs erasing by applying an erasing pulse to the memory cells of the selected memory area; when the erasing pulse is applied, the erasing pulse can be simultaneously applied to all the storage units, or the erasing pulse can be applied to each storage unit one by one, or the storage units are divided into a plurality of groups, the erasing pulse is applied to each group of the storage units one by one, and the erasing pulse is simultaneously applied to the storage units in the same group; this is not limited herein.
For example, in some embodiments, the selected memory cells are divided into a plurality of groups according to the voltage range in which the erase voltage required by each memory cell is located, the erase voltage required by the memory cells of the same group is within the same voltage range, so that the erase pulse is applied to the memory cells of each group by group, the erase pulse is simultaneously applied to the memory cells of the same group, and the voltage of the applied erase pulse is the characteristic voltage of the memory cells of the group (which may be the maximum value, the minimum value or the average value of the erase voltages required by the memory cells in the group of memory cells, or the maximum value, the minimum value or the middle value of the voltage range in which the erase voltage required by the memory cells in the group of memory cells is within). Therefore, the required voltage is applied to each group of storage units, the probability of successful erasing after one-time erasing is improved, the times of erasing operation can be reduced, and the erasing efficiency is improved.
The process of the first execution module 2 executing the erase verification operation on the selected storage area is as follows: and reading the area needing to be erased currently, judging whether the threshold voltage reaches a set value, marking the memory unit which is not successfully erased, and continuously erasing the memory unit next time.
The process of the first execution module 2 performing the soft programming operation on the selected storage area is as follows: the method comprises the steps of reading operation, programming operation and verification operation, specifically, firstly, reading operation is carried out on a selected storage area, whether programming is needed or not is judged, if not, the current loop is jumped out, the next step is jumped, if yes, programming operation is carried out on a unit needing programming, then the step is jumped to the verification operation step, whether programming is successful or not is verified in the verification operation step, and if not, programming is continued until programming is successful or the programming frequency reaches a preset frequency threshold value.
Preferably, the first execution module 2, after performing the soft programming operation on the selected storage area, further:
and performing a refresh programming operation on the selected storage area to program the storage units affected by the current erasing operation again to ensure that the threshold voltage of the storage units is high enough.
The process of the first execution module 2 executing the refresh programming operation on the selected storage area is as follows: the method comprises the steps of reading operation, programming operation and verification operation, specifically, firstly, reading operation is carried out on a selected storage area, whether programming is needed or not is judged, if not, the current loop is jumped out, the next step is jumped, if yes, programming operation is carried out on a unit needing programming, then the step is jumped to the verification operation step, whether programming is successful or not is verified in the verification operation step, and if not, programming is continued until programming is successful or the programming frequency reaches a preset frequency threshold value.
Generally, it is difficult for an erase operation to successfully erase all the memory cells, so when the first execution module 2 performs the erase process on the selected memory area, if the erase verification operation verifies that the erase operation is unsuccessful, the erase operation is performed again until the erase operation is successful or the number of erase operations reaches a preset number threshold.
Wherein, if all the memory cells become the erasing unit, the erasing operation is successful. Here, in order to avoid the erasing time being too long, when the number of times of the erasing operation performed in the current erasing process reaches the preset number threshold, the next erasing operation is not performed any more, and at this time, it may be determined that the erasing operation has failed, so that the current erasing process is ended, and a corresponding alarm signal may be sent out.
As can be seen from the above, the nonvolatile memory erasing apparatus verifies whether all data in a selected storage area are "1" or not by receiving an erase instruction for the selected storage area; if not, executing erasing processing on the selected storage area; if so, ending the operation aiming at the selected storage area; if the data in the selected storage area are all '1', it indicates that all the storage units in the selected storage area are all erasing units, so that erasing is not needed, and at this time, the operation on the selected storage area is directly ended, thereby greatly reducing the testing time, improving the testing efficiency, reducing the number of erasing operations on the chip, and reducing the influence on the service life of the chip.
Referring to fig. 4, an electronic device 100 according to an embodiment of the present application further includes a processor 101 and a memory 102, where the memory 102 stores a computer program, and the processor 101 is configured to execute the steps of the nonvolatile memory erasing method by calling the computer program stored in the memory 102.
The processor 101 is electrically connected to the memory 102. The processor 101 is a control center of the electronic device 100, connects various parts of the entire electronic device using various interfaces and lines, and performs various functions of the electronic device and processes data by running or calling a computer program stored in the memory 102 and calling data stored in the memory 102, thereby performing overall monitoring of the electronic device.
The memory 102 may be used to store computer programs and data. The memory 102 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 101 executes various functional applications and data processing by calling a computer program stored in the memory 102.
In this embodiment, the processor 101 in the electronic device 100 loads instructions corresponding to one or more processes of the computer program into the memory 102, and the processor 101 runs the computer program stored in the memory 102 according to the following steps, so as to implement various functions: verifying whether data in a selected storage area are all '1' when an erasing instruction for the selected storage area is received; if not, executing erasing processing on the selected storage area; and if so, ending the operation aiming at the selected storage area.
As can be seen from the above, the electronic device verifies whether all data in the selected storage area are "1" or not by receiving an erase instruction for the selected storage area; if not, executing erasing processing on the selected storage area; if so, ending the operation aiming at the selected storage area; if the data in the selected storage area are all '1', it indicates that all the storage units in the selected storage area are all erasing units, so that erasing is not needed, and at this time, the operation on the selected storage area is directly ended, thereby greatly reducing the testing time, improving the testing efficiency, reducing the number of erasing operations on the chip, and reducing the influence on the service life of the chip.
An embodiment of the present application further provides a storage medium, on which a computer program is stored, where the computer program runs the steps of the above-mentioned nonvolatile memory erasing method when being executed by a processor, so as to implement the following functions: verifying whether data in a selected storage area are all '1' when an erasing instruction for the selected storage area is received; if not, executing erasing processing on the selected storage area; and if so, ending the operation aiming at the selected storage area.
The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, which are substantially the same as the present invention.
Claims (10)
1. A method of erasing a non-volatile memory, comprising the steps of:
A1. verifying whether data in a selected storage area are all '1' when an erasing instruction for the selected storage area is received;
A2. if not, executing erasing processing on the selected storage area;
A3. and if so, ending the operation aiming at the selected storage area.
2. The method of claim 1, wherein step a2 includes:
A201. performing a pre-programming operation on the selected memory region to convert all memory cells of the selected memory region into programming cells;
A202. performing an erase operation on the selected memory region to erase all memory cells;
A203. performing an erase verification operation on the selected memory area to verify whether each memory cell is successfully erased;
A204. a soft programming operation is performed on the selected memory region to soft program over-erased memory cells to increase their threshold voltage.
3. The method of claim 2, further comprising, after step a 204:
A205. and performing a refresh programming operation on the selected storage area to program the storage units affected by the current erasing operation again to ensure that the threshold voltage of the storage units is high enough.
4. The method of claim 2, wherein if the erase is not successful as verified in step a203, the method returns to step a202 to perform the erase operation again until the erase operation is successful or the number of erase operations reaches a predetermined threshold number.
5. A non-volatile memory erasing apparatus, comprising:
the verification module is used for verifying whether the data in the selected storage area are all 1's when an erasing instruction aiming at the selected storage area is received;
a first execution module configured to execute an erasing process on the selected storage area when the data in the selected storage area is not all "1";
and the second execution module is used for ending the operation aiming at the selected storage area when the data in the selected storage area are all 1.
6. The apparatus of claim 5, wherein the first execution module, when executing the erase process on the selected memory region:
performing a pre-programming operation on the selected memory region to convert all memory cells of the selected memory region into programming cells;
performing an erase operation on the selected memory region to erase all memory cells;
performing an erase verification operation on the selected memory area to verify whether each memory cell is successfully erased;
a soft programming operation is performed on the selected memory region to soft program over-erased memory cells to increase their threshold voltage.
7. The non-volatile memory erasing apparatus of claim 6, wherein the first performing module, after performing the soft programming operation on the selected memory region, further:
and performing a refresh programming operation on the selected storage area to program the storage units affected by the current erasing operation again to ensure that the threshold voltage of the storage units is high enough.
8. The apparatus of claim 6, wherein the first execution module, when performing the erase process on the selected storage area, if the erase verification operation verifies that the erase operation is not successful, performs the erase operation again until the erase operation is successful or the number of erase operations reaches a preset threshold number.
9. An electronic device, characterized in that it comprises a processor and a memory, in which a computer program is stored, said processor being adapted to carry out the steps of the non-volatile memory erasing method according to any one of claims 1-4 by calling said computer program stored in said memory.
10. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the non-volatile memory erasing method of any of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110736912.5A CN113409869A (en) | 2021-06-30 | 2021-06-30 | Nonvolatile memory erasing method and device, electronic equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110736912.5A CN113409869A (en) | 2021-06-30 | 2021-06-30 | Nonvolatile memory erasing method and device, electronic equipment and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113409869A true CN113409869A (en) | 2021-09-17 |
Family
ID=77680588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110736912.5A Pending CN113409869A (en) | 2021-06-30 | 2021-06-30 | Nonvolatile memory erasing method and device, electronic equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113409869A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116991611A (en) * | 2023-05-22 | 2023-11-03 | 苏州科美信息技术有限公司 | Memory page subdivision state identification method, system, equipment and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060044919A1 (en) * | 2004-08-30 | 2006-03-02 | Spansion Llc | Non-volatile memory device and erasing method therefor |
| CN103426472A (en) * | 2013-07-31 | 2013-12-04 | 辉芒微电子（深圳）有限公司 | Programming system and method of Nor Flash memory |
| CN103606383A (en) * | 2013-11-11 | 2014-02-26 | 广东博观科技有限公司 | Device and method for adaptively grouping chip erasing word lines |
| CN103811066A (en) * | 2012-11-15 | 2014-05-21 | 北京兆易创新科技股份有限公司 | Erasing method and system of nonvolatile memory |
| CN104051012A (en) * | 2013-03-15 | 2014-09-17 | 北京兆易创新科技股份有限公司 | Memory erase method and device |
| CN105575430A (en) * | 2014-10-11 | 2016-05-11 | 北京兆易创新科技股份有限公司 | Erasing method of nonvolatile memory |
| US10802962B1 (en) * | 2019-05-30 | 2020-10-13 | Winbond Electronics Corp. | Memory device and control method for performing refresh operation based on erasing loop number |
| CN112542203A (en) * | 2020-12-31 | 2021-03-23 | 深圳市芯天下技术有限公司 | Bad block repairing method and device for nonvolatile memory, storage medium and terminal |
-
2021
- 2021-06-30 CN CN202110736912.5A patent/CN113409869A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060044919A1 (en) * | 2004-08-30 | 2006-03-02 | Spansion Llc | Non-volatile memory device and erasing method therefor |
| CN103811066A (en) * | 2012-11-15 | 2014-05-21 | 北京兆易创新科技股份有限公司 | Erasing method and system of nonvolatile memory |
| CN104051012A (en) * | 2013-03-15 | 2014-09-17 | 北京兆易创新科技股份有限公司 | Memory erase method and device |
| CN103426472A (en) * | 2013-07-31 | 2013-12-04 | 辉芒微电子（深圳）有限公司 | Programming system and method of Nor Flash memory |
| CN103606383A (en) * | 2013-11-11 | 2014-02-26 | 广东博观科技有限公司 | Device and method for adaptively grouping chip erasing word lines |
| CN105575430A (en) * | 2014-10-11 | 2016-05-11 | 北京兆易创新科技股份有限公司 | Erasing method of nonvolatile memory |
| US10802962B1 (en) * | 2019-05-30 | 2020-10-13 | Winbond Electronics Corp. | Memory device and control method for performing refresh operation based on erasing loop number |
| CN112542203A (en) * | 2020-12-31 | 2021-03-23 | 深圳市芯天下技术有限公司 | Bad block repairing method and device for nonvolatile memory, storage medium and terminal |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116991611A (en) * | 2023-05-22 | 2023-11-03 | 苏州科美信息技术有限公司 | Memory page subdivision state identification method, system, equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20110063909A1 (en) | Nonvolatile semiconductor memory and method of testing the same | |
| US5991206A (en) | Method of erasing a flash memory | |
| US6903980B2 (en) | Nonvolatile semiconductor memory device capable of correcting over-erased memory cells | |
| CN101271731A (en) | Method of erasing flash memory device | |
| JP2007004955A (en) | Nonvolatile semiconductor memory device | |
| CN116880782B (en) | Embedded memory and testing method thereof | |
| CN107045888B (en) | Data erasing method | |
| CN113409869A (en) | Nonvolatile memory erasing method and device, electronic equipment and storage medium | |
| US10176876B2 (en) | Memory control method and apparatus for programming and erasing areas | |
| CN111667872A (en) | Method, system, storage medium and terminal device for power-on repair of over-erasure interference | |
| KR102019567B1 (en) | Semiconductor memory device and operation setting method thereof | |
| CN110473585B (en) | Replacement method, device and equipment for erasing failed storage unit and storage medium | |
| US8713406B2 (en) | Erasing a non-volatile memory (NVM) system having error correction code (ECC) | |
| CN109390016B (en) | Erasing method and device for NOR flash memory | |
| US10490297B2 (en) | Memory storage apparatus and method for testing memory storage apparatus | |
| CN109509503A (en) | The method and storage system of programming nonvolatile memory | |
| CN111785313B (en) | Method, system, storage medium and terminal for reducing over-erasure phenomenon and erasure time | |
| TWI443665B (en) | Over-erased verification and repair methods for flash memory | |
| CN111951868B (en) | Method and device for controlling erasing | |
| CN113409865A (en) | Nonvolatile memory erasing method and device, electronic equipment and storage medium | |
| CN114005479A (en) | Method and device for improving NOR Flash data read-write reliability and application thereof | |
| CN113409862A (en) | Memory erasing method and device, electronic equipment and storage medium | |
| CN113409863A (en) | Method and device for reducing erasing time, electronic equipment and storage medium | |
| CN115312108B (en) | Read-write method of memory chip, electronic device and storage medium | |
| KR100571266B1 (en) | Erasing Flash Memory Cells |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |