CN113409865A - Nonvolatile memory erasing method and device, electronic equipment and storage medium - Google Patents
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- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/345—Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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Abstract
The invention provides a nonvolatile memory erasing method, a nonvolatile memory erasing device, electronic equipment and a storage medium, wherein erasing operation is carried out on a selected storage unit; performing erase verification on the selected memory cells, applying a first voltage to the gates of the selected memory cells and applying a first negative voltage to the gates of the unselected memory cells when performing a read operation of the erase verification; therefore, the non-selected memory cells can be completely turned off, so that extra drain current can not be generated, and the probability of reading the non-successfully-erased memory cells into the successfully-erased memory cells is reduced.
Description
Technical Field
The present invention relates to the field of semiconductor memory technologies, and in particular, to a method and an apparatus for erasing a nonvolatile memory, an electronic device, and a storage medium.
Background
When the nonvolatile memory is erased, a part of the storage units have an over-erase phenomenon. When erasing is performed, if the characteristics of the selected storage cells are not completely consistent, some cells may need to be erased successfully by hundreds of times of erasing pulses, and some cells may be erased successfully by one time of erasing, in this case, the cells which are easy to erase are also erased by hundreds of times, and become over-erased cells, and the threshold voltage of the over-erased cells may be less than 0 v.
In the prior art, when a nonvolatile memory is erased, an erase verification step is generally included to verify whether a memory cell is successfully erased, in the erase verification step, a voltage of 0v is usually applied to a gate of an unselected memory cell, and since the unselected memory cell may be an over-erased cell, a threshold voltage of the unselected memory cell may be smaller than 0v, so that a large drain current is generated, and as a chip capacity becomes larger, memory cells on one bit line increase, and if drain currents of a plurality of memory cells are overlapped, a read data error may be caused, so that the memory cell which is not successfully erased is read as a memory cell which is successfully erased.
Disclosure of Invention
In view of the foregoing shortcomings in the prior art, embodiments of the present application provide a method, an apparatus, an electronic device, and a storage medium for erasing a nonvolatile memory, which can reduce drain current of unselected memory cells when erasing the nonvolatile memory, thereby reducing the probability of reading the memory cells that have not been successfully erased into memory cells that have been successfully erased.
In a first aspect, an embodiment of the present application provides a method for erasing a nonvolatile memory, including:
A1. performing an erase operation on the selected memory cell;
A2. and carrying out erasing verification on the selected memory cells, applying a first voltage to the gates of the selected memory cells and applying a first negative voltage to the gates of the unselected memory cells when performing a read operation of the erasing verification.
According to the erasing method of the nonvolatile memory provided by the embodiment of the application, when the selected memory cell is subjected to erasing verification, in the read operation of the erasing verification, a negative voltage is applied to the grid electrode of the unselected memory cell, so that the unselected memory cell is completely turned off, extra drain current is not generated, current judgment of other memory cells on the same bit line is not influenced, and the actual threshold voltage of the selected memory cell is read more accurately; therefore, the drain current of the unselected memory cells can be reduced when the nonvolatile memory is erased, so that the probability of reading the memory cells which are not successfully erased into the memory cells which are successfully erased is reduced.
Preferably, in step a2, a second voltage is applied to the gates of the memory cells to be soft-programmed and a second negative voltage is applied to the gates of the unselected memory cells when performing the soft programming operation of the erase verification.
Preferably, the first negative voltage and the second negative voltage are not less than-3V.
In a second aspect, an embodiment of the present application provides a nonvolatile memory erasing apparatus, including:
the erasing module is used for erasing the selected memory unit;
and the verification module is used for carrying out erasing verification on the selected memory cells, applying a first voltage to the grid electrode of the selected memory cells when the read operation of the erasing verification is carried out, and applying a first negative voltage to the grid electrode of the unselected memory cells.
Preferably, the verification module, when performing erase verification on the selected memory cell:
and applying a second voltage to the gates of the memory cells needing to be subjected to soft programming and applying a second negative voltage to the gates of the unselected memory cells when performing the soft programming operation of the erase verification.
Preferably, the first negative voltage and the second negative voltage are not less than-3V.
In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, where the memory stores a computer program, and the processor is configured to execute the steps of the nonvolatile memory erasing method by calling the computer program stored in the memory.
In a fourth aspect, the present application provides a storage medium, on which a computer program is stored, where the computer program runs the steps of the nonvolatile memory erasing method as described when being executed by a processor.
Has the advantages that:
according to the method, the device, the electronic equipment and the storage medium for erasing the nonvolatile memory, the selected storage unit is erased; performing erase verification on the selected memory cells, applying a first voltage to the gates of the selected memory cells and applying a first negative voltage to the gates of the unselected memory cells when performing a read operation of the erase verification; therefore, the non-selected memory cells can be completely turned off, extra drain current can not be generated, current judgment of other memory cells on the same bit line can not be influenced, and the actual threshold voltage of the selected memory cells can be read more accurately; therefore, the drain current of the unselected memory cells can be reduced when the nonvolatile memory is erased, so that the probability of reading the memory cells which are not successfully erased into the memory cells which are successfully erased is reduced.
Drawings
Fig. 1 is a flowchart of a method for erasing a nonvolatile memory according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a nonvolatile memory erasing apparatus according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
The following disclosure provides embodiments or examples for implementing different configurations of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but those of ordinary skill in the art will recognize applications of other processes and/or uses of other materials.
Referring to fig. 1, an erasing method of a nonvolatile memory according to an embodiment of the present invention includes:
A1. performing an erase operation on the selected memory cell;
A2. and carrying out erasing verification on the selected memory cells, applying a first voltage to the gates of the selected memory cells and applying a first negative voltage to the gates of the unselected memory cells when performing a read operation of the erasing verification.
According to the erasing method of the nonvolatile memory, when the selected memory cell is subjected to erasing verification, in the read operation of the erasing verification, negative voltage is applied to the grid electrode of the unselected memory cell, so that the unselected memory cell is completely turned off, extra drain current is not generated, current judgment of other memory cells on the same bit line is not influenced, and the actual threshold voltage of the selected memory cell is read more accurately; therefore, the drain current of the unselected memory cells can be reduced when the nonvolatile memory is erased, so that the probability of reading the memory cells which are not successfully erased into the memory cells which are successfully erased is reduced.
In practical applications, step a1 includes:
acquiring identification information of the selected storage unit;
and applying an erasing pulse to the corresponding memory cell according to the identification information.
The identification information may be, but is not limited to, location information or label information of the selected storage unit.
When the erasing pulse is applied, the erasing pulse can be simultaneously applied to all the selected memory cells, or the erasing pulse can be applied to the selected memory cells one by one, or the selected memory cells are divided into a plurality of groups, the erasing pulse is applied to each group of memory cells one by one, and the erasing pulse is simultaneously applied to the memory cells in the same group; this is not limited herein.
For example, in some embodiments, the selected memory cells are divided into a plurality of groups according to the voltage range in which the erase voltage required by each memory cell is located, the erase voltage required by the memory cells of the same group is within the same voltage range, so that the erase pulse is applied to the memory cells of each group by group, the erase pulse is simultaneously applied to the memory cells of the same group, and the voltage of the applied erase pulse is the characteristic voltage of the memory cells of the group (which may be the maximum value, the minimum value or the average value of the erase voltages required by the memory cells in the group of memory cells, or the maximum value, the minimum value or the middle value of the voltage range in which the erase voltage required by the memory cells in the group of memory cells is within). Therefore, the required voltage is applied to each group of storage units, the probability of successful erasing after one-time erasing is improved, the times of erasing operation can be reduced, and the erasing efficiency is improved.
In step a2, when it is required to determine whether a certain memory cell is successfully erased, a first voltage is applied to the gate of the selected memory cell by using the memory cell as the selected memory cell, so as to read the drain current of the selected memory cell and calculate the threshold voltage of the corresponding memory cell, thereby determining whether the memory cell is successfully erased. The first voltage can be set according to actual needs.
In practice, the process of erase verification further includes a soft programming operation, and in the conventional method, during the soft programming operation, a command voltage is also applied to the gates of the unselected memory cells, at this time, the over-erased cells in the unselected memory cells generate drain currents, and the superposition of the drain currents of the over-erased cells on the same bit line forms a non-negligible current, and the presence of the current consumes the programming current, which increases the programming time and is very likely to result in unsuccessful programming. To this end, in some preferred embodiments, in step a2, a second voltage is applied to the gates of the memory cells to be soft-programmed and a second negative voltage is applied to the gates of the unselected memory cells when performing the soft programming operation of the erase verification.
Wherein the second voltage is set according to actual needs.
The second negative voltage is applied to the grid electrode of the unselected memory unit, so that the unselected memory unit is completely turned off, and extra drain current is not generated, therefore, the programming current is not consumed due to the extra drain current, and the programming efficiency and the programming success rate can be greatly improved.
Preferably, the first negative voltage and the second negative voltage are not less than-3V. Preferably, the first and second negative voltages are-3V, and typically, the threshold voltage of an over-erased cell is typically-2V-0V, where the use of-3V reliably ensures that the cell is fully turned off.
In view of the above, the nonvolatile memory erasing method is to erase the selected memory cell; performing erase verification on the selected memory cells, applying a first voltage to the gates of the selected memory cells and applying a first negative voltage to the gates of the unselected memory cells when performing a read operation of the erase verification; therefore, the non-selected memory cells can be completely turned off, extra drain current can not be generated, current judgment of other memory cells on the same bit line can not be influenced, and the actual threshold voltage of the selected memory cells can be read more accurately; therefore, the drain current of the unselected memory cells can be reduced when the nonvolatile memory is erased, so that the probability of reading the memory cells which are not successfully erased into the memory cells which are successfully erased is reduced. In addition, a second negative voltage is applied to the gates of the unselected memory cells by applying a second voltage to the gates of the memory cells needing to be subjected to soft programming when the soft programming operation of the erase verification is performed; the programming efficiency and the programming success rate can be greatly improved.
Referring to fig. 2, an embodiment of the present invention provides a nonvolatile memory erasing apparatus, including:
the erasing module 1 is used for erasing the selected memory cells;
and the verification module 2 is used for carrying out erasing verification on the selected memory cells, applying a first voltage to the grid electrode of the selected memory cells when the read operation of the erasing verification is carried out, and applying a first negative voltage to the grid electrode of the unselected memory cells.
In practical applications, the erasing module 1, when performing an erasing operation on a selected memory cell:
acquiring identification information of the selected storage unit;
and applying an erasing pulse to the corresponding memory cell according to the identification information.
The identification information may be, but is not limited to, location information or label information of the selected storage unit.
When the erasing pulse is applied, the erasing pulse can be simultaneously applied to all the selected memory cells, or the erasing pulse can be applied to the selected memory cells one by one, or the selected memory cells are divided into a plurality of groups, the erasing pulse is applied to each group of memory cells one by one, and the erasing pulse is simultaneously applied to the memory cells in the same group; this is not limited herein.
For example, in some embodiments, the selected memory cells are divided into a plurality of groups according to the voltage range in which the erase voltage required by each memory cell is located, the erase voltage required by the memory cells of the same group is within the same voltage range, so that the erase pulse is applied to the memory cells of each group by group, the erase pulse is simultaneously applied to the memory cells of the same group, and the voltage of the applied erase pulse is the characteristic voltage of the memory cells of the group (which may be the maximum value, the minimum value or the average value of the erase voltages required by the memory cells in the group of memory cells, or the maximum value, the minimum value or the middle value of the voltage range in which the erase voltage required by the memory cells in the group of memory cells is within). Therefore, the required voltage is applied to each group of storage units, the probability of successful erasing after one-time erasing is improved, the times of erasing operation can be reduced, and the erasing efficiency is improved.
When it is required to determine whether a certain memory cell is successfully erased, the verification module 2 applies a first voltage to the gate of the selected memory cell by using the memory cell as the selected memory cell, so as to read the drain current of the selected memory cell to calculate the threshold voltage of the corresponding memory cell, and determine whether the memory cell is successfully erased. The first voltage can be set according to actual needs.
In practice, the process of erase verification further includes a soft programming operation, and in the conventional method, during the soft programming operation, a command voltage is also applied to the gates of the unselected memory cells, at this time, the over-erased cells in the unselected memory cells generate drain currents, and the superposition of the drain currents of the over-erased cells on the same bit line forms a non-negligible current, and the presence of the current consumes the programming current, which increases the programming time and is very likely to result in unsuccessful programming. To this end, in some preferred embodiments, the verifying module 2 applies a second voltage to the gates of the memory cells to be soft-programmed and applies a second negative voltage to the gates of the unselected memory cells when performing the soft programming operation of the erase verification.
Wherein the second voltage is set according to actual needs.
The second negative voltage is applied to the grid electrode of the unselected memory unit, so that the unselected memory unit is completely turned off, and extra drain current is not generated, therefore, the programming current is not consumed due to the extra drain current, and the programming efficiency and the programming success rate can be greatly improved.
Preferably, the first negative voltage and the second negative voltage are not less than-3V. Preferably, the first negative voltage and the second negative voltage are-3V.
As can be seen from the above, the nonvolatile memory erasing apparatus erases a selected memory cell; performing erase verification on the selected memory cells, applying a first voltage to the gates of the selected memory cells and applying a first negative voltage to the gates of the unselected memory cells when performing a read operation of the erase verification; therefore, the non-selected memory cells can be completely turned off, extra drain current can not be generated, current judgment of other memory cells on the same bit line can not be influenced, and the actual threshold voltage of the selected memory cells can be read more accurately; therefore, the drain current of the unselected memory cells can be reduced when the nonvolatile memory is erased, so that the probability of reading the memory cells which are not successfully erased into the memory cells which are successfully erased is reduced. In addition, a second negative voltage is applied to the gates of the unselected memory cells by applying a second voltage to the gates of the memory cells needing to be subjected to soft programming when the soft programming operation of the erase verification is performed; the programming efficiency and the programming success rate can be greatly improved.
Referring to fig. 3, an electronic device 100 according to an embodiment of the present application further includes a processor 101 and a memory 102, where the memory 102 stores a computer program, and the processor 101 is configured to execute the steps of the nonvolatile memory erasing method by calling the computer program stored in the memory 102.
The processor 101 is electrically connected to the memory 102. The processor 101 is a control center of the electronic device 100, connects various parts of the entire electronic device using various interfaces and lines, and performs various functions of the electronic device and processes data by running or calling a computer program stored in the memory 102 and calling data stored in the memory 102, thereby performing overall monitoring of the electronic device.
The memory 102 may be used to store computer programs and data. The memory 102 stores computer programs containing instructions executable in the processor. The computer program may constitute various functional modules. The processor 101 executes various functional applications and data processing by calling a computer program stored in the memory 102.
In this embodiment, the processor 101 in the electronic device 100 loads instructions corresponding to one or more processes of the computer program into the memory 102, and the processor 101 runs the computer program stored in the memory 102 according to the following steps, so as to implement various functions: performing an erase operation on the selected memory cell; and carrying out erasing verification on the selected memory cells, applying a first voltage to the gates of the selected memory cells and applying a first negative voltage to the gates of the unselected memory cells when performing a read operation of the erasing verification.
In view of the above, the electronic device performs an erase operation on the selected memory cell; performing erase verification on the selected memory cells, applying a first voltage to the gates of the selected memory cells and applying a first negative voltage to the gates of the unselected memory cells when performing a read operation of the erase verification; therefore, the non-selected memory cells can be completely turned off, extra drain current can not be generated, current judgment of other memory cells on the same bit line can not be influenced, and the actual threshold voltage of the selected memory cells can be read more accurately; therefore, the drain current of the unselected memory cells can be reduced when the nonvolatile memory is erased, so that the probability of reading the memory cells which are not successfully erased into the memory cells which are successfully erased is reduced. In addition, a second negative voltage is applied to the gates of the unselected memory cells by applying a second voltage to the gates of the memory cells needing to be subjected to soft programming when the soft programming operation of the erase verification is performed; the programming efficiency and the programming success rate can be greatly improved.
An embodiment of the present application further provides a storage medium, on which a computer program is stored, where the computer program runs the steps of the above-mentioned nonvolatile memory erasing method when being executed by a processor, so as to implement the following functions: performing an erase operation on the selected memory cell; and carrying out erasing verification on the selected memory cells, applying a first voltage to the gates of the selected memory cells and applying a first negative voltage to the gates of the unselected memory cells when performing a read operation of the erasing verification.
The storage medium may be implemented by any type of volatile or nonvolatile storage device or combination thereof, such as a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic Memory, a flash Memory, a magnetic disk, or an optical disk.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, which are substantially the same as the present invention.
Claims (8)
1. A method of erasing a non-volatile memory, comprising the steps of:
A1. performing an erase operation on the selected memory cell;
A2. and carrying out erasing verification on the selected memory cells, applying a first voltage to the gates of the selected memory cells and applying a first negative voltage to the gates of the unselected memory cells when performing a read operation of the erasing verification.
2. The method of claim 1, wherein in step a2, a second voltage is applied to the gates of the memory cells to be soft-programmed and a second negative voltage is applied to the gates of the unselected memory cells during the soft programming operation of the erase verify.
3. The method of claim 2, wherein the first negative voltage and the second negative voltage are no less than-3V.
4. A non-volatile memory erasing apparatus, comprising:
the erasing module is used for erasing the selected memory unit;
and the verification module is used for carrying out erasing verification on the selected memory cells, applying a first voltage to the grid electrode of the selected memory cells when the read operation of the erasing verification is carried out, and applying a first negative voltage to the grid electrode of the unselected memory cells.
5. The apparatus of claim 4, wherein the verification module, when performing erase verification on the selected memory cell:
and applying a second voltage to the gates of the memory cells needing to be subjected to soft programming and applying a second negative voltage to the gates of the unselected memory cells when performing the soft programming operation of the erase verification.
6. The nonvolatile memory erase device of claim 5, wherein the first negative voltage and the second negative voltage are not less than-3V.
7. An electronic device, characterized in that it comprises a processor and a memory, in which a computer program is stored, said processor being adapted to carry out the steps of the non-volatile memory erasing method according to any one of claims 1-3 by calling said computer program stored in said memory.
8. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, performs the steps of the non-volatile memory erasing method of any of claims 1-3.
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