CN114005479A - Method and device for improving NOR Flash data read-write reliability and application thereof - Google Patents
Method and device for improving NOR Flash data read-write reliability and application thereof Download PDFInfo
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- CN114005479A CN114005479A CN202111303425.6A CN202111303425A CN114005479A CN 114005479 A CN114005479 A CN 114005479A CN 202111303425 A CN202111303425 A CN 202111303425A CN 114005479 A CN114005479 A CN 114005479A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
- G11C16/345—Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification
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Abstract
The invention relates to the technical field of memories, and discloses a method and a device for improving the data read-write reliability of NOR Flash and application thereof, wherein the method comprises the steps of matching a physical block array and additionally arranging an abnormal indication module, synchronously executing equal operation on an indication storage unit and continuously executing write-in and write-in verification operations when erasing, over-erasing repairing, weak write-in and verification operations are sequentially executed on a selected erasing block, and executing the verification operation on each abnormal indication module when the NOR Flash is electrified again, and executing corresponding operation according to a verification structure; the invention can effectively solve the problem that the bit line in the same physical block has electric leakage to cause the data of the storage unit to be read incorrectly due to the over-erased storage unit when the power is cut off again in the process of executing the erasing, and effectively improves the reliability of the data reading of the Flash.
Description
Technical Field
The invention relates to the technical field of memories, in particular to a method and a device for improving the data read-write reliability of NOR Flash and application thereof.
Background
With the development of semiconductor technology, flash memory has been widely used as a non-volatile memory. The flash memory has the advantages that the floating gate and the tunneling oxide layer are added on the basis of the traditional MOS transistor structure, and the floating gate is used for storing charges, so that the non-volatility of the stored content is realized.
The NOR FLASH is used as a nonvolatile FLASH memory chip, and the erasing process is to pre-write all bits in a target erasing block to 0 and then erase the target erasing block. After the erasing is finished, the operations of over-erasing repair, weak writing, verification, weak block repair and the like are carried out. This series of operations forms a complete erase flow, the process of which is shown in fig. 1. Fig. 1 is a schematic diagram of a conventional erase flow, but in an actual application process, it is likely that a power failure problem is encountered during an erase process, so that a complete erase flow cannot be completed. In order to speed up the process of the erase step, a strong erase condition is usually applied to perform the erase operation, if the power failure occurs at a stage before the over-erase repair is needed after the erase of the target block is completed, as shown in fig. 1, at the power failure, the NOR FLASH will be read after being powered on again, the Bit Line (BL) will leak because of the over-erased memory cell, and the error reading of data 0 into data 1 will occur for other memory cells of the same BL, so there is a need for improvement.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a method and a device for improving the data reading and writing reliability of NOR Flash and application thereof, which effectively solve the problem of data error reading of a storage unit possibly occurring after accidental power failure in the erasing process and effectively improve the data reading reliability of Flash.
The technical scheme adopted by the invention for solving the technical problems is as follows:
the invention provides a method for improving the data read-write reliability of NOR Flash, which comprises the following steps:
each physical block array in the NOR Flash memory area is matched with and additionally provided with an abnormality indication module, and the abnormality indication module comprises an additional bit line and a plurality of indication storage units connected with the additional bit line;
when erasing, over-erasing repair, weak writing and verification operations are sequentially performed on a selected erasing block, synchronously performing equivalent operations on an indicating storage unit which is matched and connected with the selected erasing block in an abnormal indicating module;
continuing to perform write and write verify operations on the indicated memory cell;
when the NOR Flash is electrified again, the verification operation of each abnormal indication module is executed:
if the verification is passed, the power-on step is completed and the subsequent instruction is normally received, otherwise:
and after the physical block array to which the failed abnormal indication module belongs is subjected to over-erasure repair, weak writing and verification operation, completing the power-on step and normally receiving a subsequent instruction.
Preferably, the additional bit lines and the indicating memory cells are connected in an identical configuration of bit lines and memory cells in the matching physical block array.
Preferably, the continuously performing the writing and the writing verification operation on the indication storage unit specifically includes:
programming the indicating memory cell to all 0 s and confirming that the indicating memory cell threshold voltage is greater than the standard threshold voltage.
Preferably, the executing the verification operation on each abnormal indication module specifically includes:
and judging whether the threshold voltage of the indicating storage unit is greater than the standard threshold voltage, if so, passing the verification, otherwise, failing to pass the verification.
Preferably, the erasing operation is performed on the selected erase block through a fowler-nordheim tunnel, and specifically includes:
a voltage of 8-10V is applied to all word lines in the selected erase block, while a voltage of 8-10V is applied to the P-Well of the physical block array.
The invention also provides a device for improving the data read-write reliability of the NOR Flash, which comprises a NOR Flash storage circuit, wherein the NOR Flash storage circuit comprises a plurality of physical block arrays, the physical block arrays are provided with an abnormal indication module in a matching way, the abnormal indication module comprises an additional bit line and a plurality of indication storage units connected with the additional bit line, and the additional bit line and the indication storage units are connected in an equivalent configuration way according to the bit line and the storage unit in the matched physical block array.
Preferably, the abnormality indication module is arranged in match with the physical block array and configured to perform the following operations:
when erasing, over-erasing repair, weak writing and verification operations are sequentially performed on a selected erasing block, synchronously performing equivalent operations on an indicating storage unit which is matched and connected with the selected erasing block in an abnormal indicating module;
continuing to perform write and write verification operations on the indicated memory cell, specifically:
when the indicated storage unit is programmed and written to be all 0 and the threshold voltage of the indicated storage unit is confirmed to be greater than the standard threshold voltage, when the NOR Flash is electrified again, the verification operation of each abnormal indication module is executed, specifically:
judging whether the threshold voltage of the indicating storage unit is larger than the standard threshold voltage or not;
if yes, completing the power-on step and normally receiving the subsequent instruction through verification, otherwise:
and after the physical block array to which the failed abnormal indication module belongs is subjected to over-erasure repair, weak writing and verification operation, completing the power-on step and normally receiving a subsequent instruction.
The invention also provides a Nor Flash memory circuit, which comprises the device for improving the data reading and writing reliability of the Nor Flash, and the device is arranged to execute the method for improving the data reading and writing reliability of the Nor Flash according to a preset program.
The invention also provides a chip comprising the Nor flash memory circuit.
The invention also provides an electronic device comprising the chip.
Compared with the prior art, the invention has the following beneficial effects:
the method for improving the data read-write reliability of the NOR Flash can effectively solve the problem that the BL in the same physical block has electric leakage to cause the data of the storage unit to be read wrongly due to the over-erased storage unit after the power failure happens in the erasing process and when the data is re-electrified and read, and effectively improve the data reliability of the Flash;
the method for improving the data reading and writing reliability of the NOR Flash relies on the existing physical block array and the abnormal indication module which is matched and arranged, has simple structure, good matching performance with the existing circuit, and quick operation of the whole verification operation, basically does not increase the area and complexity of the whole circuit and the power consumption of the circuit, can ensure the correctness and the high efficiency of the whole storage reading and writing, and has wide application prospect.
Further salient features and significant advances with respect to the present invention over the prior art are described in further detail in the examples section.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a conventional erase flow diagram;
FIG. 2 is a schematic structural diagram of an exception indication module and a physical block array in this embodiment;
FIG. 3 is a flowchart illustrating the verification operation performed on each abnormal indication module during the power-up process in the present embodiment;
FIG. 4 is a distribution diagram of threshold voltages of memory cells after over-erase;
FIG. 5 is a distribution diagram of threshold voltages of memory cells after over-erase repair and weak write;
fig. 6 is an erasing flowchart of the present embodiment.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that certain names are used throughout the specification and claims to refer to particular components. It will be understood that one of ordinary skill in the art may refer to the same component by different names. The present specification and claims do not intend to distinguish between components that differ in name but not function. As used in the specification and claims of this application, the terms "comprises" and "comprising" are intended to be open-ended terms that should be interpreted as "including, but not limited to," or "including, but not limited to. The embodiments described in the detailed description are preferred embodiments of the present invention and are not intended to limit the scope of the present invention.
Example 1
As shown in fig. 1-6, the present embodiment provides a method for improving the data read/write reliability of NOR Flash, and it should be noted that the same steps and parameters as those in the prior art are not described too much in the present embodiment, and those skilled in the art can select the method according to the needs, and only the contents of the adjustment and innovation design of the present invention are described in detail in the present embodiment;
referring to fig. 2, fig. 3 and fig. 6, a method for improving the data read/write reliability of NOR Flash in the present embodiment includes:
each physical block array in the NOR Flash memory area is matched with and additionally provided with an abnormality indication module, and the abnormality indication module comprises an additional bit line and a plurality of indication storage units connected with the additional bit line; the extra bit lines and the indicating storage units are connected according to the identical configuration of the bit lines and the storage units in the matched physical block array, namely, one more bit line and the corresponding storage unit are expanded outside the storage array, and the other bit lines and the indicating storage units are identical to the storage array;
when erasing, over-erasing repair, weak writing and verification operations are sequentially performed on a selected erasing block, synchronously performing equivalent operations on an indicating storage unit which is matched and connected with the selected erasing block in an abnormal indicating module;
in the present embodiment, the erase operation is performed on the selected erase block through an F-N tunneling (fowler-nordheim tunnel), and specifically includes:
applying a voltage of-8-10V to all word lines in a selected erase block while applying a voltage of 8-10V to the P-Well of the physical block array;
in the embodiment, subsequent over-erase repair, weak write and verify operations are also performed, because during the erase process, a large number of memory cells are erased together, the threshold voltage distribution of the erased memory cells is very wide, and some memory cells are over-erased to have the threshold voltage smaller than 0V, as shown in fig. 4, at this time, when the gate voltage of the over-erased memory cell is 0V, leakage current can also be detected, Nor Flash has a structure that the memory cells on the same bit line in the same physical block array share the bit line, when some memory cells on the bit line have leakage current due to over-erase, other memory cells on the bit line may erroneously read data 0 as data 1, so that the over-erase repair, weak write and verify operations are performed in the complete procedure of the Nor Flash erase, the over-erase repair, the weak write and the weak write operations, and the over-erase repair and the weak write operations are performed to weakly program the over-erased memory cells, making the threshold voltage greater than 0V, as shown in fig. 5, can effectively reduce the leakage current on the bit line.
Continuing to perform write and write verification operations on the indicated memory cell, specifically:
when the indicated storage unit is programmed and written to be all 0 and the threshold voltage of the indicated storage unit is confirmed to be greater than the standard threshold voltage, when the NOR Flash is electrified again, the verification operation of each abnormal indication module is executed, specifically:
judging whether the threshold voltage of the indicating storage unit is greater than the standard threshold voltage, if so, passing the verification, otherwise, failing to pass the verification;
if the verification is passed, the power-on step is completed and the subsequent instruction is normally received, otherwise:
and after the physical block array to which the failed abnormal indication module belongs is subjected to over-erasure repair, weak writing and verification operation, completing the power-on step and normally receiving a subsequent instruction.
More specifically, the following description:
after receiving an erase instruction on power-up of NOR Flash, as shown in FIGS. 2 and 6, the pairThe selected erase block performs erase, over-erase repair, weak write and verify, NOR Flash erases the memory area by F-N tunneling, all word lines WL0 and WL1 in the erase block add-8-10V while erase is performed, P-Well of physical block array 1 adds 8-10V, additional bit lines BLR1Indicating that Cell-R1 and Cell-R2, together with the erase block common word line and common Well, will be erased. After performing the erase operation, the memory cells Cell-R1 and Cell-R2 are instructed to perform over-erase repair, weak write and verify operations as normal memory regions. The additional bit line BLR is then1The upper indicator memory cells Cell-R1, Cell-R2 are programmed to all 0 s (standard threshold voltage of 8-12V).
As shown in fig. 3 and 6, for example, in the case of abnormal power loss during erasing of an erase block, erase repair and subsequent operations are not normally performed in erasing a selected erase block, and an additional bit line BLR1Indicating that Cell-R1 and Cell-R2 failed to be programmed to 0, the threshold voltage of indicating cells Cell-R1 and Cell-R2 would be less than the standard threshold voltage.
As shown in FIG. 4, after the chip is powered on again, the extra bit lines BLR in the physical block array 1-physical block array N are first determined1-BLRnIf the threshold voltage of the last indication memory cell is larger than the first standard threshold voltage, the additional bit line BLR is powered down abnormally in the previous erasing process1The indications above indicate that the threshold voltages of Cell-R1 and Cell-R2 are less than the standard threshold voltage, indicating that the chip was unexpectedly powered down during the last erase operation, and that the extra bit line BLR will be asserted1The physical block array 1 executes over-erase repair and subsequent verification operation, the problem that BL leakage exists in the physical block array 1 due to over-erase to cause data misreading of a storage unit is avoided, and after the operation is completed, the chip completes the power-on process and normally receives instructions.
Example 2
Referring to fig. 2 and fig. 3, the present embodiment provides an apparatus for improving data read/write reliability of NOR Flash, which includes a NOR Flash storage circuit, where the NOR Flash storage circuit includes a plurality of physical block arrays, and the physical block arraysThe column matching is provided with an abnormal indication module, which comprises an additional bit line and a plurality of indication memory cells connected with the additional bit line, such as the additional bit line BLR in FIG. 21The above indicates that Cell-R1 and Cell-R2 are both connected in a matching physical block array of bit lines and Cell equivalent configurations.
The exception indication module is arranged in a matching way with the physical block array in the embodiment and is configured to execute the following operations:
when erasing, over-erasing repair, weak writing and verification operations are sequentially performed on a selected erasing block, synchronously performing equivalent operations on an indicating storage unit which is matched and connected with the selected erasing block in an abnormal indicating module;
continuing to perform write and write verification operations on the indicated memory cell, specifically:
when the indicated storage unit is programmed and written to be all 0 and the threshold voltage of the indicated storage unit is confirmed to be greater than the standard threshold voltage, when the NOR Flash is electrified again, the verification operation of each abnormal indication module is executed, specifically:
judging whether the threshold voltage of the indicating storage unit is larger than the standard threshold voltage or not;
if yes, completing the power-on step and normally receiving the subsequent instruction through verification, otherwise:
and after the physical block array to which the failed abnormal indication module belongs is subjected to over-erasure repair, weak writing and verification operation, completing the power-on step and normally receiving a subsequent instruction.
Example 3
The embodiment provides a Nor Flash memory circuit, which comprises the device for improving the data reading and writing reliability of Nor Flash according to embodiment 2, wherein the device is configured to execute the method for improving the data reading and writing reliability of Nor Flash according to embodiment 1 according to a preset program.
Example 4
The embodiment provides a chip comprising the Nor flash memory circuit according to embodiment 3.
Example 5
The present embodiment provides an electronic device including the chip according to embodiment 4.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (10)
1. A method for improving the data read-write reliability of NOR Flash is characterized by comprising the following steps:
each physical block array in the NOR Flash memory area is matched with and additionally provided with an abnormality indication module, and the abnormality indication module comprises an additional bit line and a plurality of indication storage units connected with the additional bit line;
when erasing, over-erasing repair, weak writing and verification operations are sequentially performed on a selected erasing block, synchronously performing equivalent operations on an indicating storage unit which is matched and connected with the selected erasing block in an abnormal indicating module;
continuing to perform write and write verify operations on the indicated memory cell;
when the NOR Flash is electrified again, the verification operation of each abnormal indication module is executed:
if the verification is passed, the power-on step is completed and the subsequent instruction is normally received, otherwise:
and after the physical block array to which the failed abnormal indication module belongs is subjected to over-erasure repair, weak writing and verification operation, completing the power-on step and normally receiving a subsequent instruction.
2. The method of claim 1, wherein the extra bit lines and the indicating memory cells are connected according to the equivalent configuration of the bit lines and the memory cells in the matched physical block array.
3. The method according to claim 1, wherein the continuing of the write and write verification operations to the indication storage unit is specifically:
programming the indicating memory cell to all 0 s and confirming that the indicating memory cell threshold voltage is greater than the standard threshold voltage.
4. The method according to claim 1, wherein the performing the verification operation on each anomaly indication module specifically comprises:
and judging whether the threshold voltage of the indicating storage unit is greater than the standard threshold voltage, if so, passing the verification, otherwise, failing to pass the verification.
5. The method according to claim 1, wherein the erase operation is performed on the selected erase block through a fowler-nordheim tunnel, and specifically comprises:
a voltage of 8-10V is applied to all word lines in the selected erase block, while a voltage of 8-10V is applied to the P-Well of the physical block array.
6. The device for improving the data reading and writing reliability of the NOR Flash is characterized by comprising a NOR Flash storage circuit, wherein the NOR Flash storage circuit comprises a plurality of physical block arrays, the physical block arrays are provided with an abnormal indication module in a matching mode, the abnormal indication module comprises an additional bit line and a plurality of indication storage units connected with the additional bit line, and the additional bit line and the indication storage units are connected in an equivalent configuration mode according to the bit line and the storage unit in the matched physical block arrays.
7. The apparatus of claim 6, wherein the abnormality indication module is disposed in match with the physical block array and configured to perform the following operations:
when erasing, over-erasing repair, weak writing and verification operations are sequentially performed on a selected erasing block, synchronously performing equivalent operations on an indicating storage unit which is matched and connected with the selected erasing block in an abnormal indicating module;
continuing to perform write and write verification operations on the indicated memory cell, specifically:
when the indicated storage unit is programmed and written to be all 0 and the threshold voltage of the indicated storage unit is confirmed to be greater than the standard threshold voltage, when the NOR Flash is electrified again, the verification operation of each abnormal indication module is executed, specifically:
judging whether the threshold voltage of the indicating storage unit is larger than the standard threshold voltage or not;
if yes, completing the power-on step and normally receiving the subsequent instruction through verification, otherwise:
and after the physical block array to which the failed abnormal indication module belongs is subjected to over-erasure repair, weak writing and verification operation, completing the power-on step and normally receiving a subsequent instruction.
8. A Nor Flash memory circuit comprising means for improving the read-write reliability of Nor Flash data according to any of claims 6 to 7, the means being arranged to perform the method for improving the read-write reliability of Nor Flash data according to a predetermined program, the method comprising the steps of any of claims 1 to 5.
9. A chip comprising the Nor flash memory circuit of claim 8.
10. An electronic device comprising the chip of claim 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114758689A (en) * | 2022-04-08 | 2022-07-15 | 珠海博雅科技股份有限公司 | Erasing method and power-on repair method for nonvolatile memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114758689A (en) * | 2022-04-08 | 2022-07-15 | 珠海博雅科技股份有限公司 | Erasing method and power-on repair method for nonvolatile memory |
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